Project Settings
Project Name proj_1 Device Name imp1: Lattice LFCPNX : LFCPNX_100
Implementation Name imp1 Top Module Top
Pipelining 1 Retiming 0
Resource Sharing 1 Fanout Guide 1000
Disable I/O Insertion 0 Disable Sequential Optimizations 0
Clock Conversion 0 FSM Compiler 1

Run Status
Job Name Status CPU Time Real Time Memory Date/Time
(compiler)Complete 163 29 0 - 00m:11s - 9/5/2024
2:20 PM
(premap)Complete 5 112 0 0m:02s 0m:02s 266MB 9/5/2024
2:20 PM
(fpga_mapper)Complete 14 73 0 0m:08s 0m:08s 301MB 9/5/2024
2:20 PM
Multi-srs Generator Complete00m:01s9/5/2024
2:20 PM

Area Summary
Register bits 1044 I/O cells 5
Block RAMs (v_ram) 0 DSPs (dsp_used) 0
LUTs (total_luts) 980

Timing Summary
Clock NameReq FreqEst FreqSlack
CE_Sync_uniq_0|clko_inferred_clock1.0 MHz396.4 MHz997.477
Top|CLK1.0 MHz220.0 MHz995.456
Top|jtck_inferred_clock1.0 MHz177.8 MHz994.377
System1.0 MHz334.6 MHz997.011

Optimizations Summary
Combined Clock Conversion 3 / 0