Lattice Timing Report - Setup and Hold, Version Radiant Software (64-bit) 2023.1.1.200.1 Thu Nov 30 09:30:01 2023 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2023 Lattice Semiconductor Corporation, All rights reserved. Command line: timing -sethld -v 10 -u 10 -endpoints 10 -nperend 1 -sp 9_High-Performance_1.0V -hsp m -pwrprd -html -rpt LAB04_Async_rst.twr LAB04_Async_rst.udb -gui ------------------------------------------- Design: Top Family: LFCPNX Device: LFCPNX-100 Package: LFG672 Performance: 9_High-Performance_1.0V Package Status: Final Version 16 Performance Hardware Data Status : Final Version 3.9 ------------------------------------------- ===================================================================== Table of Contents ===================================================================== 1 DESIGN CHECKING 1.1 SDC Constraints 1.2 Constraint Coverage 1.3 Overall Summary 1.4 Unconstrained Report 1.5 Combinational Loop 2 Setup at Speed Grade 9_High-Performance_1.0V Corner at 85 Degrees 2.1 Clock Summary 2.2 Endpoint slacks 2.3 Detailed Report 3 Hold at Speed Grade m Corner at 0 Degrees 3.1 Endpoint slacks 3.2 Detailed Report ===================================================================== End of Table of Contents ===================================================================== ============================================== 1 DESIGN CHECKING ============================================== 1.1 SDC Constraints ===================== create_clock -name {clk150} -period 8.88889 [get_pins {OSCA001.OSCA_inst/HFCLKOUT }] create_clock -name {rvltck} -period 33.33 -waveform {0.000 16.665} [get_ports TCK] set_clock_groups -group [get_clocks clk150] -group [get_clocks rvltck] -asynchronous 1.2 Constraint Coverage --------------------------- Constraint Coverage: 94.842% 1.3 Overall Summary --------------------------- Setup at Speed Grade 9_High-Performance_1.0V Corner at 85 Degrees Timing Errors: 0 endpoints; Total Negative Slack: 0.000 ns Hold at Speed Grade m Corner at 0 Degrees Timing Errors: 0 endpoints; Total Negative Slack: 0.000 ns 1.4 Unconstrained Report =========================== 1.4.1 Unconstrained Start/End Points -------------------------------------- Clocked but unconstrained timing start points ------------------------------------------------------------------- Listing 3 Start Points | Type ------------------------------------------------------------------- LED3_0io.PIC_inst/Q | No required time LED2_0io.PIC_inst/Q | No required time LED1_0io.PIC_inst/Q | No required time ------------------------------------------------------------------- | Number of unconstrained timing start po | ints | 3 | ------------------------------------------------------------------- Clocked but unconstrained timing end points ------------------------------------------------------------------- Listing 4 End Points | Type ------------------------------------------------------------------- top_reveal_coretop_instance/core0/tm_u/secured_instance_1_266/DF | No arrival or required top_reveal_coretop_instance/core0/tm_u/secured_instance_1_267/DF | No arrival or required top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_475/DF | No arrival or required {RST001/Rst_Sync1_reg.ff_inst/LSR RST001/Rst_Sync.ff_inst/LSR} | No arrival time ------------------------------------------------------------------- | Number of unconstrained timing end poin | ts | 4 | ------------------------------------------------------------------- 1.4.2 Start/End Points Without Timing Constraints --------------------------------------------------- I/O ports without constraint ---------------------------- Possible constraints to use on I/O ports are: set_input_delay, set_output_delay, set_max_delay, create_clock, create_generated_clock, ... ------------------------------------------------------------------- Listing 6 Start or End Points | Type ------------------------------------------------------------------- en | input reset | input LED4 | output LED3 | output LED2 | output LED1 | output ------------------------------------------------------------------- | Number of I/O ports without constraint | 6 | ------------------------------------------------------------------- Nets without clock definition Define a clock on a top level port or a generated clock on a clock divider pin associated with this net(s). -------------------------------------------------- There is no instance satisfying reporting criteria 1.5 Combinational Loop ======================== None =============================================================== 2 Setup at Speed Grade 9_High-Performance_1.0V Corner at 85 Degrees =============================================================== 2.1 Clock Summary ======================= 2.1.1 Clock "clk150" ======================= create_clock -name {clk150} -period 8.88889 [get_pins {OSCA001.OSCA_inst/HFCLKOUT }] Single Clock Domain ------------------------------------------------------------------------------------------------------- Clock clk150 | | Period | Frequency ------------------------------------------------------------------------------------------------------- From clk150 | Target | 8.889 ns | 112.500 MHz | Actual (all paths) | 5.803 ns | 172.325 MHz OSCA001.OSCA_inst/HFCLKOUT (MPW) | (50% duty cycle) | 4.354 ns | 229.674 MHz ------------------------------------------------------------------------------------------------------- Clock Domain Crossing ------------------------------------------------------------------------------------------------------ Clock clk150 | Worst Time Between Edges | Comment ------------------------------------------------------------------------------------------------------ From rvltck | ---- | False path ------------------------------------------------------------------------------------------------------ 2.1.2 Clock "rvltck" ======================= create_clock -name {rvltck} -period 33.33 -waveform {0.000 16.665} [get_ports TCK] Single Clock Domain ------------------------------------------------------------------------------------------------------- Clock rvltck | | Period | Frequency ------------------------------------------------------------------------------------------------------- From rvltck | Target | 33.330 ns | 30.003 MHz | Actual (all paths) | 13.845 ns | 72.228 MHz jtaghub_inst/IB_inst2.bb_inst/B (MPW) | (50% duty cycle) | 5.000 ns | 200.000 MHz ------------------------------------------------------------------------------------------------------- Clock Domain Crossing ------------------------------------------------------------------------------------------------------ Clock rvltck | Worst Time Between Edges | Comment ------------------------------------------------------------------------------------------------------ From clk150 | ---- | False path ------------------------------------------------------------------------------------------------------ 2.2 Endpoint slacks ======================= ------------------------------------------------------- Listing 10 End Points | Slack ------------------------------------------------------- LED3_0io.PIC_inst/D | 3.086 ns LED1_0io.PIC_inst/D | 3.105 ns {top_reveal_coretop_instance/core0/trig_u/te_0/secured_instance_9_98/CE top_reveal_coretop_instance/core0/trig_u/te_0/secured_instance_9_95/CE} | 3.149 ns {top_reveal_coretop_instance/core0/trig_u/te_0/secured_instance_9_83/CE top_reveal_coretop_instance/core0/trig_u/te_0/secured_instance_9_85/CE} | 3.526 ns {top_reveal_coretop_instance/core0/trig_u/te_0/secured_instance_9_80/CE top_reveal_coretop_instance/core0/trig_u/te_0/secured_instance_9_82/CE} | 3.526 ns {top_reveal_coretop_instance/core0/trig_u/te_0/secured_instance_9_75/CE top_reveal_coretop_instance/core0/trig_u/te_0/secured_instance_9_77/CE} | 3.526 ns {top_reveal_coretop_instance/core0/trig_u/te_0/secured_instance_9_71/CE top_reveal_coretop_instance/core0/trig_u/te_0/secured_instance_9_73/CE} | 3.526 ns {top_reveal_coretop_instance/core0/trig_u/te_0/secured_instance_9_99/CE top_reveal_coretop_instance/core0/trig_u/te_0/secured_instance_9_101/CE} | 3.532 ns {top_reveal_coretop_instance/core0/trig_u/te_2/secured_instance_5_85/CE top_reveal_coretop_instance/core0/trig_u/te_2/secured_instance_5_86/CE} | 3.638 ns reveal_ist_128.ff_inst/DF | 3.642 ns ------------------------------------------------------- | Setup # of endpoints with negative slack:| 0 | ------------------------------------------------------- 2.3 Detailed Report ======================= XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX Detail report of critical paths XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Detailed Report for timing paths +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ ++++Path 1 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Path Begin : CNT03/Couti_reg[0].ff_inst/Q (SLICE_R60C9A) Path End : LED3_0io.PIC_inst/D (SIOLOGIC_CORE_IOL_R31A) Source Clock : clk150 (R) Destination Clock: clk150 (R) Logic Level : 2 Delay Ratio : 90.7% (route), 9.3% (logic) Clock Skew : 0.084 ns Setup Constraint : 8.888 ns Path Slack : 3.085 ns (Passed) Source Clock Path Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- ------------------------ ------------- -------- --------------------- ------ OSCA001.OSCA_inst/HFCLKOUT OSC_CORE_OSC_CORE_R1C137 CLOCK LATENCY 0.000 0.000 344 top_reveal_coretop_instance/core0/tm_u/secured_instance_1_101/secured_signal_0_143 NET DELAY 2.427 2.427 344 CNT03/Couti_reg[0].ff_inst/CLK 0.000 2.427 1 Data Path Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- ------------------------ ------------- -------- --------------------- ------ CNT03/Couti_reg[0].ff_inst/CLK->CNT03/Couti_reg[0].ff_inst/Q SLICE_R60C9A REG_DEL 0.307 2.734 5 top_reveal_coretop_instance/core0/tm_u/secured_signal_1_72 NET DELAY 2.411 5.145 5 LED3_1_cZ/A->LED3_1_cZ/Z SLICE_R35C62B CTOF_DEL 0.213 5.358 1 LED3_1 NET DELAY 2.662 8.020 1 LED3_0io.PIC_inst/D 0.000 8.020 1 Destination Clock Path Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- ------------------------ ------------- -------- --------------------- ------ CONSTRAINT 0.000 8.888 1 OSCA001.OSCA_inst/HFCLKOUT OSC_CORE_OSC_CORE_R1C137 CLOCK LATENCY 0.000 8.888 344 top_reveal_coretop_instance/core0/tm_u/secured_instance_1_101/secured_signal_0_143 NET DELAY 2.511 11.399 344 LED3_0io.PIC_inst/CLK 0.000 11.399 1 Uncertainty -(0.000) 11.399 Setup time -(0.294) 11.105 ---------------------------------------- ------------------------ ------------- -------- --------------------- ------ Required Time 11.105 Arrival Time -(8.019) ---------------------------------------- ------------------------ ------------- -------- --------------------- ------ Path Slack (Passed) 3.085 ++++ Path 2 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Path Begin : CNT01/Couti_reg[0].ff_inst/Q (SLICE_R14C12A) Path End : LED1_0io.PIC_inst/D (SIOLOGIC_CORE_IOL_R28B) Source Clock : clk150 (R) Destination Clock: clk150 (R) Logic Level : 2 Delay Ratio : 90.7% (route), 9.3% (logic) Clock Skew : 0.084 ns Setup Constraint : 8.888 ns Path Slack : 3.104 ns (Passed) Source Clock Path Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- ------------------------ ------------- -------- --------------------- ------ OSCA001.OSCA_inst/HFCLKOUT OSC_CORE_OSC_CORE_R1C137 CLOCK LATENCY 0.000 0.000 344 top_reveal_coretop_instance/core0/tm_u/secured_instance_1_101/secured_signal_0_143 NET DELAY 2.427 2.427 344 CNT01/Couti_reg[0].ff_inst/CLK 0.000 2.427 1 Data Path Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- ------------------------ ------------- -------- --------------------- ------ CNT01/Couti_reg[0].ff_inst/CLK->CNT01/Couti_reg[0].ff_inst/Q SLICE_R14C12A REG_DEL 0.307 2.734 5 top_reveal_coretop_instance/core0/tm_u/secured_signal_1_40 NET DELAY 2.206 4.940 5 LED1_1_cZ/A->LED1_1_cZ/Z SLICE_R33C67D CTOF_DEL 0.213 5.153 1 LED1_1 NET DELAY 2.848 8.001 1 LED1_0io.PIC_inst/D 0.000 8.001 1 Destination Clock Path Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- ------------------------ ------------- -------- --------------------- ------ CONSTRAINT 0.000 8.888 1 OSCA001.OSCA_inst/HFCLKOUT OSC_CORE_OSC_CORE_R1C137 CLOCK LATENCY 0.000 8.888 344 top_reveal_coretop_instance/core0/tm_u/secured_instance_1_101/secured_signal_0_143 NET DELAY 2.511 11.399 344 LED1_0io.PIC_inst/CLK 0.000 11.399 1 Uncertainty -(0.000) 11.399 Setup time -(0.294) 11.105 ---------------------------------------- ------------------------ ------------- -------- --------------------- ------ Required Time 11.105 Arrival Time -(8.000) ---------------------------------------- ------------------------ ------------- -------- --------------------- ------ Path Slack (Passed) 3.104 ++++ Path 3 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Path Begin : top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_478/Q (SLICE_R45C52B) Path End : {top_reveal_coretop_instance/core0/trig_u/te_0/secured_instance_9_98/CE top_reveal_coretop_instance/core0/trig_u/te_0/secured_instance_9_95/CE} (SLICE_R42C54B) Source Clock : clk150 (R) Destination Clock: clk150 (R) Logic Level : 7 Delay Ratio : 71.4% (route), 28.6% (logic) Clock Skew : 0.000 ns Setup Constraint : 8.888 ns Path Slack : 3.148 ns (Passed) Source Clock Path Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- ------------------------ ------------- -------- --------------------- ------ OSCA001.OSCA_inst/HFCLKOUT OSC_CORE_OSC_CORE_R1C137 CLOCK LATENCY 0.000 0.000 344 top_reveal_coretop_instance/core0/tm_u/secured_instance_1_101/secured_signal_0_143 NET DELAY 2.427 2.427 344 {top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_477/CLK top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_478/CLK} 0.000 2.427 1 Data Path Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- ------------------------ ------------- -------- --------------------- ------ top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_478/CLK->top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_478/Q SLICE_R45C52B REG_DEL 0.307 2.734 4 top_reveal_coretop_instance/core0/jtag_int_u/secured_signal_2_156 NET DELAY 0.246 2.980 4 top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_248/C->top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_248/Z SLICE_R45C52B CTOF_DEL 0.213 3.193 1 top_reveal_coretop_instance/core0/jtag_int_u/secured_signal_2_579 NET DELAY 0.274 3.467 1 top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_234/C->top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_234/Z SLICE_R44C52B CTOF_DEL 0.213 3.680 6 top_reveal_coretop_instance/core0/tm_u/secured_signal_1_159 NET DELAY 0.752 4.432 6 top_reveal_coretop_instance/core0/trig_u/decode_u/secured_instance_16_18/B->top_reveal_coretop_instance/core0/trig_u/decode_u/secured_instance_16_18/Z SLICE_R34C50A CTOF_DEL 0.213 4.645 4 top_reveal_coretop_instance/core0/trig_u/decode_u/secured_signal_16_27 NET DELAY 0.596 5.241 4 top_reveal_coretop_instance/core0/trig_u/decode_u/secured_instance_16_5/A->top_reveal_coretop_instance/core0/trig_u/decode_u/secured_instance_16_5/Z SLICE_R42C52B CTOF_DEL 0.213 5.454 4 top_reveal_coretop_instance/core0/trig_u/decode_u/secured_signal_16_28 NET DELAY 0.721 6.175 4 top_reveal_coretop_instance/core0/trig_u/decode_u/secured_instance_16_2/B->top_reveal_coretop_instance/core0/trig_u/decode_u/secured_instance_16_2/Z SLICE_R38C51C CTOF_DEL 0.213 6.388 5 top_reveal_coretop_instance/core0/trig_u/te_0/secured_signal_9_35 NET DELAY 0.457 6.845 5 top_reveal_coretop_instance/core0/trig_u/te_0/secured_instance_9_20/C->top_reveal_coretop_instance/core0/trig_u/te_0/secured_instance_9_20/Z SLICE_R36C52C CTOF_DEL 0.213 7.058 8 top_reveal_coretop_instance/core0/trig_u/te_0/secured_signal_9_137 NET DELAY 0.916 7.974 8 {top_reveal_coretop_instance/core0/trig_u/te_0/secured_instance_9_98/CE top_reveal_coretop_instance/core0/trig_u/te_0/secured_instance_9_95/CE} 0.000 7.974 1 Destination Clock Path Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- ------------------------ ------------- -------- --------------------- ------ CONSTRAINT 0.000 8.888 1 OSCA001.OSCA_inst/HFCLKOUT OSC_CORE_OSC_CORE_R1C137 CLOCK LATENCY 0.000 8.888 344 top_reveal_coretop_instance/core0/tm_u/secured_instance_1_101/secured_signal_0_143 NET DELAY 2.427 11.315 344 {top_reveal_coretop_instance/core0/trig_u/te_0/secured_instance_9_98/CLK top_reveal_coretop_instance/core0/trig_u/te_0/secured_instance_9_95/CLK} 0.000 11.315 1 Uncertainty -(0.000) 11.315 Setup time -(0.193) 11.122 ---------------------------------------- ------------------------ ------------- -------- --------------------- ------ Required Time 11.122 Arrival Time -(7.973) ---------------------------------------- ------------------------ ------------- -------- --------------------- ------ Path Slack (Passed) 3.148 ++++ Path 4 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Path Begin : top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_478/Q (SLICE_R45C52B) Path End : {top_reveal_coretop_instance/core0/trig_u/te_0/secured_instance_9_83/CE top_reveal_coretop_instance/core0/trig_u/te_0/secured_instance_9_85/CE} (SLICE_R32C50C) Source Clock : clk150 (R) Destination Clock: clk150 (R) Logic Level : 7 Delay Ratio : 69.3% (route), 30.7% (logic) Clock Skew : 0.000 ns Setup Constraint : 8.888 ns Path Slack : 3.525 ns (Passed) Source Clock Path Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- ------------------------ ------------- -------- --------------------- ------ OSCA001.OSCA_inst/HFCLKOUT OSC_CORE_OSC_CORE_R1C137 CLOCK LATENCY 0.000 0.000 344 top_reveal_coretop_instance/core0/tm_u/secured_instance_1_101/secured_signal_0_143 NET DELAY 2.427 2.427 344 {top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_477/CLK top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_478/CLK} 0.000 2.427 1 Data Path Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- ------------------------ ------------- -------- --------------------- ------ top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_478/CLK->top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_478/Q SLICE_R45C52B REG_DEL 0.307 2.734 4 top_reveal_coretop_instance/core0/jtag_int_u/secured_signal_2_156 NET DELAY 0.246 2.980 4 top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_248/C->top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_248/Z SLICE_R45C52B CTOF_DEL 0.213 3.193 1 top_reveal_coretop_instance/core0/jtag_int_u/secured_signal_2_579 NET DELAY 0.274 3.467 1 top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_234/C->top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_234/Z SLICE_R44C52B CTOF_DEL 0.213 3.680 6 top_reveal_coretop_instance/core0/tm_u/secured_signal_1_159 NET DELAY 0.752 4.432 6 top_reveal_coretop_instance/core0/trig_u/decode_u/secured_instance_16_18/B->top_reveal_coretop_instance/core0/trig_u/decode_u/secured_instance_16_18/Z SLICE_R34C50A CTOF_DEL 0.213 4.645 4 top_reveal_coretop_instance/core0/trig_u/decode_u/secured_signal_16_27 NET DELAY 0.596 5.241 4 top_reveal_coretop_instance/core0/trig_u/decode_u/secured_instance_16_5/A->top_reveal_coretop_instance/core0/trig_u/decode_u/secured_instance_16_5/Z SLICE_R42C52B CTOF_DEL 0.213 5.454 4 top_reveal_coretop_instance/core0/trig_u/decode_u/secured_signal_16_28 NET DELAY 0.721 6.175 4 top_reveal_coretop_instance/core0/trig_u/decode_u/secured_instance_16_2/B->top_reveal_coretop_instance/core0/trig_u/decode_u/secured_instance_16_2/Z SLICE_R38C51C CTOF_DEL 0.213 6.388 5 top_reveal_coretop_instance/core0/trig_u/te_0/secured_signal_9_35 NET DELAY 0.457 6.845 5 top_reveal_coretop_instance/core0/trig_u/te_0/secured_instance_9_20/C->top_reveal_coretop_instance/core0/trig_u/te_0/secured_instance_9_20/Z SLICE_R36C52C CTOF_DEL 0.213 7.058 8 top_reveal_coretop_instance/core0/trig_u/te_0/secured_signal_9_137 NET DELAY 0.539 7.597 8 {top_reveal_coretop_instance/core0/trig_u/te_0/secured_instance_9_83/CE top_reveal_coretop_instance/core0/trig_u/te_0/secured_instance_9_85/CE} 0.000 7.597 1 Destination Clock Path Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- ------------------------ ------------- -------- --------------------- ------ CONSTRAINT 0.000 8.888 1 OSCA001.OSCA_inst/HFCLKOUT OSC_CORE_OSC_CORE_R1C137 CLOCK LATENCY 0.000 8.888 344 top_reveal_coretop_instance/core0/tm_u/secured_instance_1_101/secured_signal_0_143 NET DELAY 2.427 11.315 344 {top_reveal_coretop_instance/core0/trig_u/te_0/secured_instance_9_83/CLK top_reveal_coretop_instance/core0/trig_u/te_0/secured_instance_9_85/CLK} 0.000 11.315 1 Uncertainty -(0.000) 11.315 Setup time -(0.193) 11.122 ---------------------------------------- ------------------------ ------------- -------- --------------------- ------ Required Time 11.122 Arrival Time -(7.596) ---------------------------------------- ------------------------ ------------- -------- --------------------- ------ Path Slack (Passed) 3.525 ++++ Path 5 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Path Begin : top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_478/Q (SLICE_R45C52B) Path End : {top_reveal_coretop_instance/core0/trig_u/te_0/secured_instance_9_80/CE top_reveal_coretop_instance/core0/trig_u/te_0/secured_instance_9_82/CE} (SLICE_R32C51A) Source Clock : clk150 (R) Destination Clock: clk150 (R) Logic Level : 7 Delay Ratio : 69.3% (route), 30.7% (logic) Clock Skew : 0.000 ns Setup Constraint : 8.888 ns Path Slack : 3.525 ns (Passed) Source Clock Path Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- ------------------------ ------------- -------- --------------------- ------ OSCA001.OSCA_inst/HFCLKOUT OSC_CORE_OSC_CORE_R1C137 CLOCK LATENCY 0.000 0.000 344 top_reveal_coretop_instance/core0/tm_u/secured_instance_1_101/secured_signal_0_143 NET DELAY 2.427 2.427 344 {top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_477/CLK top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_478/CLK} 0.000 2.427 1 Data Path Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- ------------------------ ------------- -------- --------------------- ------ top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_478/CLK->top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_478/Q SLICE_R45C52B REG_DEL 0.307 2.734 4 top_reveal_coretop_instance/core0/jtag_int_u/secured_signal_2_156 NET DELAY 0.246 2.980 4 top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_248/C->top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_248/Z SLICE_R45C52B CTOF_DEL 0.213 3.193 1 top_reveal_coretop_instance/core0/jtag_int_u/secured_signal_2_579 NET DELAY 0.274 3.467 1 top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_234/C->top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_234/Z SLICE_R44C52B CTOF_DEL 0.213 3.680 6 top_reveal_coretop_instance/core0/tm_u/secured_signal_1_159 NET DELAY 0.752 4.432 6 top_reveal_coretop_instance/core0/trig_u/decode_u/secured_instance_16_18/B->top_reveal_coretop_instance/core0/trig_u/decode_u/secured_instance_16_18/Z SLICE_R34C50A CTOF_DEL 0.213 4.645 4 top_reveal_coretop_instance/core0/trig_u/decode_u/secured_signal_16_27 NET DELAY 0.596 5.241 4 top_reveal_coretop_instance/core0/trig_u/decode_u/secured_instance_16_5/A->top_reveal_coretop_instance/core0/trig_u/decode_u/secured_instance_16_5/Z SLICE_R42C52B CTOF_DEL 0.213 5.454 4 top_reveal_coretop_instance/core0/trig_u/decode_u/secured_signal_16_28 NET DELAY 0.721 6.175 4 top_reveal_coretop_instance/core0/trig_u/decode_u/secured_instance_16_2/B->top_reveal_coretop_instance/core0/trig_u/decode_u/secured_instance_16_2/Z SLICE_R38C51C CTOF_DEL 0.213 6.388 5 top_reveal_coretop_instance/core0/trig_u/te_0/secured_signal_9_35 NET DELAY 0.457 6.845 5 top_reveal_coretop_instance/core0/trig_u/te_0/secured_instance_9_20/C->top_reveal_coretop_instance/core0/trig_u/te_0/secured_instance_9_20/Z SLICE_R36C52C CTOF_DEL 0.213 7.058 8 top_reveal_coretop_instance/core0/trig_u/te_0/secured_signal_9_137 NET DELAY 0.539 7.597 8 {top_reveal_coretop_instance/core0/trig_u/te_0/secured_instance_9_80/CE top_reveal_coretop_instance/core0/trig_u/te_0/secured_instance_9_82/CE} 0.000 7.597 1 Destination Clock Path Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- ------------------------ ------------- -------- --------------------- ------ CONSTRAINT 0.000 8.888 1 OSCA001.OSCA_inst/HFCLKOUT OSC_CORE_OSC_CORE_R1C137 CLOCK LATENCY 0.000 8.888 344 top_reveal_coretop_instance/core0/tm_u/secured_instance_1_101/secured_signal_0_143 NET DELAY 2.427 11.315 344 {top_reveal_coretop_instance/core0/trig_u/te_0/secured_instance_9_80/CLK top_reveal_coretop_instance/core0/trig_u/te_0/secured_instance_9_82/CLK} 0.000 11.315 1 Uncertainty -(0.000) 11.315 Setup time -(0.193) 11.122 ---------------------------------------- ------------------------ ------------- -------- --------------------- ------ Required Time 11.122 Arrival Time -(7.596) ---------------------------------------- ------------------------ ------------- -------- --------------------- ------ Path Slack (Passed) 3.525 ++++ Path 6 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Path Begin : top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_478/Q (SLICE_R45C52B) Path End : {top_reveal_coretop_instance/core0/trig_u/te_0/secured_instance_9_75/CE top_reveal_coretop_instance/core0/trig_u/te_0/secured_instance_9_77/CE} (SLICE_R32C50D) Source Clock : clk150 (R) Destination Clock: clk150 (R) Logic Level : 7 Delay Ratio : 69.3% (route), 30.7% (logic) Clock Skew : 0.000 ns Setup Constraint : 8.888 ns Path Slack : 3.525 ns (Passed) Source Clock Path Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- ------------------------ ------------- -------- --------------------- ------ OSCA001.OSCA_inst/HFCLKOUT OSC_CORE_OSC_CORE_R1C137 CLOCK LATENCY 0.000 0.000 344 top_reveal_coretop_instance/core0/tm_u/secured_instance_1_101/secured_signal_0_143 NET DELAY 2.427 2.427 344 {top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_477/CLK top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_478/CLK} 0.000 2.427 1 Data Path Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- ------------------------ ------------- -------- --------------------- ------ top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_478/CLK->top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_478/Q SLICE_R45C52B REG_DEL 0.307 2.734 4 top_reveal_coretop_instance/core0/jtag_int_u/secured_signal_2_156 NET DELAY 0.246 2.980 4 top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_248/C->top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_248/Z SLICE_R45C52B CTOF_DEL 0.213 3.193 1 top_reveal_coretop_instance/core0/jtag_int_u/secured_signal_2_579 NET DELAY 0.274 3.467 1 top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_234/C->top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_234/Z SLICE_R44C52B CTOF_DEL 0.213 3.680 6 top_reveal_coretop_instance/core0/tm_u/secured_signal_1_159 NET DELAY 0.752 4.432 6 top_reveal_coretop_instance/core0/trig_u/decode_u/secured_instance_16_18/B->top_reveal_coretop_instance/core0/trig_u/decode_u/secured_instance_16_18/Z SLICE_R34C50A CTOF_DEL 0.213 4.645 4 top_reveal_coretop_instance/core0/trig_u/decode_u/secured_signal_16_27 NET DELAY 0.596 5.241 4 top_reveal_coretop_instance/core0/trig_u/decode_u/secured_instance_16_5/A->top_reveal_coretop_instance/core0/trig_u/decode_u/secured_instance_16_5/Z SLICE_R42C52B CTOF_DEL 0.213 5.454 4 top_reveal_coretop_instance/core0/trig_u/decode_u/secured_signal_16_28 NET DELAY 0.721 6.175 4 top_reveal_coretop_instance/core0/trig_u/decode_u/secured_instance_16_2/B->top_reveal_coretop_instance/core0/trig_u/decode_u/secured_instance_16_2/Z SLICE_R38C51C CTOF_DEL 0.213 6.388 5 top_reveal_coretop_instance/core0/trig_u/te_0/secured_signal_9_35 NET DELAY 0.457 6.845 5 top_reveal_coretop_instance/core0/trig_u/te_0/secured_instance_9_20/C->top_reveal_coretop_instance/core0/trig_u/te_0/secured_instance_9_20/Z SLICE_R36C52C CTOF_DEL 0.213 7.058 8 top_reveal_coretop_instance/core0/trig_u/te_0/secured_signal_9_137 NET DELAY 0.539 7.597 8 {top_reveal_coretop_instance/core0/trig_u/te_0/secured_instance_9_75/CE top_reveal_coretop_instance/core0/trig_u/te_0/secured_instance_9_77/CE} 0.000 7.597 1 Destination Clock Path Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- ------------------------ ------------- -------- --------------------- ------ CONSTRAINT 0.000 8.888 1 OSCA001.OSCA_inst/HFCLKOUT OSC_CORE_OSC_CORE_R1C137 CLOCK LATENCY 0.000 8.888 344 top_reveal_coretop_instance/core0/tm_u/secured_instance_1_101/secured_signal_0_143 NET DELAY 2.427 11.315 344 {top_reveal_coretop_instance/core0/trig_u/te_0/secured_instance_9_75/CLK top_reveal_coretop_instance/core0/trig_u/te_0/secured_instance_9_77/CLK} 0.000 11.315 1 Uncertainty -(0.000) 11.315 Setup time -(0.193) 11.122 ---------------------------------------- ------------------------ ------------- -------- --------------------- ------ Required Time 11.122 Arrival Time -(7.596) ---------------------------------------- ------------------------ ------------- -------- --------------------- ------ Path Slack (Passed) 3.525 ++++ Path 7 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Path Begin : top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_478/Q (SLICE_R45C52B) Path End : {top_reveal_coretop_instance/core0/trig_u/te_0/secured_instance_9_71/CE top_reveal_coretop_instance/core0/trig_u/te_0/secured_instance_9_73/CE} (SLICE_R32C51B) Source Clock : clk150 (R) Destination Clock: clk150 (R) Logic Level : 7 Delay Ratio : 69.3% (route), 30.7% (logic) Clock Skew : 0.000 ns Setup Constraint : 8.888 ns Path Slack : 3.525 ns (Passed) Source Clock Path Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- ------------------------ ------------- -------- --------------------- ------ OSCA001.OSCA_inst/HFCLKOUT OSC_CORE_OSC_CORE_R1C137 CLOCK LATENCY 0.000 0.000 344 top_reveal_coretop_instance/core0/tm_u/secured_instance_1_101/secured_signal_0_143 NET DELAY 2.427 2.427 344 {top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_477/CLK top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_478/CLK} 0.000 2.427 1 Data Path Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- ------------------------ ------------- -------- --------------------- ------ top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_478/CLK->top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_478/Q SLICE_R45C52B REG_DEL 0.307 2.734 4 top_reveal_coretop_instance/core0/jtag_int_u/secured_signal_2_156 NET DELAY 0.246 2.980 4 top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_248/C->top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_248/Z SLICE_R45C52B CTOF_DEL 0.213 3.193 1 top_reveal_coretop_instance/core0/jtag_int_u/secured_signal_2_579 NET DELAY 0.274 3.467 1 top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_234/C->top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_234/Z SLICE_R44C52B CTOF_DEL 0.213 3.680 6 top_reveal_coretop_instance/core0/tm_u/secured_signal_1_159 NET DELAY 0.752 4.432 6 top_reveal_coretop_instance/core0/trig_u/decode_u/secured_instance_16_18/B->top_reveal_coretop_instance/core0/trig_u/decode_u/secured_instance_16_18/Z SLICE_R34C50A CTOF_DEL 0.213 4.645 4 top_reveal_coretop_instance/core0/trig_u/decode_u/secured_signal_16_27 NET DELAY 0.596 5.241 4 top_reveal_coretop_instance/core0/trig_u/decode_u/secured_instance_16_5/A->top_reveal_coretop_instance/core0/trig_u/decode_u/secured_instance_16_5/Z SLICE_R42C52B CTOF_DEL 0.213 5.454 4 top_reveal_coretop_instance/core0/trig_u/decode_u/secured_signal_16_28 NET DELAY 0.721 6.175 4 top_reveal_coretop_instance/core0/trig_u/decode_u/secured_instance_16_2/B->top_reveal_coretop_instance/core0/trig_u/decode_u/secured_instance_16_2/Z SLICE_R38C51C CTOF_DEL 0.213 6.388 5 top_reveal_coretop_instance/core0/trig_u/te_0/secured_signal_9_35 NET DELAY 0.457 6.845 5 top_reveal_coretop_instance/core0/trig_u/te_0/secured_instance_9_20/C->top_reveal_coretop_instance/core0/trig_u/te_0/secured_instance_9_20/Z SLICE_R36C52C CTOF_DEL 0.213 7.058 8 top_reveal_coretop_instance/core0/trig_u/te_0/secured_signal_9_137 NET DELAY 0.539 7.597 8 {top_reveal_coretop_instance/core0/trig_u/te_0/secured_instance_9_71/CE top_reveal_coretop_instance/core0/trig_u/te_0/secured_instance_9_73/CE} 0.000 7.597 1 Destination Clock Path Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- ------------------------ ------------- -------- --------------------- ------ CONSTRAINT 0.000 8.888 1 OSCA001.OSCA_inst/HFCLKOUT OSC_CORE_OSC_CORE_R1C137 CLOCK LATENCY 0.000 8.888 344 top_reveal_coretop_instance/core0/tm_u/secured_instance_1_101/secured_signal_0_143 NET DELAY 2.427 11.315 344 {top_reveal_coretop_instance/core0/trig_u/te_0/secured_instance_9_71/CLK top_reveal_coretop_instance/core0/trig_u/te_0/secured_instance_9_73/CLK} 0.000 11.315 1 Uncertainty -(0.000) 11.315 Setup time -(0.193) 11.122 ---------------------------------------- ------------------------ ------------- -------- --------------------- ------ Required Time 11.122 Arrival Time -(7.596) ---------------------------------------- ------------------------ ------------- -------- --------------------- ------ Path Slack (Passed) 3.525 ++++ Path 8 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Path Begin : top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_478/Q (SLICE_R45C52B) Path End : {top_reveal_coretop_instance/core0/trig_u/te_0/secured_instance_9_99/CE top_reveal_coretop_instance/core0/trig_u/te_0/secured_instance_9_101/CE} (SLICE_R33C53D) Source Clock : clk150 (R) Destination Clock: clk150 (R) Logic Level : 7 Delay Ratio : 69.3% (route), 30.7% (logic) Clock Skew : 0.000 ns Setup Constraint : 8.888 ns Path Slack : 3.531 ns (Passed) Source Clock Path Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- ------------------------ ------------- -------- --------------------- ------ OSCA001.OSCA_inst/HFCLKOUT OSC_CORE_OSC_CORE_R1C137 CLOCK LATENCY 0.000 0.000 344 top_reveal_coretop_instance/core0/tm_u/secured_instance_1_101/secured_signal_0_143 NET DELAY 2.427 2.427 344 {top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_477/CLK top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_478/CLK} 0.000 2.427 1 Data Path Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- ------------------------ ------------- -------- --------------------- ------ top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_478/CLK->top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_478/Q SLICE_R45C52B REG_DEL 0.307 2.734 4 top_reveal_coretop_instance/core0/jtag_int_u/secured_signal_2_156 NET DELAY 0.246 2.980 4 top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_248/C->top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_248/Z SLICE_R45C52B CTOF_DEL 0.213 3.193 1 top_reveal_coretop_instance/core0/jtag_int_u/secured_signal_2_579 NET DELAY 0.274 3.467 1 top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_234/C->top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_234/Z SLICE_R44C52B CTOF_DEL 0.213 3.680 6 top_reveal_coretop_instance/core0/tm_u/secured_signal_1_159 NET DELAY 0.752 4.432 6 top_reveal_coretop_instance/core0/trig_u/decode_u/secured_instance_16_18/B->top_reveal_coretop_instance/core0/trig_u/decode_u/secured_instance_16_18/Z SLICE_R34C50A CTOF_DEL 0.213 4.645 4 top_reveal_coretop_instance/core0/trig_u/decode_u/secured_signal_16_27 NET DELAY 0.596 5.241 4 top_reveal_coretop_instance/core0/trig_u/decode_u/secured_instance_16_5/A->top_reveal_coretop_instance/core0/trig_u/decode_u/secured_instance_16_5/Z SLICE_R42C52B CTOF_DEL 0.213 5.454 4 top_reveal_coretop_instance/core0/trig_u/decode_u/secured_signal_16_28 NET DELAY 0.721 6.175 4 top_reveal_coretop_instance/core0/trig_u/decode_u/secured_instance_16_2/B->top_reveal_coretop_instance/core0/trig_u/decode_u/secured_instance_16_2/Z SLICE_R38C51C CTOF_DEL 0.213 6.388 5 top_reveal_coretop_instance/core0/trig_u/te_0/secured_signal_9_35 NET DELAY 0.457 6.845 5 top_reveal_coretop_instance/core0/trig_u/te_0/secured_instance_9_20/C->top_reveal_coretop_instance/core0/trig_u/te_0/secured_instance_9_20/Z SLICE_R36C52C CTOF_DEL 0.213 7.058 8 top_reveal_coretop_instance/core0/trig_u/te_0/secured_signal_9_137 NET DELAY 0.533 7.591 8 {top_reveal_coretop_instance/core0/trig_u/te_0/secured_instance_9_99/CE top_reveal_coretop_instance/core0/trig_u/te_0/secured_instance_9_101/CE} 0.000 7.591 1 Destination Clock Path Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- ------------------------ ------------- -------- --------------------- ------ CONSTRAINT 0.000 8.888 1 OSCA001.OSCA_inst/HFCLKOUT OSC_CORE_OSC_CORE_R1C137 CLOCK LATENCY 0.000 8.888 344 top_reveal_coretop_instance/core0/tm_u/secured_instance_1_101/secured_signal_0_143 NET DELAY 2.427 11.315 344 {top_reveal_coretop_instance/core0/trig_u/te_0/secured_instance_9_99/CLK top_reveal_coretop_instance/core0/trig_u/te_0/secured_instance_9_101/CLK} 0.000 11.315 1 Uncertainty -(0.000) 11.315 Setup time -(0.193) 11.122 ---------------------------------------- ------------------------ ------------- -------- --------------------- ------ Required Time 11.122 Arrival Time -(7.590) ---------------------------------------- ------------------------ ------------- -------- --------------------- ------ Path Slack (Passed) 3.531 ++++ Path 9 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Path Begin : top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_478/Q (SLICE_R45C52B) Path End : {top_reveal_coretop_instance/core0/trig_u/te_2/secured_instance_5_85/CE top_reveal_coretop_instance/core0/trig_u/te_2/secured_instance_5_86/CE} (SLICE_R35C50B) Source Clock : clk150 (R) Destination Clock: clk150 (R) Logic Level : 7 Delay Ratio : 68.7% (route), 31.3% (logic) Clock Skew : 0.000 ns Setup Constraint : 8.888 ns Path Slack : 3.637 ns (Passed) Source Clock Path Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- ------------------------ ------------- -------- --------------------- ------ OSCA001.OSCA_inst/HFCLKOUT OSC_CORE_OSC_CORE_R1C137 CLOCK LATENCY 0.000 0.000 344 top_reveal_coretop_instance/core0/tm_u/secured_instance_1_101/secured_signal_0_143 NET DELAY 2.427 2.427 344 {top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_477/CLK top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_478/CLK} 0.000 2.427 1 Data Path Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- ------------------------ ------------- -------- --------------------- ------ top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_478/CLK->top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_478/Q SLICE_R45C52B REG_DEL 0.307 2.734 4 top_reveal_coretop_instance/core0/jtag_int_u/secured_signal_2_156 NET DELAY 0.246 2.980 4 top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_248/C->top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_248/Z SLICE_R45C52B CTOF_DEL 0.213 3.193 1 top_reveal_coretop_instance/core0/jtag_int_u/secured_signal_2_579 NET DELAY 0.274 3.467 1 top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_234/C->top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_234/Z SLICE_R44C52B CTOF_DEL 0.213 3.680 6 top_reveal_coretop_instance/core0/tm_u/secured_signal_1_159 NET DELAY 0.752 4.432 6 top_reveal_coretop_instance/core0/trig_u/decode_u/secured_instance_16_18/B->top_reveal_coretop_instance/core0/trig_u/decode_u/secured_instance_16_18/Z SLICE_R34C50A CTOF_DEL 0.213 4.645 4 top_reveal_coretop_instance/core0/trig_u/decode_u/secured_signal_16_27 NET DELAY 0.596 5.241 4 top_reveal_coretop_instance/core0/trig_u/decode_u/secured_instance_16_5/A->top_reveal_coretop_instance/core0/trig_u/decode_u/secured_instance_16_5/Z SLICE_R42C52B CTOF_DEL 0.213 5.454 4 top_reveal_coretop_instance/core0/trig_u/decode_u/secured_signal_16_28 NET DELAY 0.678 6.132 4 top_reveal_coretop_instance/core0/trig_u/decode_u/secured_instance_16_0/B->top_reveal_coretop_instance/core0/trig_u/decode_u/secured_instance_16_0/Z SLICE_R38C50C CTOF_DEL 0.213 6.345 4 top_reveal_coretop_instance/core0/trig_u/te_2/secured_signal_5_20 NET DELAY 0.580 6.925 4 top_reveal_coretop_instance/core0/trig_u/te_2/secured_instance_5_27/D->top_reveal_coretop_instance/core0/trig_u/te_2/secured_instance_5_27/Z SLICE_R35C53D CTOF_DEL 0.213 7.138 1 top_reveal_coretop_instance/core0/trig_u/te_2/secured_signal_5_101 NET DELAY 0.347 7.485 1 {top_reveal_coretop_instance/core0/trig_u/te_2/secured_instance_5_85/CE top_reveal_coretop_instance/core0/trig_u/te_2/secured_instance_5_86/CE} 0.000 7.485 1 Destination Clock Path Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- ------------------------ ------------- -------- --------------------- ------ CONSTRAINT 0.000 8.888 1 OSCA001.OSCA_inst/HFCLKOUT OSC_CORE_OSC_CORE_R1C137 CLOCK LATENCY 0.000 8.888 344 top_reveal_coretop_instance/core0/tm_u/secured_instance_1_101/secured_signal_0_143 NET DELAY 2.427 11.315 344 {top_reveal_coretop_instance/core0/trig_u/te_2/secured_instance_5_85/CLK top_reveal_coretop_instance/core0/trig_u/te_2/secured_instance_5_86/CLK} 0.000 11.315 1 Uncertainty -(0.000) 11.315 Setup time -(0.193) 11.122 ---------------------------------------- ------------------------ ------------- -------- --------------------- ------ Required Time 11.122 Arrival Time -(7.484) ---------------------------------------- ------------------------ ------------- -------- --------------------- ------ Path Slack (Passed) 3.637 ++++ Path 10 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Path Begin : CNT04/Couti_reg[12].ff_inst/Q (SLICE_R40C149C) Path End : reveal_ist_128.ff_inst/DF (SLICE_R34C63D) Source Clock : clk150 (R) Destination Clock: clk150 (R) Logic Level : 5 Delay Ratio : 74.9% (route), 25.1% (logic) Clock Skew : 0.000 ns Setup Constraint : 8.888 ns Path Slack : 3.641 ns (Passed) Source Clock Path Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- ------------------------ ------------- --------- --------------------- ------ OSCA001.OSCA_inst/HFCLKOUT OSC_CORE_OSC_CORE_R1C137 CLOCK LATENCY 0.000 0.000 344 top_reveal_coretop_instance/core0/tm_u/secured_instance_1_101/secured_signal_0_143 NET DELAY 2.427 2.427 344 {CNT04/Couti_reg[11].ff_inst/CLK CNT04/Couti_reg[12].ff_inst/CLK} 0.000 2.427 1 Data Path Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- ------------------------ ------------- --------- --------------------- ------ CNT04/Couti_reg[12].ff_inst/CLK->CNT04/Couti_reg[12].ff_inst/Q SLICE_R40C149C REG_DEL 0.307 2.734 6 top_reveal_coretop_instance/core0/tm_u/secured_signal_1_76 NET DELAY 2.948 5.682 6 op_neq.un1_CNT1_0_I_15_0_RNO_0_cZ/C->op_neq.un1_CNT1_0_I_15_0_RNO_0_cZ/Z SLICE_R34C60A CTOF_DEL 0.213 5.895 1 op_neq.un1_CNT1_0_I_15_0_RNO_0 NET DELAY 0.607 6.502 1 op_neq.un1_CNT1_0_I_15_0/A1->op_neq.un1_CNT1_0_I_15_0/COUT SLICE_R33C61D C1TOFCO_DEL 0.316 6.818 1 op_neq.un1_CNT1_0_data_tmp[6] NET DELAY 0.000 6.818 1 op_neq.un1_CNT1_0_I_45_0/CIN->op_neq.un1_CNT1_0_I_45_0/S1 SLICE_R33C62A FCITOF1_DEL 0.280 7.098 1 op_neq.un1_CNT1_i NET DELAY 0.421 7.519 1 reveal_ist_1283_cZ/A->reveal_ist_1283_cZ/Z SLICE_R34C63D CTOF_DEL 0.213 7.732 1 reveal_ist_1283 NET DELAY 0.000 7.732 1 reveal_ist_128.ff_inst/DF 0.000 7.732 1 Destination Clock Path Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- ------------------------ ------------- --------- --------------------- ------ CONSTRAINT 0.000 8.888 1 OSCA001.OSCA_inst/HFCLKOUT OSC_CORE_OSC_CORE_R1C137 CLOCK LATENCY 0.000 8.888 344 top_reveal_coretop_instance/core0/tm_u/secured_instance_1_101/secured_signal_0_143 NET DELAY 2.427 11.315 344 reveal_ist_128.ff_inst/CLK 0.000 11.315 1 Uncertainty -(0.000) 11.315 Setup time -(-0.058) 11.373 ---------------------------------------- ------------------------ ------------- --------- --------------------- ------ Required Time 11.373 Arrival Time -(7.731) ---------------------------------------- ------------------------ ------------- --------- --------------------- ------ Path Slack (Passed) 3.641 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ End of Detailed Report for timing paths +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ ########################################################## =============================================================== 3 Hold at Speed Grade m Corner at 0 Degrees =============================================================== 3.1 Endpoint slacks ======================= ------------------------------------------------------- Listing 10 End Points | Slack ------------------------------------------------------- RST001/Rst_Sync.ff_inst/DF | 0.162 ns top_reveal_coretop_instance/core0/trig_u/tu_2/secured_instance_13_128/DF | 0.163 ns top_reveal_coretop_instance/core0/trig_u/tu_2/secured_instance_13_125/DF | 0.163 ns top_reveal_coretop_instance/core0/trig_u/tu_4/secured_instance_11_125/DF | 0.163 ns top_reveal_coretop_instance/core0/trig_u/tu_4/secured_instance_11_127/DF | 0.163 ns top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_494/DF | 0.163 ns top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_476/DF | 0.163 ns top_reveal_coretop_instance/core0/trig_u/tu_3/secured_instance_12_117/DF | 0.166 ns top_reveal_coretop_instance/core0/trig_u/tu_4/secured_instance_11_119/DF | 0.166 ns top_reveal_coretop_instance/core0/trig_u/tu_4/secured_instance_11_118/DF | 0.166 ns ------------------------------------------------------- | Hold # of endpoints with negative slack: | 0 | ------------------------------------------------------- 3.2 Detailed Report ======================= XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX Detail report of critical paths XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Detailed Report for timing paths +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ ++++Path 1 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Path Begin : RST001/Rst_Sync1_reg.ff_inst/Q (SLICE_R38C59B) Path End : RST001/Rst_Sync.ff_inst/DF (SLICE_R38C59B) Source Clock : clk150 (R) Destination Clock: clk150 (R) Logic Level : 1 Delay Ratio : 33.2% (route), 66.8% (logic) Clock Skew : 0.000 ns Hold Constraint : 0.000 ns Path Slack : 0.162 ns (Passed) Source Clock Path Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- ------------------------ ------------- ----- --------------------- ------ OSCA001.OSCA_inst/HFCLKOUT OSC_CORE_OSC_CORE_R1C137 CLOCK LATENCY 0.000 0.000 345 top_reveal_coretop_instance/core0/tm_u/secured_instance_1_101/secured_signal_0_143 NET DELAY 1.762 1.762 345 {RST001/Rst_Sync1_reg.ff_inst/CLK RST001/Rst_Sync.ff_inst/CLK} 0.000 1.762 1 Data Path Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- ------------------------ ------------- ----- --------------------- ------ RST001/Rst_Sync1_reg.ff_inst/CLK->RST001/Rst_Sync1_reg.ff_inst/Q SLICE_R38C59B REG_DEL 0.173 1.935 1 RST001/Rst_Sync1 NET DELAY 0.086 2.021 1 RST001/Rst_Sync.ff_inst/DF 0.000 2.021 1 Destination Clock Path Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- ------------------------ ------------- ----- --------------------- ------ CONSTRAINT 0.000 0.000 1 OSCA001.OSCA_inst/HFCLKOUT OSC_CORE_OSC_CORE_R1C137 CLOCK LATENCY 0.000 0.000 345 top_reveal_coretop_instance/core0/tm_u/secured_instance_1_101/secured_signal_0_143 NET DELAY 1.762 1.762 345 {RST001/Rst_Sync1_reg.ff_inst/CLK RST001/Rst_Sync.ff_inst/CLK} 0.000 1.762 1 Uncertainty 0.000 1.762 Hold time 0.097 1.859 ---------------------------------------- ------------------------ ------------- ----- --------------------- ------ Required Time -1.859 Arrival Time 2.021 ---------------------------------------- ------------------------ ------------- ----- --------------------- ------ Path Slack (Passed) 0.162 ++++ Path 2 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Path Begin : top_reveal_coretop_instance/core0/trig_u/tu_2/secured_instance_13_144/Q (SLICE_R36C59A) Path End : top_reveal_coretop_instance/core0/trig_u/tu_2/secured_instance_13_128/DF (SLICE_R36C59B) Source Clock : clk150 (R) Destination Clock: clk150 (R) Logic Level : 1 Delay Ratio : 33.1% (route), 66.9% (logic) Clock Skew : 0.000 ns Hold Constraint : 0.000 ns Path Slack : 0.163 ns (Passed) Source Clock Path Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- ------------------------ ------------- ----- --------------------- ------ OSCA001.OSCA_inst/HFCLKOUT OSC_CORE_OSC_CORE_R1C137 CLOCK LATENCY 0.000 0.000 345 top_reveal_coretop_instance/core0/tm_u/secured_instance_1_101/secured_signal_0_143 NET DELAY 1.762 1.762 345 {top_reveal_coretop_instance/core0/trig_u/tu_2/secured_instance_13_133/CLK top_reveal_coretop_instance/core0/trig_u/tu_2/secured_instance_13_144/CLK} 0.000 1.762 1 Data Path Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- ------------------------ ------------- ----- --------------------- ------ top_reveal_coretop_instance/core0/trig_u/tu_2/secured_instance_13_144/CLK->top_reveal_coretop_instance/core0/trig_u/tu_2/secured_instance_13_144/Q SLICE_R36C59A REG_DEL 0.174 1.936 5 top_reveal_coretop_instance/core0/trig_u/tu_2/secured_signal_13_144 NET DELAY 0.086 2.022 5 top_reveal_coretop_instance/core0/trig_u/tu_2/secured_instance_13_128/DF 0.000 2.022 1 Destination Clock Path Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- ------------------------ ------------- ----- --------------------- ------ CONSTRAINT 0.000 0.000 1 OSCA001.OSCA_inst/HFCLKOUT OSC_CORE_OSC_CORE_R1C137 CLOCK LATENCY 0.000 0.000 345 top_reveal_coretop_instance/core0/tm_u/secured_instance_1_101/secured_signal_0_143 NET DELAY 1.762 1.762 345 {top_reveal_coretop_instance/core0/trig_u/tu_2/secured_instance_13_128/CLK top_reveal_coretop_instance/core0/trig_u/tu_2/secured_instance_13_129/CLK} 0.000 1.762 1 Uncertainty 0.000 1.762 Hold time 0.097 1.859 ---------------------------------------- ------------------------ ------------- ----- --------------------- ------ Required Time -1.859 Arrival Time 2.022 ---------------------------------------- ------------------------ ------------- ----- --------------------- ------ Path Slack (Passed) 0.163 ++++ Path 3 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Path Begin : top_reveal_coretop_instance/core0/trig_u/tu_2/secured_instance_13_141/Q (SLICE_R35C59C) Path End : top_reveal_coretop_instance/core0/trig_u/tu_2/secured_instance_13_125/DF (SLICE_R35C59D) Source Clock : clk150 (R) Destination Clock: clk150 (R) Logic Level : 1 Delay Ratio : 33.1% (route), 66.9% (logic) Clock Skew : 0.000 ns Hold Constraint : 0.000 ns Path Slack : 0.163 ns (Passed) Source Clock Path Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- ------------------------ ------------- ----- --------------------- ------ OSCA001.OSCA_inst/HFCLKOUT OSC_CORE_OSC_CORE_R1C137 CLOCK LATENCY 0.000 0.000 345 top_reveal_coretop_instance/core0/tm_u/secured_instance_1_101/secured_signal_0_143 NET DELAY 1.762 1.762 345 {top_reveal_coretop_instance/core0/trig_u/tu_2/secured_instance_13_137/CLK top_reveal_coretop_instance/core0/trig_u/tu_2/secured_instance_13_141/CLK} 0.000 1.762 1 Data Path Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- ------------------------ ------------- ----- --------------------- ------ top_reveal_coretop_instance/core0/trig_u/tu_2/secured_instance_13_141/CLK->top_reveal_coretop_instance/core0/trig_u/tu_2/secured_instance_13_141/Q SLICE_R35C59C REG_DEL 0.174 1.936 5 top_reveal_coretop_instance/core0/trig_u/tu_2/secured_signal_13_141 NET DELAY 0.086 2.022 5 top_reveal_coretop_instance/core0/trig_u/tu_2/secured_instance_13_125/DF 0.000 2.022 1 Destination Clock Path Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- ------------------------ ------------- ----- --------------------- ------ CONSTRAINT 0.000 0.000 1 OSCA001.OSCA_inst/HFCLKOUT OSC_CORE_OSC_CORE_R1C137 CLOCK LATENCY 0.000 0.000 345 top_reveal_coretop_instance/core0/tm_u/secured_instance_1_101/secured_signal_0_143 NET DELAY 1.762 1.762 345 {top_reveal_coretop_instance/core0/trig_u/tu_2/secured_instance_13_124/CLK top_reveal_coretop_instance/core0/trig_u/tu_2/secured_instance_13_125/CLK} 0.000 1.762 1 Uncertainty 0.000 1.762 Hold time 0.097 1.859 ---------------------------------------- ------------------------ ------------- ----- --------------------- ------ Required Time -1.859 Arrival Time 2.022 ---------------------------------------- ------------------------ ------------- ----- --------------------- ------ Path Slack (Passed) 0.163 ++++ Path 4 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Path Begin : top_reveal_coretop_instance/core0/trig_u/tu_4/secured_instance_11_141/Q (SLICE_R40C62B) Path End : top_reveal_coretop_instance/core0/trig_u/tu_4/secured_instance_11_125/DF (SLICE_R40C62A) Source Clock : clk150 (R) Destination Clock: clk150 (R) Logic Level : 1 Delay Ratio : 33.1% (route), 66.9% (logic) Clock Skew : 0.000 ns Hold Constraint : 0.000 ns Path Slack : 0.163 ns (Passed) Source Clock Path Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- ------------------------ ------------- ----- --------------------- ------ OSCA001.OSCA_inst/HFCLKOUT OSC_CORE_OSC_CORE_R1C137 CLOCK LATENCY 0.000 0.000 345 top_reveal_coretop_instance/core0/tm_u/secured_instance_1_101/secured_signal_0_143 NET DELAY 1.762 1.762 345 {top_reveal_coretop_instance/core0/trig_u/tu_4/secured_instance_11_137/CLK top_reveal_coretop_instance/core0/trig_u/tu_4/secured_instance_11_141/CLK} 0.000 1.762 1 Data Path Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- ------------------------ ------------- ----- --------------------- ------ top_reveal_coretop_instance/core0/trig_u/tu_4/secured_instance_11_141/CLK->top_reveal_coretop_instance/core0/trig_u/tu_4/secured_instance_11_141/Q SLICE_R40C62B REG_DEL 0.174 1.936 5 top_reveal_coretop_instance/core0/trig_u/tu_4/secured_signal_11_141 NET DELAY 0.086 2.022 5 top_reveal_coretop_instance/core0/trig_u/tu_4/secured_instance_11_125/DF 0.000 2.022 1 Destination Clock Path Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- ------------------------ ------------- ----- --------------------- ------ CONSTRAINT 0.000 0.000 1 OSCA001.OSCA_inst/HFCLKOUT OSC_CORE_OSC_CORE_R1C137 CLOCK LATENCY 0.000 0.000 345 top_reveal_coretop_instance/core0/tm_u/secured_instance_1_101/secured_signal_0_143 NET DELAY 1.762 1.762 345 {top_reveal_coretop_instance/core0/trig_u/tu_4/secured_instance_11_124/CLK top_reveal_coretop_instance/core0/trig_u/tu_4/secured_instance_11_125/CLK} 0.000 1.762 1 Uncertainty 0.000 1.762 Hold time 0.097 1.859 ---------------------------------------- ------------------------ ------------- ----- --------------------- ------ Required Time -1.859 Arrival Time 2.022 ---------------------------------------- ------------------------ ------------- ----- --------------------- ------ Path Slack (Passed) 0.163 ++++ Path 5 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Path Begin : top_reveal_coretop_instance/core0/trig_u/tu_4/secured_instance_11_143/Q (SLICE_R39C63D) Path End : top_reveal_coretop_instance/core0/trig_u/tu_4/secured_instance_11_127/DF (SLICE_R39C63C) Source Clock : clk150 (R) Destination Clock: clk150 (R) Logic Level : 1 Delay Ratio : 33.1% (route), 66.9% (logic) Clock Skew : 0.000 ns Hold Constraint : 0.000 ns Path Slack : 0.163 ns (Passed) Source Clock Path Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- ------------------------ ------------- ----- --------------------- ------ OSCA001.OSCA_inst/HFCLKOUT OSC_CORE_OSC_CORE_R1C137 CLOCK LATENCY 0.000 0.000 345 top_reveal_coretop_instance/core0/tm_u/secured_instance_1_101/secured_signal_0_143 NET DELAY 1.762 1.762 345 {top_reveal_coretop_instance/core0/trig_u/tu_4/secured_instance_11_142/CLK top_reveal_coretop_instance/core0/trig_u/tu_4/secured_instance_11_143/CLK} 0.000 1.762 1 Data Path Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- ------------------------ ------------- ----- --------------------- ------ top_reveal_coretop_instance/core0/trig_u/tu_4/secured_instance_11_143/CLK->top_reveal_coretop_instance/core0/trig_u/tu_4/secured_instance_11_143/Q SLICE_R39C63D REG_DEL 0.174 1.936 5 top_reveal_coretop_instance/core0/trig_u/tu_4/secured_signal_11_143 NET DELAY 0.086 2.022 5 top_reveal_coretop_instance/core0/trig_u/tu_4/secured_instance_11_127/DF 0.000 2.022 1 Destination Clock Path Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- ------------------------ ------------- ----- --------------------- ------ CONSTRAINT 0.000 0.000 1 OSCA001.OSCA_inst/HFCLKOUT OSC_CORE_OSC_CORE_R1C137 CLOCK LATENCY 0.000 0.000 345 top_reveal_coretop_instance/core0/tm_u/secured_instance_1_101/secured_signal_0_143 NET DELAY 1.762 1.762 345 {top_reveal_coretop_instance/core0/trig_u/tu_4/secured_instance_11_126/CLK top_reveal_coretop_instance/core0/trig_u/tu_4/secured_instance_11_127/CLK} 0.000 1.762 1 Uncertainty 0.000 1.762 Hold time 0.097 1.859 ---------------------------------------- ------------------------ ------------- ----- --------------------- ------ Required Time -1.859 Arrival Time 2.022 ---------------------------------------- ------------------------ ------------- ----- --------------------- ------ Path Slack (Passed) 0.163 ++++ Path 6 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Path Begin : top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_493/Q (SLICE_R45C50C) Path End : top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_494/DF (SLICE_R45C50C) Source Clock : clk150 (R) Destination Clock: clk150 (R) Logic Level : 1 Delay Ratio : 33.1% (route), 66.9% (logic) Clock Skew : 0.000 ns Hold Constraint : 0.000 ns Path Slack : 0.163 ns (Passed) Source Clock Path Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- ------------------------ ------------- ----- --------------------- ------ OSCA001.OSCA_inst/HFCLKOUT OSC_CORE_OSC_CORE_R1C137 CLOCK LATENCY 0.000 0.000 345 top_reveal_coretop_instance/core0/tm_u/secured_instance_1_101/secured_signal_0_143 NET DELAY 1.762 1.762 345 {top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_494/CLK top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_493/CLK} 0.000 1.762 1 Data Path Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- ------------------------ ------------- ----- --------------------- ------ top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_493/CLK->top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_493/Q SLICE_R45C50C REG_DEL 0.174 1.936 2 top_reveal_coretop_instance/core0/jtag_int_u/secured_signal_2_161 NET DELAY 0.086 2.022 2 top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_494/DF 0.000 2.022 1 Destination Clock Path Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- ------------------------ ------------- ----- --------------------- ------ CONSTRAINT 0.000 0.000 1 OSCA001.OSCA_inst/HFCLKOUT OSC_CORE_OSC_CORE_R1C137 CLOCK LATENCY 0.000 0.000 345 top_reveal_coretop_instance/core0/tm_u/secured_instance_1_101/secured_signal_0_143 NET DELAY 1.762 1.762 345 {top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_494/CLK top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_493/CLK} 0.000 1.762 1 Uncertainty 0.000 1.762 Hold time 0.097 1.859 ---------------------------------------- ------------------------ ------------- ----- --------------------- ------ Required Time -1.859 Arrival Time 2.022 ---------------------------------------- ------------------------ ------------- ----- --------------------- ------ Path Slack (Passed) 0.163 ++++ Path 7 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Path Begin : top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_475/Q (SLICE_R45C53D) Path End : top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_476/DF (SLICE_R45C53D) Source Clock : clk150 (R) Destination Clock: clk150 (R) Logic Level : 1 Delay Ratio : 33.5% (route), 66.5% (logic) Clock Skew : 0.000 ns Hold Constraint : 0.000 ns Path Slack : 0.163 ns (Passed) Source Clock Path Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- ------------------------ ------------- ----- --------------------- ------ OSCA001.OSCA_inst/HFCLKOUT OSC_CORE_OSC_CORE_R1C137 CLOCK LATENCY 0.000 0.000 345 top_reveal_coretop_instance/core0/tm_u/secured_instance_1_101/secured_signal_0_143 NET DELAY 1.762 1.762 345 {top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_475/CLK top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_476/CLK} 0.000 1.762 1 Data Path Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- ------------------------ ------------- ----- --------------------- ------ top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_475/CLK->top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_475/Q SLICE_R45C53D REG_DEL 0.173 1.935 1 top_reveal_coretop_instance/core0/jtag_int_u/secured_signal_2_159 NET DELAY 0.087 2.022 1 top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_476/DF 0.000 2.022 1 Destination Clock Path Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- ------------------------ ------------- ----- --------------------- ------ CONSTRAINT 0.000 0.000 1 OSCA001.OSCA_inst/HFCLKOUT OSC_CORE_OSC_CORE_R1C137 CLOCK LATENCY 0.000 0.000 345 top_reveal_coretop_instance/core0/tm_u/secured_instance_1_101/secured_signal_0_143 NET DELAY 1.762 1.762 345 {top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_475/CLK top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_476/CLK} 0.000 1.762 1 Uncertainty 0.000 1.762 Hold time 0.097 1.859 ---------------------------------------- ------------------------ ------------- ----- --------------------- ------ Required Time -1.859 Arrival Time 2.022 ---------------------------------------- ------------------------ ------------- ----- --------------------- ------ Path Slack (Passed) 0.163 ++++ Path 8 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Path Begin : top_reveal_coretop_instance/core0/trig_u/tu_3/secured_instance_12_133/Q (SLICE_R45C58C) Path End : top_reveal_coretop_instance/core0/trig_u/tu_3/secured_instance_12_117/DF (SLICE_R45C58D) Source Clock : clk150 (R) Destination Clock: clk150 (R) Logic Level : 1 Delay Ratio : 34.2% (route), 65.8% (logic) Clock Skew : 0.000 ns Hold Constraint : 0.000 ns Path Slack : 0.166 ns (Passed) Source Clock Path Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- ------------------------ ------------- ----- --------------------- ------ OSCA001.OSCA_inst/HFCLKOUT OSC_CORE_OSC_CORE_R1C137 CLOCK LATENCY 0.000 0.000 345 top_reveal_coretop_instance/core0/tm_u/secured_instance_1_101/secured_signal_0_143 NET DELAY 1.762 1.762 345 top_reveal_coretop_instance/core0/trig_u/tu_3/secured_instance_12_133/CLK 0.000 1.762 1 Data Path Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- ------------------------ ------------- ----- --------------------- ------ top_reveal_coretop_instance/core0/trig_u/tu_3/secured_instance_12_133/CLK->top_reveal_coretop_instance/core0/trig_u/tu_3/secured_instance_12_133/Q SLICE_R45C58C REG_DEL 0.173 1.935 5 top_reveal_coretop_instance/core0/trig_u/tu_3/secured_signal_12_133 NET DELAY 0.090 2.025 5 top_reveal_coretop_instance/core0/trig_u/tu_3/secured_instance_12_117/DF 0.000 2.025 1 Destination Clock Path Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- ------------------------ ------------- ----- --------------------- ------ CONSTRAINT 0.000 0.000 1 OSCA001.OSCA_inst/HFCLKOUT OSC_CORE_OSC_CORE_R1C137 CLOCK LATENCY 0.000 0.000 345 top_reveal_coretop_instance/core0/tm_u/secured_instance_1_101/secured_signal_0_143 NET DELAY 1.762 1.762 345 {top_reveal_coretop_instance/core0/trig_u/tu_3/secured_instance_12_116/CLK top_reveal_coretop_instance/core0/trig_u/tu_3/secured_instance_12_117/CLK} 0.000 1.762 1 Uncertainty 0.000 1.762 Hold time 0.097 1.859 ---------------------------------------- ------------------------ ------------- ----- --------------------- ------ Required Time -1.859 Arrival Time 2.025 ---------------------------------------- ------------------------ ------------- ----- --------------------- ------ Path Slack (Passed) 0.166 ++++ Path 9 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Path Begin : top_reveal_coretop_instance/core0/trig_u/tu_4/secured_instance_11_135/Q (SLICE_R40C63B) Path End : top_reveal_coretop_instance/core0/trig_u/tu_4/secured_instance_11_119/DF (SLICE_R40C63C) Source Clock : clk150 (R) Destination Clock: clk150 (R) Logic Level : 1 Delay Ratio : 34.2% (route), 65.8% (logic) Clock Skew : 0.000 ns Hold Constraint : 0.000 ns Path Slack : 0.166 ns (Passed) Source Clock Path Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- ------------------------ ------------- ----- --------------------- ------ OSCA001.OSCA_inst/HFCLKOUT OSC_CORE_OSC_CORE_R1C137 CLOCK LATENCY 0.000 0.000 345 top_reveal_coretop_instance/core0/tm_u/secured_instance_1_101/secured_signal_0_143 NET DELAY 1.762 1.762 345 {top_reveal_coretop_instance/core0/trig_u/tu_4/secured_instance_11_135/CLK top_reveal_coretop_instance/core0/trig_u/tu_4/secured_instance_11_140/CLK} 0.000 1.762 1 Data Path Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- ------------------------ ------------- ----- --------------------- ------ top_reveal_coretop_instance/core0/trig_u/tu_4/secured_instance_11_135/CLK->top_reveal_coretop_instance/core0/trig_u/tu_4/secured_instance_11_135/Q SLICE_R40C63B REG_DEL 0.173 1.935 5 top_reveal_coretop_instance/core0/trig_u/tu_4/secured_signal_11_135 NET DELAY 0.090 2.025 5 top_reveal_coretop_instance/core0/trig_u/tu_4/secured_instance_11_119/DF 0.000 2.025 1 Destination Clock Path Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- ------------------------ ------------- ----- --------------------- ------ CONSTRAINT 0.000 0.000 1 OSCA001.OSCA_inst/HFCLKOUT OSC_CORE_OSC_CORE_R1C137 CLOCK LATENCY 0.000 0.000 345 top_reveal_coretop_instance/core0/tm_u/secured_instance_1_101/secured_signal_0_143 NET DELAY 1.762 1.762 345 {top_reveal_coretop_instance/core0/trig_u/tu_4/secured_instance_11_118/CLK top_reveal_coretop_instance/core0/trig_u/tu_4/secured_instance_11_119/CLK} 0.000 1.762 1 Uncertainty 0.000 1.762 Hold time 0.097 1.859 ---------------------------------------- ------------------------ ------------- ----- --------------------- ------ Required Time -1.859 Arrival Time 2.025 ---------------------------------------- ------------------------ ------------- ----- --------------------- ------ Path Slack (Passed) 0.166 ++++ Path 10 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Path Begin : top_reveal_coretop_instance/core0/trig_u/tu_4/secured_instance_11_134/Q (SLICE_R40C63D) Path End : top_reveal_coretop_instance/core0/trig_u/tu_4/secured_instance_11_118/DF (SLICE_R40C63C) Source Clock : clk150 (R) Destination Clock: clk150 (R) Logic Level : 1 Delay Ratio : 34.2% (route), 65.8% (logic) Clock Skew : 0.000 ns Hold Constraint : 0.000 ns Path Slack : 0.166 ns (Passed) Source Clock Path Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- ------------------------ ------------- ----- --------------------- ------ OSCA001.OSCA_inst/HFCLKOUT OSC_CORE_OSC_CORE_R1C137 CLOCK LATENCY 0.000 0.000 345 top_reveal_coretop_instance/core0/tm_u/secured_instance_1_101/secured_signal_0_143 NET DELAY 1.762 1.762 345 top_reveal_coretop_instance/core0/trig_u/tu_4/secured_instance_11_134/CLK 0.000 1.762 1 Data Path Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- ------------------------ ------------- ----- --------------------- ------ top_reveal_coretop_instance/core0/trig_u/tu_4/secured_instance_11_134/CLK->top_reveal_coretop_instance/core0/trig_u/tu_4/secured_instance_11_134/Q SLICE_R40C63D REG_DEL 0.173 1.935 5 top_reveal_coretop_instance/core0/trig_u/tu_4/secured_signal_11_134 NET DELAY 0.090 2.025 5 top_reveal_coretop_instance/core0/trig_u/tu_4/secured_instance_11_118/DF 0.000 2.025 1 Destination Clock Path Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- ------------------------ ------------- ----- --------------------- ------ CONSTRAINT 0.000 0.000 1 OSCA001.OSCA_inst/HFCLKOUT OSC_CORE_OSC_CORE_R1C137 CLOCK LATENCY 0.000 0.000 345 top_reveal_coretop_instance/core0/tm_u/secured_instance_1_101/secured_signal_0_143 NET DELAY 1.762 1.762 345 {top_reveal_coretop_instance/core0/trig_u/tu_4/secured_instance_11_118/CLK top_reveal_coretop_instance/core0/trig_u/tu_4/secured_instance_11_119/CLK} 0.000 1.762 1 Uncertainty 0.000 1.762 Hold time 0.097 1.859 ---------------------------------------- ------------------------ ------------- ----- --------------------- ------ Required Time -1.859 Arrival Time 2.025 ---------------------------------------- ------------------------ ------------- ----- --------------------- ------ Path Slack (Passed) 0.166 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ End of Detailed Report for timing paths +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ ##########################################################