Timing Report
Lattice Timing Report - Setup and Hold, Version Radiant Software (64-bit) 2024.1.0.34.2
Thu Sep 5 16:06:22 2024
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2024 Lattice Semiconductor Corporation, All rights reserved.
Command line: timing -sethld -v 10 -u 10 -endpoints 10 -nperend 1 -sp 9_High-Performance_1.0V -hsp m -pwrprd -html -rpt LAB03_Async_rst.twr LAB03_Async_rst.udb -gui -msgset C:/Users/qnoor/Downloads/LAB03_Sync_rst/LAB03_Sync_rst/promote.xml
-------------------------------------------
Design: Top
Family: LFCPNX
Device: LFCPNX-100
Package: LFG672
Performance: 9_High-Performance_1.0V
Package Status: Final Version 16
Performance Hardware Data Status : Final Version 3.9
-------------------------------------------
=====================================================================
Table of Contents
=====================================================================
1 Timing Overview
1.1 SDC Constraints
1.2 Constraint Coverage
1.3 Overall Summary
1.4 Unconstrained Report
1.5 Combinational Loop
2 Setup at Speed Grade 9_High-Performance_1.0V Corner at 100 Degrees
2.1 Clock Summary
2.2 Endpoint slacks
2.3 Detailed Report
3 Setup at Speed Grade 9_High-Performance_1.0V Corner at -40 Degrees
3.1 Clock Summary
3.2 Endpoint slacks
3.3 Detailed Report
4 Hold at Speed Grade m Corner at -40 Degrees
4.1 Endpoint slacks
4.2 Detailed Report
=====================================================================
End of Table of Contents
=====================================================================
1 Timing Overview
1.1 SDC Constraints
create_clock -name {clk150} -period 8.88889 [get_pins {OSCA001.OSCA_inst/HFCLKOUT }]
create_clock -name {rvltck} -period 33.33 [get_ports TCK]
set_false_path -to [get_clocks rvltck]
set_false_path -from [get_clocks rvltck]
create_generated_clock -name {rvjtck} -source [get_ports TCK] [get_nets jtck]
set_false_path -to [get_clocks rvjtck]
set_false_path -from [get_clocks rvjtck]
set_clock_groups -group [get_clocks clk150] -group [get_clocks rvltck] -asynchronous
1.2 Constraint Coverage
Constraint Coverage: 99.7741%
1.3 Overall Summary
Setup at Speed Grade 9_High-Performance_1.0V Corner at 100 Degrees Timing Errors: 0 endpoints; Total Negative Slack: 0.000 ns
Setup at Speed Grade 9_High-Performance_1.0V Corner at -40 Degrees Timing Errors: 0 endpoints; Total Negative Slack: 0.000 ns
Hold at Speed Grade m Corner at -40 Degrees Timing Errors: 0 endpoints; Total Negative Slack: 0.000 ns
1.4 Unconstrained Report
1.4.1 Unconstrained Start/End Points
Clocked but unconstrained timing start points
-------------------------------------------------------------------
Listing 4 Start Points | Type
-------------------------------------------------------------------
LED4_0io.PIC_inst/Q | No required time
LED3_0io.PIC_inst/Q | No required time
LED2_0io.PIC_inst/Q | No required time
LED1_0io.PIC_inst/Q | No required time
-------------------------------------------------------------------
|
Number of unconstrained timing start po |
ints | 4
|
-------------------------------------------------------------------
Clocked but unconstrained timing end points
-------------------------------------------------------------------
Listing 1 End Points | Type
-------------------------------------------------------------------
rsti_0io.PIC_inst/D | No arrival time
-------------------------------------------------------------------
|
Number of unconstrained timing end poin |
ts | 1
|
-------------------------------------------------------------------
1.4.2 Start/End Points Without Timing Constraints
I/O ports without constraint
----------------------------
Possible constraints to use on I/O ports are:
set_input_delay,
set_output_delay,
set_max_delay,
create_clock,
create_generated_clock,
...
-------------------------------------------------------------------
Listing 6 Start or End Points | Type
-------------------------------------------------------------------
en | input
reset | input
LED4 | output
LED3 | output
LED2 | output
LED1 | output
-------------------------------------------------------------------
|
Number of I/O ports without constraint | 6
|
-------------------------------------------------------------------
Nets without clock definition
Define a clock on a top level port or a generated clock on a clock divider pin associated with this net(s).
--------------------------------------------------
There is no instance satisfying reporting criteria
1.5 Combinational Loop
None
2 Setup at Speed Grade 9_High-Performance_1.0V Corner at 100 Degrees
2.1 Clock Summary
2.1.1 Clock "clk150"
create_clock -name {clk150} -period 8.88889 [get_pins {OSCA001.OSCA_inst/HFCLKOUT }]
Single Clock Domain
-------------------------------------------------------------------------------------------------------
Clock clk150 | | Period | Frequency
-------------------------------------------------------------------------------------------------------
From clk150 | Target | 8.889 ns | 112.500 MHz
| Actual (all paths) | 5.962 ns | 167.729 MHz
OSCA001.OSCA_inst/HFCLKOUT (MPW) | (50% duty cycle) | 4.358 ns | 229.463 MHz
-------------------------------------------------------------------------------------------------------
Clock Domain Crossing
------------------------------------------------------------------------------------------------------
Clock clk150 | Worst Time Between Edges | Comment
------------------------------------------------------------------------------------------------------
From rvltck | ---- | False path
From rvjtck | ---- | False path
------------------------------------------------------------------------------------------------------
2.1.2 Clock "rvltck"
create_clock -name {rvltck} -period 33.33 [get_ports TCK]
Single Clock Domain
-------------------------------------------------------------------------------------------------------
Clock rvltck | | Period | Frequency
-------------------------------------------------------------------------------------------------------
From rvltck | Target | 33.330 ns | 30.003 MHz
| Actual (all paths) | 5.000 ns | 200.000 MHz
jtaghub_inst/IB_inst2.bb_inst/B (MPW) | (50% duty cycle) | 5.000 ns | 200.000 MHz
-------------------------------------------------------------------------------------------------------
Clock Domain Crossing
------------------------------------------------------------------------------------------------------
Clock rvltck | Worst Time Between Edges | Comment
------------------------------------------------------------------------------------------------------
From clk150 | ---- | False path
From rvjtck | ---- | False path
------------------------------------------------------------------------------------------------------
2.1.3 Clock "rvjtck"
create_generated_clock -name {rvjtck} -source [get_ports TCK] [get_nets jtck]
Single Clock Domain
-------------------------------------------------------------------------------------------------------
Clock rvjtck | | Period | Frequency
-------------------------------------------------------------------------------------------------------
From rvjtck | Target | 33.330 ns | 30.003 MHz
| Actual (all paths) | 2.920 ns | 342.466 MHz
top_reveal_coretop_instance/core0/tm_u/secured_instance_1_105/secured_instance_0_65/CLKR (MPW)
| (50% duty cycle) | 2.920 ns | 342.466 MHz
-------------------------------------------------------------------------------------------------------
Clock Domain Crossing
------------------------------------------------------------------------------------------------------
Clock rvjtck | Worst Time Between Edges | Comment
------------------------------------------------------------------------------------------------------
From clk150 | ---- | False path
From rvltck | ---- | False path
------------------------------------------------------------------------------------------------------
2.2 Endpoint slacks
-------------------------------------------------------
Listing 10 End Points | Slack
-------------------------------------------------------
LED3_0io.PIC_inst/D | 2.927 ns
LED1_0io.PIC_inst/D | 2.996 ns
CNT03/Couti_reg[0].ff_inst/LSR | 3.161 ns
{CNT03/Couti_reg[1].ff_inst/LSR CNT03/Couti_reg[2].ff_inst/LSR}
| 3.161 ns
{CNT03/Couti_reg[3].ff_inst/LSR CNT03/Couti_reg[4].ff_inst/LSR}
| 3.161 ns
{CNT03/Couti_reg[5].ff_inst/LSR CNT03/Couti_reg[6].ff_inst/LSR}
| 3.161 ns
{CNT03/Couti_reg[7].ff_inst/LSR CNT03/Couti_reg[8].ff_inst/LSR}
| 3.206 ns
{CNT03/Couti_reg[9].ff_inst/LSR CNT03/Couti_reg[10].ff_inst/LSR}
| 3.206 ns
{CNT03/Couti_reg[11].ff_inst/LSR CNT03/Couti_reg[12].ff_inst/LSR}
| 3.206 ns
{CNT03/Couti_reg[13].ff_inst/LSR CNT03/Couti_reg[14].ff_inst/LSR}
| 3.206 ns
-------------------------------------------------------
|
Setup # of endpoints with negative slack:| 0
|
-------------------------------------------------------
2.3 Detailed Report
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
Detail report of critical paths
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Detailed Report for timing paths
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++++Path 1 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Path Begin : CNT03/Couti_reg[15].ff_inst/Q (SLICE_R61C11A)
Path End : LED3_0io.PIC_inst/D (SIOLOGIC_CORE_IOL_R31A)
Source Clock : clk150 (R)
Destination Clock: clk150 (R)
Logic Level : 2
Delay Ratio : 90.9% (route), 9.1% (logic)
Clock Skew : -0.084 ns
Setup Constraint : 8.888 ns
Common Path Skew : 0.027 ns
Path Slack : 2.926 ns (Passed)
Source Clock Path
{
"path_begin":
{
"type":"pin",
"log_name":"OSCA001.OSCA_inst/HFCLKOUT",
"phy_name":"OSCA001.OSCA_inst/HFCLKOUT"
},
"path_end":
{
"type":"pin",
"log_name":"CNT03/Couti_reg[15].ff_inst/CLK",
"phy_name":"CNT03.un1_Couti_s_15_0/CLK"
},
"path_sections":[
{
"type":"net_delay",
"net":
{
"log_name":"top_reveal_coretop_instance/core0/tm_u/secured_instance_1_105/secured_signal_0_141",
"phy_name":"clk150"
},
"arrive":2.342,
"delay":2.342
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":2.342,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- ------------------------ ---------------- -------- --------------------- ------
OSCA001.OSCA_inst/HFCLKOUT OSC_CORE_OSC_CORE_R1C137 CLOCK LATENCY 0.000 0.000 323
top_reveal_coretop_instance/core0/tm_u/secured_instance_1_105/secured_signal_0_141
NET DELAY 2.342 2.342 323
CNT03/Couti_reg[15].ff_inst/CLK CLOCK PIN 0.000 2.342 1
Data Path
{
"path_begin":
{
"type":"pin",
"log_name":"CNT03/Couti_reg[15].ff_inst/Q",
"phy_name":"CNT03.un1_Couti_s_15_0/Q0"
},
"path_end":
{
"type":"pin",
"log_name":"LED3_0io.PIC_inst/D",
"phy_name":"LED3_pad.bb_inst_IOL/TXDATA0"
},
"path_sections":[
{
"type":"site_delay",
"pin0":
{
"log_name":"CNT03/Couti_reg[15].ff_inst/CLK",
"phy_name":"CNT03.un1_Couti_s_15_0/CLK"
},
"pin1":
{
"log_name":"CNT03/Couti_reg[15].ff_inst/Q",
"phy_name":"CNT03.un1_Couti_s_15_0/Q0"
},
"arrive":2.648,
"delay":0.306
},
{
"type":"net_delay",
"net":
{
"log_name":"top_reveal_coretop_instance/core0/tm_u/secured_signal_1_57",
"phy_name":"CNT3[15]"
},
"arrive":6.008,
"delay":3.360
},
{
"type":"site_delay",
"pin0":
{
"log_name":"LED3_1_cZ/B",
"phy_name":"LED2_1_cZ/D1"
},
"pin1":
{
"log_name":"LED3_1_cZ/Z",
"phy_name":"LED2_1_cZ/F1"
},
"arrive":6.214,
"delay":0.206
},
{
"type":"net_delay",
"net":
{
"log_name":"LED3_1",
"phy_name":"LED3_1"
},
"arrive":7.957,
"delay":1.743
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":7.957,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- ------------------------ ---------------- -------- --------------------- ------
CNT03/Couti_reg[15].ff_inst/CLK->CNT03/Couti_reg[15].ff_inst/Q
SLICE_R61C11A REG_DEL 0.306 2.648 4
top_reveal_coretop_instance/core0/tm_u/secured_signal_1_57
NET DELAY 3.360 6.008 4
LED3_1_cZ/B->LED3_1_cZ/Z SLICE_R38C112D CTOF_DEL 0.206 6.214 1
LED3_1 NET DELAY 1.743 7.957 1
LED3_0io.PIC_inst/D ENDPOINT 0.000 7.957 1
Destination Clock Path
{
"path_begin":
{
"type":"pin",
"log_name":"OSCA001.OSCA_inst/HFCLKOUT",
"phy_name":"OSCA001.OSCA_inst/HFCLKOUT"
},
"path_end":
{
"type":"pin",
"log_name":"LED3_0io.PIC_inst/CLK",
"phy_name":"LED3_pad.bb_inst_IOL/SCLKOUT"
},
"path_sections":[
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":8.888,
"delay":0.000
},
{
"type":"net_delay",
"net":
{
"log_name":"top_reveal_coretop_instance/core0/tm_u/secured_instance_1_105/secured_signal_0_141",
"phy_name":"clk150"
},
"arrive":11.146,
"delay":2.258
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":11.146,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- ------------------------ ---------------- -------- --------------------- ------
CONSTRAINT 0.000 8.888 1
OSCA001.OSCA_inst/HFCLKOUT OSC_CORE_OSC_CORE_R1C137 CLOCK LATENCY 0.000 8.888 323
top_reveal_coretop_instance/core0/tm_u/secured_instance_1_105/secured_signal_0_141
NET DELAY 2.258 11.146 323
LED3_0io.PIC_inst/CLK CLOCK PIN 0.000 11.146 1
Uncertainty -(0.000) 11.146
Common Path Skew 0.027 11.173
Setup time -(0.290) 10.883
---------------------------------------- ------------------------ ---------------- -------- --------------------- ------
Required Time 10.883
Arrival Time -(7.956)
---------------------------------------- ------------------------ ---------------- -------- --------------------- ------
Path Slack (Passed) 2.926
++++ Path 2 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Path Begin : CNT01/Couti_reg[0].ff_inst/Q (SLICE_R14C12A)
Path End : LED1_0io.PIC_inst/D (SIOLOGIC_CORE_IOL_R28B)
Source Clock : clk150 (R)
Destination Clock: clk150 (R)
Logic Level : 2
Delay Ratio : 91.0% (route), 9.0% (logic)
Clock Skew : -0.084 ns
Setup Constraint : 8.888 ns
Common Path Skew : 0.027 ns
Path Slack : 2.995 ns (Passed)
Source Clock Path
{
"path_begin":
{
"type":"pin",
"log_name":"OSCA001.OSCA_inst/HFCLKOUT",
"phy_name":"OSCA001.OSCA_inst/HFCLKOUT"
},
"path_end":
{
"type":"pin",
"log_name":"CNT01/Couti_reg[0].ff_inst/CLK",
"phy_name":"CNT01.un1_Couti_cry_0_0/CLK"
},
"path_sections":[
{
"type":"net_delay",
"net":
{
"log_name":"top_reveal_coretop_instance/core0/tm_u/secured_instance_1_105/secured_signal_0_141",
"phy_name":"clk150"
},
"arrive":2.342,
"delay":2.342
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":2.342,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- ------------------------ ---------------- -------- --------------------- ------
OSCA001.OSCA_inst/HFCLKOUT OSC_CORE_OSC_CORE_R1C137 CLOCK LATENCY 0.000 0.000 323
top_reveal_coretop_instance/core0/tm_u/secured_instance_1_105/secured_signal_0_141
NET DELAY 2.342 2.342 323
CNT01/Couti_reg[0].ff_inst/CLK CLOCK PIN 0.000 2.342 1
Data Path
{
"path_begin":
{
"type":"pin",
"log_name":"CNT01/Couti_reg[0].ff_inst/Q",
"phy_name":"CNT01.un1_Couti_cry_0_0/Q1"
},
"path_end":
{
"type":"pin",
"log_name":"LED1_0io.PIC_inst/D",
"phy_name":"LED1_pad.bb_inst_IOL/TXDATA0"
},
"path_sections":[
{
"type":"site_delay",
"pin0":
{
"log_name":"CNT01/Couti_reg[0].ff_inst/CLK",
"phy_name":"CNT01.un1_Couti_cry_0_0/CLK"
},
"pin1":
{
"log_name":"CNT01/Couti_reg[0].ff_inst/Q",
"phy_name":"CNT01.un1_Couti_cry_0_0/Q1"
},
"arrive":2.637,
"delay":0.295
},
{
"type":"net_delay",
"net":
{
"log_name":"top_reveal_coretop_instance/core0/tm_u/secured_signal_1_40",
"phy_name":"CNT1[0]"
},
"arrive":6.010,
"delay":3.373
},
{
"type":"site_delay",
"pin0":
{
"log_name":"LED1_1_cZ/A",
"phy_name":"GND_cZ/C1"
},
"pin1":
{
"log_name":"LED1_1_cZ/Z",
"phy_name":"GND_cZ/F1"
},
"arrive":6.216,
"delay":0.206
},
{
"type":"net_delay",
"net":
{
"log_name":"LED1_1",
"phy_name":"LED1_1"
},
"arrive":7.888,
"delay":1.672
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":7.888,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- ------------------------ ---------------- -------- --------------------- ------
CNT01/Couti_reg[0].ff_inst/CLK->CNT01/Couti_reg[0].ff_inst/Q
SLICE_R14C12A REG_DEL 0.295 2.637 4
top_reveal_coretop_instance/core0/tm_u/secured_signal_1_40
NET DELAY 3.373 6.010 4
LED1_1_cZ/A->LED1_1_cZ/Z SLICE_R38C117D CTOF_DEL 0.206 6.216 1
LED1_1 NET DELAY 1.672 7.888 1
LED1_0io.PIC_inst/D ENDPOINT 0.000 7.888 1
Destination Clock Path
{
"path_begin":
{
"type":"pin",
"log_name":"OSCA001.OSCA_inst/HFCLKOUT",
"phy_name":"OSCA001.OSCA_inst/HFCLKOUT"
},
"path_end":
{
"type":"pin",
"log_name":"LED1_0io.PIC_inst/CLK",
"phy_name":"LED1_pad.bb_inst_IOL/SCLKOUT"
},
"path_sections":[
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":8.888,
"delay":0.000
},
{
"type":"net_delay",
"net":
{
"log_name":"top_reveal_coretop_instance/core0/tm_u/secured_instance_1_105/secured_signal_0_141",
"phy_name":"clk150"
},
"arrive":11.146,
"delay":2.258
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":11.146,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- ------------------------ ---------------- -------- --------------------- ------
CONSTRAINT 0.000 8.888 1
OSCA001.OSCA_inst/HFCLKOUT OSC_CORE_OSC_CORE_R1C137 CLOCK LATENCY 0.000 8.888 323
top_reveal_coretop_instance/core0/tm_u/secured_instance_1_105/secured_signal_0_141
NET DELAY 2.258 11.146 323
LED1_0io.PIC_inst/CLK CLOCK PIN 0.000 11.146 1
Uncertainty -(0.000) 11.146
Common Path Skew 0.027 11.173
Setup time -(0.290) 10.883
---------------------------------------- ------------------------ ---------------- -------- --------------------- ------
Required Time 10.883
Arrival Time -(7.887)
---------------------------------------- ------------------------ ---------------- -------- --------------------- ------
Path Slack (Passed) 2.995
++++ Path 3 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Path Begin : rsti_0io.PIC_inst/Q (SIOLOGIC_CORE_IOL_R24A)
Path End : CNT03/Couti_reg[0].ff_inst/LSR (SLICE_R61C9A)
Source Clock : clk150 (R)
Destination Clock: clk150 (R)
Logic Level : 1
Delay Ratio : 92.3% (route), 7.7% (logic)
Clock Skew : -0.215 ns
Setup Constraint : 8.888 ns
Common Path Skew : 0.027 ns
Path Slack : 3.160 ns (Passed)
Source Clock Path
{
"path_begin":
{
"type":"pin",
"log_name":"OSCA001.OSCA_inst/HFCLKOUT",
"phy_name":"OSCA001.OSCA_inst/HFCLKOUT"
},
"path_end":
{
"type":"pin",
"log_name":"rsti_0io.PIC_inst/CLK",
"phy_name":"reset_pad.bb_inst_IOL/SCLKIN"
},
"path_sections":[
{
"type":"net_delay",
"net":
{
"log_name":"top_reveal_coretop_instance/core0/tm_u/secured_instance_1_105/secured_signal_0_141",
"phy_name":"clk150"
},
"arrive":2.427,
"delay":2.427
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":2.427,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- ------------------------ ---------------- -------- --------------------- ------
OSCA001.OSCA_inst/HFCLKOUT OSC_CORE_OSC_CORE_R1C137 CLOCK LATENCY 0.000 0.000 323
top_reveal_coretop_instance/core0/tm_u/secured_instance_1_105/secured_signal_0_141
NET DELAY 2.427 2.427 323
rsti_0io.PIC_inst/CLK CLOCK PIN 0.000 2.427 1
Data Path
{
"path_begin":
{
"type":"pin",
"log_name":"rsti_0io.PIC_inst/Q",
"phy_name":"reset_pad.bb_inst_IOL/INFF"
},
"path_end":
{
"type":"pin",
"log_name":"CNT03/Couti_reg[0].ff_inst/LSR",
"phy_name":"CNT03.un1_Couti_cry_0_0/LSR"
},
"path_sections":[
{
"type":"site_delay",
"pin0":
{
"log_name":"rsti_0io.PIC_inst/CLK",
"phy_name":"reset_pad.bb_inst_IOL/SCLKIN"
},
"pin1":
{
"log_name":"rsti_0io.PIC_inst/Q",
"phy_name":"reset_pad.bb_inst_IOL/INFF"
},
"arrive":2.837,
"delay":0.410
},
{
"type":"net_delay",
"net":
{
"log_name":"top_reveal_coretop_instance/core0/tm_u/secured_signal_1_89",
"phy_name":"rsti_1"
},
"arrive":7.761,
"delay":4.924
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":7.761,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- ------------------------ ---------------- -------- --------------------- ------
rsti_0io.PIC_inst/CLK->rsti_0io.PIC_inst/Q
SIOLOGIC_CORE_IOL_R24A C2INP_DEL 0.410 2.837 38
top_reveal_coretop_instance/core0/tm_u/secured_signal_1_89
NET DELAY 4.924 7.761 38
CNT03/Couti_reg[0].ff_inst/LSR ENDPOINT 0.000 7.761 1
Destination Clock Path
{
"path_begin":
{
"type":"pin",
"log_name":"OSCA001.OSCA_inst/HFCLKOUT",
"phy_name":"OSCA001.OSCA_inst/HFCLKOUT"
},
"path_end":
{
"type":"pin",
"log_name":"CNT03/Couti_reg[0].ff_inst/CLK",
"phy_name":"CNT03.un1_Couti_cry_0_0/CLK"
},
"path_sections":[
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":8.888,
"delay":0.000
},
{
"type":"net_delay",
"net":
{
"log_name":"top_reveal_coretop_instance/core0/tm_u/secured_instance_1_105/secured_signal_0_141",
"phy_name":"clk150"
},
"arrive":11.100,
"delay":2.212
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":11.100,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- ------------------------ ---------------- -------- --------------------- ------
CONSTRAINT 0.000 8.888 1
OSCA001.OSCA_inst/HFCLKOUT OSC_CORE_OSC_CORE_R1C137 CLOCK LATENCY 0.000 8.888 323
top_reveal_coretop_instance/core0/tm_u/secured_instance_1_105/secured_signal_0_141
NET DELAY 2.212 11.100 323
CNT03/Couti_reg[0].ff_inst/CLK CLOCK PIN 0.000 11.100 1
Uncertainty -(0.000) 11.100
Common Path Skew 0.027 11.127
Setup time -(0.206) 10.921
---------------------------------------- ------------------------ ---------------- -------- --------------------- ------
Required Time 10.921
Arrival Time -(7.760)
---------------------------------------- ------------------------ ---------------- -------- --------------------- ------
Path Slack (Passed) 3.160
++++ Path 4 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Path Begin : rsti_0io.PIC_inst/Q (SIOLOGIC_CORE_IOL_R24A)
Path End : {CNT03/Couti_reg[1].ff_inst/LSR CNT03/Couti_reg[2].ff_inst/LSR} (SLICE_R61C9B)
Source Clock : clk150 (R)
Destination Clock: clk150 (R)
Logic Level : 1
Delay Ratio : 92.3% (route), 7.7% (logic)
Clock Skew : -0.215 ns
Setup Constraint : 8.888 ns
Common Path Skew : 0.027 ns
Path Slack : 3.160 ns (Passed)
Source Clock Path
{
"path_begin":
{
"type":"pin",
"log_name":"OSCA001.OSCA_inst/HFCLKOUT",
"phy_name":"OSCA001.OSCA_inst/HFCLKOUT"
},
"path_end":
{
"type":"pin",
"log_name":"rsti_0io.PIC_inst/CLK",
"phy_name":"reset_pad.bb_inst_IOL/SCLKIN"
},
"path_sections":[
{
"type":"net_delay",
"net":
{
"log_name":"top_reveal_coretop_instance/core0/tm_u/secured_instance_1_105/secured_signal_0_141",
"phy_name":"clk150"
},
"arrive":2.427,
"delay":2.427
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":2.427,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- ------------------------ ---------------- -------- --------------------- ------
OSCA001.OSCA_inst/HFCLKOUT OSC_CORE_OSC_CORE_R1C137 CLOCK LATENCY 0.000 0.000 323
top_reveal_coretop_instance/core0/tm_u/secured_instance_1_105/secured_signal_0_141
NET DELAY 2.427 2.427 323
rsti_0io.PIC_inst/CLK CLOCK PIN 0.000 2.427 1
Data Path
{
"path_begin":
{
"type":"pin",
"log_name":"rsti_0io.PIC_inst/Q",
"phy_name":"reset_pad.bb_inst_IOL/INFF"
},
"path_end":
{
"type":"pin",
"log_name":"{CNT03/Couti_reg[1].ff_inst/LSR CNT03/Couti_reg[2].ff_inst/LSR}",
"phy_name":"CNT03.un1_Couti_cry_1_0/LSR"
},
"path_sections":[
{
"type":"site_delay",
"pin0":
{
"log_name":"rsti_0io.PIC_inst/CLK",
"phy_name":"reset_pad.bb_inst_IOL/SCLKIN"
},
"pin1":
{
"log_name":"rsti_0io.PIC_inst/Q",
"phy_name":"reset_pad.bb_inst_IOL/INFF"
},
"arrive":2.837,
"delay":0.410
},
{
"type":"net_delay",
"net":
{
"log_name":"top_reveal_coretop_instance/core0/tm_u/secured_signal_1_89",
"phy_name":"rsti_1"
},
"arrive":7.761,
"delay":4.924
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":7.761,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- ------------------------ ---------------- -------- --------------------- ------
rsti_0io.PIC_inst/CLK->rsti_0io.PIC_inst/Q
SIOLOGIC_CORE_IOL_R24A C2INP_DEL 0.410 2.837 38
top_reveal_coretop_instance/core0/tm_u/secured_signal_1_89
NET DELAY 4.924 7.761 38
{CNT03/Couti_reg[1].ff_inst/LSR CNT03/Couti_reg[2].ff_inst/LSR}
ENDPOINT 0.000 7.761 1
Destination Clock Path
{
"path_begin":
{
"type":"pin",
"log_name":"OSCA001.OSCA_inst/HFCLKOUT",
"phy_name":"OSCA001.OSCA_inst/HFCLKOUT"
},
"path_end":
{
"type":"pin",
"log_name":"CNT03/Couti_reg[1].ff_inst/CLK",
"phy_name":"CNT03.un1_Couti_cry_1_0/CLK"
},
"path_sections":[
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":8.888,
"delay":0.000
},
{
"type":"net_delay",
"net":
{
"log_name":"top_reveal_coretop_instance/core0/tm_u/secured_instance_1_105/secured_signal_0_141",
"phy_name":"clk150"
},
"arrive":11.100,
"delay":2.212
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":11.100,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- ------------------------ ---------------- -------- --------------------- ------
CONSTRAINT 0.000 8.888 1
OSCA001.OSCA_inst/HFCLKOUT OSC_CORE_OSC_CORE_R1C137 CLOCK LATENCY 0.000 8.888 323
top_reveal_coretop_instance/core0/tm_u/secured_instance_1_105/secured_signal_0_141
NET DELAY 2.212 11.100 323
{CNT03/Couti_reg[1].ff_inst/CLK CNT03/Couti_reg[2].ff_inst/CLK}
CLOCK PIN 0.000 11.100 1
Uncertainty -(0.000) 11.100
Common Path Skew 0.027 11.127
Setup time -(0.206) 10.921
---------------------------------------- ------------------------ ---------------- -------- --------------------- ------
Required Time 10.921
Arrival Time -(7.760)
---------------------------------------- ------------------------ ---------------- -------- --------------------- ------
Path Slack (Passed) 3.160
++++ Path 5 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Path Begin : rsti_0io.PIC_inst/Q (SIOLOGIC_CORE_IOL_R24A)
Path End : {CNT03/Couti_reg[3].ff_inst/LSR CNT03/Couti_reg[4].ff_inst/LSR} (SLICE_R61C9C)
Source Clock : clk150 (R)
Destination Clock: clk150 (R)
Logic Level : 1
Delay Ratio : 92.3% (route), 7.7% (logic)
Clock Skew : -0.215 ns
Setup Constraint : 8.888 ns
Common Path Skew : 0.027 ns
Path Slack : 3.160 ns (Passed)
Source Clock Path
{
"path_begin":
{
"type":"pin",
"log_name":"OSCA001.OSCA_inst/HFCLKOUT",
"phy_name":"OSCA001.OSCA_inst/HFCLKOUT"
},
"path_end":
{
"type":"pin",
"log_name":"rsti_0io.PIC_inst/CLK",
"phy_name":"reset_pad.bb_inst_IOL/SCLKIN"
},
"path_sections":[
{
"type":"net_delay",
"net":
{
"log_name":"top_reveal_coretop_instance/core0/tm_u/secured_instance_1_105/secured_signal_0_141",
"phy_name":"clk150"
},
"arrive":2.427,
"delay":2.427
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":2.427,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- ------------------------ ---------------- -------- --------------------- ------
OSCA001.OSCA_inst/HFCLKOUT OSC_CORE_OSC_CORE_R1C137 CLOCK LATENCY 0.000 0.000 323
top_reveal_coretop_instance/core0/tm_u/secured_instance_1_105/secured_signal_0_141
NET DELAY 2.427 2.427 323
rsti_0io.PIC_inst/CLK CLOCK PIN 0.000 2.427 1
Data Path
{
"path_begin":
{
"type":"pin",
"log_name":"rsti_0io.PIC_inst/Q",
"phy_name":"reset_pad.bb_inst_IOL/INFF"
},
"path_end":
{
"type":"pin",
"log_name":"{CNT03/Couti_reg[3].ff_inst/LSR CNT03/Couti_reg[4].ff_inst/LSR}",
"phy_name":"CNT03.un1_Couti_cry_3_0/LSR"
},
"path_sections":[
{
"type":"site_delay",
"pin0":
{
"log_name":"rsti_0io.PIC_inst/CLK",
"phy_name":"reset_pad.bb_inst_IOL/SCLKIN"
},
"pin1":
{
"log_name":"rsti_0io.PIC_inst/Q",
"phy_name":"reset_pad.bb_inst_IOL/INFF"
},
"arrive":2.837,
"delay":0.410
},
{
"type":"net_delay",
"net":
{
"log_name":"top_reveal_coretop_instance/core0/tm_u/secured_signal_1_89",
"phy_name":"rsti_1"
},
"arrive":7.761,
"delay":4.924
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":7.761,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- ------------------------ ---------------- -------- --------------------- ------
rsti_0io.PIC_inst/CLK->rsti_0io.PIC_inst/Q
SIOLOGIC_CORE_IOL_R24A C2INP_DEL 0.410 2.837 38
top_reveal_coretop_instance/core0/tm_u/secured_signal_1_89
NET DELAY 4.924 7.761 38
{CNT03/Couti_reg[3].ff_inst/LSR CNT03/Couti_reg[4].ff_inst/LSR}
ENDPOINT 0.000 7.761 1
Destination Clock Path
{
"path_begin":
{
"type":"pin",
"log_name":"OSCA001.OSCA_inst/HFCLKOUT",
"phy_name":"OSCA001.OSCA_inst/HFCLKOUT"
},
"path_end":
{
"type":"pin",
"log_name":"CNT03/Couti_reg[3].ff_inst/CLK",
"phy_name":"CNT03.un1_Couti_cry_3_0/CLK"
},
"path_sections":[
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":8.888,
"delay":0.000
},
{
"type":"net_delay",
"net":
{
"log_name":"top_reveal_coretop_instance/core0/tm_u/secured_instance_1_105/secured_signal_0_141",
"phy_name":"clk150"
},
"arrive":11.100,
"delay":2.212
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":11.100,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- ------------------------ ---------------- -------- --------------------- ------
CONSTRAINT 0.000 8.888 1
OSCA001.OSCA_inst/HFCLKOUT OSC_CORE_OSC_CORE_R1C137 CLOCK LATENCY 0.000 8.888 323
top_reveal_coretop_instance/core0/tm_u/secured_instance_1_105/secured_signal_0_141
NET DELAY 2.212 11.100 323
{CNT03/Couti_reg[3].ff_inst/CLK CNT03/Couti_reg[4].ff_inst/CLK}
CLOCK PIN 0.000 11.100 1
Uncertainty -(0.000) 11.100
Common Path Skew 0.027 11.127
Setup time -(0.206) 10.921
---------------------------------------- ------------------------ ---------------- -------- --------------------- ------
Required Time 10.921
Arrival Time -(7.760)
---------------------------------------- ------------------------ ---------------- -------- --------------------- ------
Path Slack (Passed) 3.160
++++ Path 6 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Path Begin : rsti_0io.PIC_inst/Q (SIOLOGIC_CORE_IOL_R24A)
Path End : {CNT03/Couti_reg[5].ff_inst/LSR CNT03/Couti_reg[6].ff_inst/LSR} (SLICE_R61C9D)
Source Clock : clk150 (R)
Destination Clock: clk150 (R)
Logic Level : 1
Delay Ratio : 92.3% (route), 7.7% (logic)
Clock Skew : -0.215 ns
Setup Constraint : 8.888 ns
Common Path Skew : 0.027 ns
Path Slack : 3.160 ns (Passed)
Source Clock Path
{
"path_begin":
{
"type":"pin",
"log_name":"OSCA001.OSCA_inst/HFCLKOUT",
"phy_name":"OSCA001.OSCA_inst/HFCLKOUT"
},
"path_end":
{
"type":"pin",
"log_name":"rsti_0io.PIC_inst/CLK",
"phy_name":"reset_pad.bb_inst_IOL/SCLKIN"
},
"path_sections":[
{
"type":"net_delay",
"net":
{
"log_name":"top_reveal_coretop_instance/core0/tm_u/secured_instance_1_105/secured_signal_0_141",
"phy_name":"clk150"
},
"arrive":2.427,
"delay":2.427
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":2.427,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- ------------------------ ---------------- -------- --------------------- ------
OSCA001.OSCA_inst/HFCLKOUT OSC_CORE_OSC_CORE_R1C137 CLOCK LATENCY 0.000 0.000 323
top_reveal_coretop_instance/core0/tm_u/secured_instance_1_105/secured_signal_0_141
NET DELAY 2.427 2.427 323
rsti_0io.PIC_inst/CLK CLOCK PIN 0.000 2.427 1
Data Path
{
"path_begin":
{
"type":"pin",
"log_name":"rsti_0io.PIC_inst/Q",
"phy_name":"reset_pad.bb_inst_IOL/INFF"
},
"path_end":
{
"type":"pin",
"log_name":"{CNT03/Couti_reg[5].ff_inst/LSR CNT03/Couti_reg[6].ff_inst/LSR}",
"phy_name":"CNT03.un1_Couti_cry_5_0/LSR"
},
"path_sections":[
{
"type":"site_delay",
"pin0":
{
"log_name":"rsti_0io.PIC_inst/CLK",
"phy_name":"reset_pad.bb_inst_IOL/SCLKIN"
},
"pin1":
{
"log_name":"rsti_0io.PIC_inst/Q",
"phy_name":"reset_pad.bb_inst_IOL/INFF"
},
"arrive":2.837,
"delay":0.410
},
{
"type":"net_delay",
"net":
{
"log_name":"top_reveal_coretop_instance/core0/tm_u/secured_signal_1_89",
"phy_name":"rsti_1"
},
"arrive":7.761,
"delay":4.924
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":7.761,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- ------------------------ ---------------- -------- --------------------- ------
rsti_0io.PIC_inst/CLK->rsti_0io.PIC_inst/Q
SIOLOGIC_CORE_IOL_R24A C2INP_DEL 0.410 2.837 38
top_reveal_coretop_instance/core0/tm_u/secured_signal_1_89
NET DELAY 4.924 7.761 38
{CNT03/Couti_reg[5].ff_inst/LSR CNT03/Couti_reg[6].ff_inst/LSR}
ENDPOINT 0.000 7.761 1
Destination Clock Path
{
"path_begin":
{
"type":"pin",
"log_name":"OSCA001.OSCA_inst/HFCLKOUT",
"phy_name":"OSCA001.OSCA_inst/HFCLKOUT"
},
"path_end":
{
"type":"pin",
"log_name":"CNT03/Couti_reg[5].ff_inst/CLK",
"phy_name":"CNT03.un1_Couti_cry_5_0/CLK"
},
"path_sections":[
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":8.888,
"delay":0.000
},
{
"type":"net_delay",
"net":
{
"log_name":"top_reveal_coretop_instance/core0/tm_u/secured_instance_1_105/secured_signal_0_141",
"phy_name":"clk150"
},
"arrive":11.100,
"delay":2.212
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":11.100,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- ------------------------ ---------------- -------- --------------------- ------
CONSTRAINT 0.000 8.888 1
OSCA001.OSCA_inst/HFCLKOUT OSC_CORE_OSC_CORE_R1C137 CLOCK LATENCY 0.000 8.888 323
top_reveal_coretop_instance/core0/tm_u/secured_instance_1_105/secured_signal_0_141
NET DELAY 2.212 11.100 323
{CNT03/Couti_reg[5].ff_inst/CLK CNT03/Couti_reg[6].ff_inst/CLK}
CLOCK PIN 0.000 11.100 1
Uncertainty -(0.000) 11.100
Common Path Skew 0.027 11.127
Setup time -(0.206) 10.921
---------------------------------------- ------------------------ ---------------- -------- --------------------- ------
Required Time 10.921
Arrival Time -(7.760)
---------------------------------------- ------------------------ ---------------- -------- --------------------- ------
Path Slack (Passed) 3.160
++++ Path 7 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Path Begin : rsti_0io.PIC_inst/Q (SIOLOGIC_CORE_IOL_R24A)
Path End : {CNT03/Couti_reg[7].ff_inst/LSR CNT03/Couti_reg[8].ff_inst/LSR} (SLICE_R61C10A)
Source Clock : clk150 (R)
Destination Clock: clk150 (R)
Logic Level : 1
Delay Ratio : 92.3% (route), 7.7% (logic)
Clock Skew : -0.215 ns
Setup Constraint : 8.888 ns
Common Path Skew : 0.027 ns
Path Slack : 3.205 ns (Passed)
Source Clock Path
{
"path_begin":
{
"type":"pin",
"log_name":"OSCA001.OSCA_inst/HFCLKOUT",
"phy_name":"OSCA001.OSCA_inst/HFCLKOUT"
},
"path_end":
{
"type":"pin",
"log_name":"rsti_0io.PIC_inst/CLK",
"phy_name":"reset_pad.bb_inst_IOL/SCLKIN"
},
"path_sections":[
{
"type":"net_delay",
"net":
{
"log_name":"top_reveal_coretop_instance/core0/tm_u/secured_instance_1_105/secured_signal_0_141",
"phy_name":"clk150"
},
"arrive":2.427,
"delay":2.427
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":2.427,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- ------------------------ ---------------- -------- --------------------- ------
OSCA001.OSCA_inst/HFCLKOUT OSC_CORE_OSC_CORE_R1C137 CLOCK LATENCY 0.000 0.000 323
top_reveal_coretop_instance/core0/tm_u/secured_instance_1_105/secured_signal_0_141
NET DELAY 2.427 2.427 323
rsti_0io.PIC_inst/CLK CLOCK PIN 0.000 2.427 1
Data Path
{
"path_begin":
{
"type":"pin",
"log_name":"rsti_0io.PIC_inst/Q",
"phy_name":"reset_pad.bb_inst_IOL/INFF"
},
"path_end":
{
"type":"pin",
"log_name":"{CNT03/Couti_reg[7].ff_inst/LSR CNT03/Couti_reg[8].ff_inst/LSR}",
"phy_name":"CNT03.un1_Couti_cry_7_0/LSR"
},
"path_sections":[
{
"type":"site_delay",
"pin0":
{
"log_name":"rsti_0io.PIC_inst/CLK",
"phy_name":"reset_pad.bb_inst_IOL/SCLKIN"
},
"pin1":
{
"log_name":"rsti_0io.PIC_inst/Q",
"phy_name":"reset_pad.bb_inst_IOL/INFF"
},
"arrive":2.837,
"delay":0.410
},
{
"type":"net_delay",
"net":
{
"log_name":"top_reveal_coretop_instance/core0/tm_u/secured_signal_1_89",
"phy_name":"rsti_1"
},
"arrive":7.724,
"delay":4.887
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":7.724,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- ------------------------ ---------------- -------- --------------------- ------
rsti_0io.PIC_inst/CLK->rsti_0io.PIC_inst/Q
SIOLOGIC_CORE_IOL_R24A C2INP_DEL 0.410 2.837 38
top_reveal_coretop_instance/core0/tm_u/secured_signal_1_89
NET DELAY 4.887 7.724 38
{CNT03/Couti_reg[7].ff_inst/LSR CNT03/Couti_reg[8].ff_inst/LSR}
ENDPOINT 0.000 7.724 1
Destination Clock Path
{
"path_begin":
{
"type":"pin",
"log_name":"OSCA001.OSCA_inst/HFCLKOUT",
"phy_name":"OSCA001.OSCA_inst/HFCLKOUT"
},
"path_end":
{
"type":"pin",
"log_name":"CNT03/Couti_reg[7].ff_inst/CLK",
"phy_name":"CNT03.un1_Couti_cry_7_0/CLK"
},
"path_sections":[
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":8.888,
"delay":0.000
},
{
"type":"net_delay",
"net":
{
"log_name":"top_reveal_coretop_instance/core0/tm_u/secured_instance_1_105/secured_signal_0_141",
"phy_name":"clk150"
},
"arrive":11.100,
"delay":2.212
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":11.100,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- ------------------------ ---------------- -------- --------------------- ------
CONSTRAINT 0.000 8.888 1
OSCA001.OSCA_inst/HFCLKOUT OSC_CORE_OSC_CORE_R1C137 CLOCK LATENCY 0.000 8.888 323
top_reveal_coretop_instance/core0/tm_u/secured_instance_1_105/secured_signal_0_141
NET DELAY 2.212 11.100 323
{CNT03/Couti_reg[7].ff_inst/CLK CNT03/Couti_reg[8].ff_inst/CLK}
CLOCK PIN 0.000 11.100 1
Uncertainty -(0.000) 11.100
Common Path Skew 0.027 11.127
Setup time -(0.198) 10.929
---------------------------------------- ------------------------ ---------------- -------- --------------------- ------
Required Time 10.929
Arrival Time -(7.723)
---------------------------------------- ------------------------ ---------------- -------- --------------------- ------
Path Slack (Passed) 3.205
++++ Path 8 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Path Begin : rsti_0io.PIC_inst/Q (SIOLOGIC_CORE_IOL_R24A)
Path End : {CNT03/Couti_reg[9].ff_inst/LSR CNT03/Couti_reg[10].ff_inst/LSR} (SLICE_R61C10B)
Source Clock : clk150 (R)
Destination Clock: clk150 (R)
Logic Level : 1
Delay Ratio : 92.3% (route), 7.7% (logic)
Clock Skew : -0.215 ns
Setup Constraint : 8.888 ns
Common Path Skew : 0.027 ns
Path Slack : 3.205 ns (Passed)
Source Clock Path
{
"path_begin":
{
"type":"pin",
"log_name":"OSCA001.OSCA_inst/HFCLKOUT",
"phy_name":"OSCA001.OSCA_inst/HFCLKOUT"
},
"path_end":
{
"type":"pin",
"log_name":"rsti_0io.PIC_inst/CLK",
"phy_name":"reset_pad.bb_inst_IOL/SCLKIN"
},
"path_sections":[
{
"type":"net_delay",
"net":
{
"log_name":"top_reveal_coretop_instance/core0/tm_u/secured_instance_1_105/secured_signal_0_141",
"phy_name":"clk150"
},
"arrive":2.427,
"delay":2.427
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":2.427,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- ------------------------ ---------------- -------- --------------------- ------
OSCA001.OSCA_inst/HFCLKOUT OSC_CORE_OSC_CORE_R1C137 CLOCK LATENCY 0.000 0.000 323
top_reveal_coretop_instance/core0/tm_u/secured_instance_1_105/secured_signal_0_141
NET DELAY 2.427 2.427 323
rsti_0io.PIC_inst/CLK CLOCK PIN 0.000 2.427 1
Data Path
{
"path_begin":
{
"type":"pin",
"log_name":"rsti_0io.PIC_inst/Q",
"phy_name":"reset_pad.bb_inst_IOL/INFF"
},
"path_end":
{
"type":"pin",
"log_name":"{CNT03/Couti_reg[9].ff_inst/LSR CNT03/Couti_reg[10].ff_inst/LSR}",
"phy_name":"CNT03.un1_Couti_cry_9_0/LSR"
},
"path_sections":[
{
"type":"site_delay",
"pin0":
{
"log_name":"rsti_0io.PIC_inst/CLK",
"phy_name":"reset_pad.bb_inst_IOL/SCLKIN"
},
"pin1":
{
"log_name":"rsti_0io.PIC_inst/Q",
"phy_name":"reset_pad.bb_inst_IOL/INFF"
},
"arrive":2.837,
"delay":0.410
},
{
"type":"net_delay",
"net":
{
"log_name":"top_reveal_coretop_instance/core0/tm_u/secured_signal_1_89",
"phy_name":"rsti_1"
},
"arrive":7.724,
"delay":4.887
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":7.724,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- ------------------------ ---------------- -------- --------------------- ------
rsti_0io.PIC_inst/CLK->rsti_0io.PIC_inst/Q
SIOLOGIC_CORE_IOL_R24A C2INP_DEL 0.410 2.837 38
top_reveal_coretop_instance/core0/tm_u/secured_signal_1_89
NET DELAY 4.887 7.724 38
{CNT03/Couti_reg[9].ff_inst/LSR CNT03/Couti_reg[10].ff_inst/LSR}
ENDPOINT 0.000 7.724 1
Destination Clock Path
{
"path_begin":
{
"type":"pin",
"log_name":"OSCA001.OSCA_inst/HFCLKOUT",
"phy_name":"OSCA001.OSCA_inst/HFCLKOUT"
},
"path_end":
{
"type":"pin",
"log_name":"CNT03/Couti_reg[9].ff_inst/CLK",
"phy_name":"CNT03.un1_Couti_cry_9_0/CLK"
},
"path_sections":[
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":8.888,
"delay":0.000
},
{
"type":"net_delay",
"net":
{
"log_name":"top_reveal_coretop_instance/core0/tm_u/secured_instance_1_105/secured_signal_0_141",
"phy_name":"clk150"
},
"arrive":11.100,
"delay":2.212
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":11.100,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- ------------------------ ---------------- -------- --------------------- ------
CONSTRAINT 0.000 8.888 1
OSCA001.OSCA_inst/HFCLKOUT OSC_CORE_OSC_CORE_R1C137 CLOCK LATENCY 0.000 8.888 323
top_reveal_coretop_instance/core0/tm_u/secured_instance_1_105/secured_signal_0_141
NET DELAY 2.212 11.100 323
{CNT03/Couti_reg[9].ff_inst/CLK CNT03/Couti_reg[10].ff_inst/CLK}
CLOCK PIN 0.000 11.100 1
Uncertainty -(0.000) 11.100
Common Path Skew 0.027 11.127
Setup time -(0.198) 10.929
---------------------------------------- ------------------------ ---------------- -------- --------------------- ------
Required Time 10.929
Arrival Time -(7.723)
---------------------------------------- ------------------------ ---------------- -------- --------------------- ------
Path Slack (Passed) 3.205
++++ Path 9 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Path Begin : rsti_0io.PIC_inst/Q (SIOLOGIC_CORE_IOL_R24A)
Path End : {CNT03/Couti_reg[11].ff_inst/LSR CNT03/Couti_reg[12].ff_inst/LSR} (SLICE_R61C10C)
Source Clock : clk150 (R)
Destination Clock: clk150 (R)
Logic Level : 1
Delay Ratio : 92.3% (route), 7.7% (logic)
Clock Skew : -0.215 ns
Setup Constraint : 8.888 ns
Common Path Skew : 0.027 ns
Path Slack : 3.205 ns (Passed)
Source Clock Path
{
"path_begin":
{
"type":"pin",
"log_name":"OSCA001.OSCA_inst/HFCLKOUT",
"phy_name":"OSCA001.OSCA_inst/HFCLKOUT"
},
"path_end":
{
"type":"pin",
"log_name":"rsti_0io.PIC_inst/CLK",
"phy_name":"reset_pad.bb_inst_IOL/SCLKIN"
},
"path_sections":[
{
"type":"net_delay",
"net":
{
"log_name":"top_reveal_coretop_instance/core0/tm_u/secured_instance_1_105/secured_signal_0_141",
"phy_name":"clk150"
},
"arrive":2.427,
"delay":2.427
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":2.427,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- ------------------------ ---------------- -------- --------------------- ------
OSCA001.OSCA_inst/HFCLKOUT OSC_CORE_OSC_CORE_R1C137 CLOCK LATENCY 0.000 0.000 323
top_reveal_coretop_instance/core0/tm_u/secured_instance_1_105/secured_signal_0_141
NET DELAY 2.427 2.427 323
rsti_0io.PIC_inst/CLK CLOCK PIN 0.000 2.427 1
Data Path
{
"path_begin":
{
"type":"pin",
"log_name":"rsti_0io.PIC_inst/Q",
"phy_name":"reset_pad.bb_inst_IOL/INFF"
},
"path_end":
{
"type":"pin",
"log_name":"{CNT03/Couti_reg[11].ff_inst/LSR CNT03/Couti_reg[12].ff_inst/LSR}",
"phy_name":"CNT03.un1_Couti_cry_11_0/LSR"
},
"path_sections":[
{
"type":"site_delay",
"pin0":
{
"log_name":"rsti_0io.PIC_inst/CLK",
"phy_name":"reset_pad.bb_inst_IOL/SCLKIN"
},
"pin1":
{
"log_name":"rsti_0io.PIC_inst/Q",
"phy_name":"reset_pad.bb_inst_IOL/INFF"
},
"arrive":2.837,
"delay":0.410
},
{
"type":"net_delay",
"net":
{
"log_name":"top_reveal_coretop_instance/core0/tm_u/secured_signal_1_89",
"phy_name":"rsti_1"
},
"arrive":7.724,
"delay":4.887
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":7.724,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- ------------------------ ---------------- -------- --------------------- ------
rsti_0io.PIC_inst/CLK->rsti_0io.PIC_inst/Q
SIOLOGIC_CORE_IOL_R24A C2INP_DEL 0.410 2.837 38
top_reveal_coretop_instance/core0/tm_u/secured_signal_1_89
NET DELAY 4.887 7.724 38
{CNT03/Couti_reg[11].ff_inst/LSR CNT03/Couti_reg[12].ff_inst/LSR}
ENDPOINT 0.000 7.724 1
Destination Clock Path
{
"path_begin":
{
"type":"pin",
"log_name":"OSCA001.OSCA_inst/HFCLKOUT",
"phy_name":"OSCA001.OSCA_inst/HFCLKOUT"
},
"path_end":
{
"type":"pin",
"log_name":"CNT03/Couti_reg[11].ff_inst/CLK",
"phy_name":"CNT03.un1_Couti_cry_11_0/CLK"
},
"path_sections":[
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":8.888,
"delay":0.000
},
{
"type":"net_delay",
"net":
{
"log_name":"top_reveal_coretop_instance/core0/tm_u/secured_instance_1_105/secured_signal_0_141",
"phy_name":"clk150"
},
"arrive":11.100,
"delay":2.212
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":11.100,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- ------------------------ ---------------- -------- --------------------- ------
CONSTRAINT 0.000 8.888 1
OSCA001.OSCA_inst/HFCLKOUT OSC_CORE_OSC_CORE_R1C137 CLOCK LATENCY 0.000 8.888 323
top_reveal_coretop_instance/core0/tm_u/secured_instance_1_105/secured_signal_0_141
NET DELAY 2.212 11.100 323
{CNT03/Couti_reg[11].ff_inst/CLK CNT03/Couti_reg[12].ff_inst/CLK}
CLOCK PIN 0.000 11.100 1
Uncertainty -(0.000) 11.100
Common Path Skew 0.027 11.127
Setup time -(0.198) 10.929
---------------------------------------- ------------------------ ---------------- -------- --------------------- ------
Required Time 10.929
Arrival Time -(7.723)
---------------------------------------- ------------------------ ---------------- -------- --------------------- ------
Path Slack (Passed) 3.205
++++ Path 10 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Path Begin : rsti_0io.PIC_inst/Q (SIOLOGIC_CORE_IOL_R24A)
Path End : {CNT03/Couti_reg[13].ff_inst/LSR CNT03/Couti_reg[14].ff_inst/LSR} (SLICE_R61C10D)
Source Clock : clk150 (R)
Destination Clock: clk150 (R)
Logic Level : 1
Delay Ratio : 92.3% (route), 7.7% (logic)
Clock Skew : -0.215 ns
Setup Constraint : 8.888 ns
Common Path Skew : 0.027 ns
Path Slack : 3.205 ns (Passed)
Source Clock Path
{
"path_begin":
{
"type":"pin",
"log_name":"OSCA001.OSCA_inst/HFCLKOUT",
"phy_name":"OSCA001.OSCA_inst/HFCLKOUT"
},
"path_end":
{
"type":"pin",
"log_name":"rsti_0io.PIC_inst/CLK",
"phy_name":"reset_pad.bb_inst_IOL/SCLKIN"
},
"path_sections":[
{
"type":"net_delay",
"net":
{
"log_name":"top_reveal_coretop_instance/core0/tm_u/secured_instance_1_105/secured_signal_0_141",
"phy_name":"clk150"
},
"arrive":2.427,
"delay":2.427
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":2.427,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- ------------------------ ---------------- -------- --------------------- ------
OSCA001.OSCA_inst/HFCLKOUT OSC_CORE_OSC_CORE_R1C137 CLOCK LATENCY 0.000 0.000 323
top_reveal_coretop_instance/core0/tm_u/secured_instance_1_105/secured_signal_0_141
NET DELAY 2.427 2.427 323
rsti_0io.PIC_inst/CLK CLOCK PIN 0.000 2.427 1
Data Path
{
"path_begin":
{
"type":"pin",
"log_name":"rsti_0io.PIC_inst/Q",
"phy_name":"reset_pad.bb_inst_IOL/INFF"
},
"path_end":
{
"type":"pin",
"log_name":"{CNT03/Couti_reg[13].ff_inst/LSR CNT03/Couti_reg[14].ff_inst/LSR}",
"phy_name":"CNT03.un1_Couti_cry_13_0/LSR"
},
"path_sections":[
{
"type":"site_delay",
"pin0":
{
"log_name":"rsti_0io.PIC_inst/CLK",
"phy_name":"reset_pad.bb_inst_IOL/SCLKIN"
},
"pin1":
{
"log_name":"rsti_0io.PIC_inst/Q",
"phy_name":"reset_pad.bb_inst_IOL/INFF"
},
"arrive":2.837,
"delay":0.410
},
{
"type":"net_delay",
"net":
{
"log_name":"top_reveal_coretop_instance/core0/tm_u/secured_signal_1_89",
"phy_name":"rsti_1"
},
"arrive":7.724,
"delay":4.887
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":7.724,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- ------------------------ ---------------- -------- --------------------- ------
rsti_0io.PIC_inst/CLK->rsti_0io.PIC_inst/Q
SIOLOGIC_CORE_IOL_R24A C2INP_DEL 0.410 2.837 38
top_reveal_coretop_instance/core0/tm_u/secured_signal_1_89
NET DELAY 4.887 7.724 38
{CNT03/Couti_reg[13].ff_inst/LSR CNT03/Couti_reg[14].ff_inst/LSR}
ENDPOINT 0.000 7.724 1
Destination Clock Path
{
"path_begin":
{
"type":"pin",
"log_name":"OSCA001.OSCA_inst/HFCLKOUT",
"phy_name":"OSCA001.OSCA_inst/HFCLKOUT"
},
"path_end":
{
"type":"pin",
"log_name":"CNT03/Couti_reg[13].ff_inst/CLK",
"phy_name":"CNT03.un1_Couti_cry_13_0/CLK"
},
"path_sections":[
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":8.888,
"delay":0.000
},
{
"type":"net_delay",
"net":
{
"log_name":"top_reveal_coretop_instance/core0/tm_u/secured_instance_1_105/secured_signal_0_141",
"phy_name":"clk150"
},
"arrive":11.100,
"delay":2.212
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":11.100,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- ------------------------ ---------------- -------- --------------------- ------
CONSTRAINT 0.000 8.888 1
OSCA001.OSCA_inst/HFCLKOUT OSC_CORE_OSC_CORE_R1C137 CLOCK LATENCY 0.000 8.888 323
top_reveal_coretop_instance/core0/tm_u/secured_instance_1_105/secured_signal_0_141
NET DELAY 2.212 11.100 323
{CNT03/Couti_reg[13].ff_inst/CLK CNT03/Couti_reg[14].ff_inst/CLK}
CLOCK PIN 0.000 11.100 1
Uncertainty -(0.000) 11.100
Common Path Skew 0.027 11.127
Setup time -(0.198) 10.929
---------------------------------------- ------------------------ ---------------- -------- --------------------- ------
Required Time 10.929
Arrival Time -(7.723)
---------------------------------------- ------------------------ ---------------- -------- --------------------- ------
Path Slack (Passed) 3.205
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
End of Detailed Report for timing paths
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
##########################################################
3 Setup at Speed Grade 9_High-Performance_1.0V Corner at -40 Degrees
3.1 Clock Summary
3.1.1 Clock "clk150"
create_clock -name {clk150} -period 8.88889 [get_pins {OSCA001.OSCA_inst/HFCLKOUT }]
Single Clock Domain
-------------------------------------------------------------------------------------------------------
Clock clk150 | | Period | Frequency
-------------------------------------------------------------------------------------------------------
From clk150 | Target | 8.889 ns | 112.500 MHz
| Actual (all paths) | 5.854 ns | 170.823 MHz
OSCA001.OSCA_inst/HFCLKOUT (MPW) | (50% duty cycle) | 4.358 ns | 229.463 MHz
-------------------------------------------------------------------------------------------------------
Clock Domain Crossing
------------------------------------------------------------------------------------------------------
Clock clk150 | Worst Time Between Edges | Comment
------------------------------------------------------------------------------------------------------
From rvltck | ---- | False path
From rvjtck | ---- | False path
------------------------------------------------------------------------------------------------------
3.1.2 Clock "rvltck"
create_clock -name {rvltck} -period 33.33 [get_ports TCK]
Single Clock Domain
-------------------------------------------------------------------------------------------------------
Clock rvltck | | Period | Frequency
-------------------------------------------------------------------------------------------------------
From rvltck | Target | 33.330 ns | 30.003 MHz
| Actual (all paths) | 5.000 ns | 200.000 MHz
jtaghub_inst/IB_inst2.bb_inst/B (MPW) | (50% duty cycle) | 5.000 ns | 200.000 MHz
-------------------------------------------------------------------------------------------------------
Clock Domain Crossing
------------------------------------------------------------------------------------------------------
Clock rvltck | Worst Time Between Edges | Comment
------------------------------------------------------------------------------------------------------
From clk150 | ---- | False path
From rvjtck | ---- | False path
------------------------------------------------------------------------------------------------------
3.1.3 Clock "rvjtck"
create_generated_clock -name {rvjtck} -source [get_ports TCK] [get_nets jtck]
Single Clock Domain
-------------------------------------------------------------------------------------------------------
Clock rvjtck | | Period | Frequency
-------------------------------------------------------------------------------------------------------
From rvjtck | Target | 33.330 ns | 30.003 MHz
| Actual (all paths) | 2.920 ns | 342.466 MHz
top_reveal_coretop_instance/core0/tm_u/secured_instance_1_105/secured_instance_0_65/CLKR (MPW)
| (50% duty cycle) | 2.920 ns | 342.466 MHz
-------------------------------------------------------------------------------------------------------
Clock Domain Crossing
------------------------------------------------------------------------------------------------------
Clock rvjtck | Worst Time Between Edges | Comment
------------------------------------------------------------------------------------------------------
From clk150 | ---- | False path
From rvltck | ---- | False path
------------------------------------------------------------------------------------------------------
3.2 Endpoint slacks
-------------------------------------------------------
Listing 10 End Points | Slack
-------------------------------------------------------
LED3_0io.PIC_inst/D | 3.035 ns
LED1_0io.PIC_inst/D | 3.094 ns
CNT03/Couti_reg[0].ff_inst/LSR | 3.256 ns
{CNT03/Couti_reg[1].ff_inst/LSR CNT03/Couti_reg[2].ff_inst/LSR}
| 3.256 ns
{CNT03/Couti_reg[3].ff_inst/LSR CNT03/Couti_reg[4].ff_inst/LSR}
| 3.256 ns
{CNT03/Couti_reg[5].ff_inst/LSR CNT03/Couti_reg[6].ff_inst/LSR}
| 3.256 ns
{CNT03/Couti_reg[7].ff_inst/LSR CNT03/Couti_reg[8].ff_inst/LSR}
| 3.293 ns
{CNT03/Couti_reg[9].ff_inst/LSR CNT03/Couti_reg[10].ff_inst/LSR}
| 3.293 ns
{CNT03/Couti_reg[11].ff_inst/LSR CNT03/Couti_reg[12].ff_inst/LSR}
| 3.293 ns
{CNT03/Couti_reg[13].ff_inst/LSR CNT03/Couti_reg[14].ff_inst/LSR}
| 3.293 ns
-------------------------------------------------------
|
Setup # of endpoints with negative slack:| 0
|
-------------------------------------------------------
3.3 Detailed Report
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
Detail report of critical paths
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Detailed Report for timing paths
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++++Path 1 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Path Begin : CNT03/Couti_reg[15].ff_inst/Q (SLICE_R61C11A)
Path End : LED3_0io.PIC_inst/D (SIOLOGIC_CORE_IOL_R31A)
Source Clock : clk150 (R)
Destination Clock: clk150 (R)
Logic Level : 2
Delay Ratio : 90.6% (route), 9.4% (logic)
Clock Skew : -0.101 ns
Setup Constraint : 8.888 ns
Common Path Skew : 0.031 ns
Path Slack : 3.034 ns (Passed)
Source Clock Path
{
"path_begin":
{
"type":"pin",
"log_name":"OSCA001.OSCA_inst/HFCLKOUT",
"phy_name":"OSCA001.OSCA_inst/HFCLKOUT"
},
"path_end":
{
"type":"pin",
"log_name":"CNT03/Couti_reg[15].ff_inst/CLK",
"phy_name":"CNT03.un1_Couti_s_15_0/CLK"
},
"path_sections":[
{
"type":"net_delay",
"net":
{
"log_name":"top_reveal_coretop_instance/core0/tm_u/secured_instance_1_105/secured_signal_0_141",
"phy_name":"clk150"
},
"arrive":2.654,
"delay":2.654
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":2.654,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- ------------------------ ---------------- -------- --------------------- ------
OSCA001.OSCA_inst/HFCLKOUT OSC_CORE_OSC_CORE_R1C137 CLOCK LATENCY 0.000 0.000 324
top_reveal_coretop_instance/core0/tm_u/secured_instance_1_105/secured_signal_0_141
NET DELAY 2.654 2.654 324
CNT03/Couti_reg[15].ff_inst/CLK CLOCK PIN 0.000 2.654 1
Data Path
{
"path_begin":
{
"type":"pin",
"log_name":"CNT03/Couti_reg[15].ff_inst/Q",
"phy_name":"CNT03.un1_Couti_s_15_0/Q0"
},
"path_end":
{
"type":"pin",
"log_name":"LED3_0io.PIC_inst/D",
"phy_name":"LED3_pad.bb_inst_IOL/TXDATA0"
},
"path_sections":[
{
"type":"site_delay",
"pin0":
{
"log_name":"CNT03/Couti_reg[15].ff_inst/CLK",
"phy_name":"CNT03.un1_Couti_s_15_0/CLK"
},
"pin1":
{
"log_name":"CNT03/Couti_reg[15].ff_inst/Q",
"phy_name":"CNT03.un1_Couti_s_15_0/Q0"
},
"arrive":2.955,
"delay":0.301
},
{
"type":"net_delay",
"net":
{
"log_name":"top_reveal_coretop_instance/core0/tm_u/secured_signal_1_57",
"phy_name":"CNT3[15]"
},
"arrive":6.200,
"delay":3.245
},
{
"type":"site_delay",
"pin0":
{
"log_name":"LED3_1_cZ/B",
"phy_name":"LED2_1_cZ/D1"
},
"pin1":
{
"log_name":"LED3_1_cZ/Z",
"phy_name":"LED2_1_cZ/F1"
},
"arrive":6.411,
"delay":0.211
},
{
"type":"net_delay",
"net":
{
"log_name":"LED3_1",
"phy_name":"LED3_1"
},
"arrive":8.101,
"delay":1.690
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":8.101,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- ------------------------ ---------------- -------- --------------------- ------
CNT03/Couti_reg[15].ff_inst/CLK->CNT03/Couti_reg[15].ff_inst/Q
SLICE_R61C11A REG_DEL 0.301 2.955 4
top_reveal_coretop_instance/core0/tm_u/secured_signal_1_57
NET DELAY 3.245 6.200 4
LED3_1_cZ/B->LED3_1_cZ/Z SLICE_R38C112D CTOF_DEL 0.211 6.411 1
LED3_1 NET DELAY 1.690 8.101 1
LED3_0io.PIC_inst/D ENDPOINT 0.000 8.101 1
Destination Clock Path
{
"path_begin":
{
"type":"pin",
"log_name":"OSCA001.OSCA_inst/HFCLKOUT",
"phy_name":"OSCA001.OSCA_inst/HFCLKOUT"
},
"path_end":
{
"type":"pin",
"log_name":"LED3_0io.PIC_inst/CLK",
"phy_name":"LED3_pad.bb_inst_IOL/SCLKOUT"
},
"path_sections":[
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":8.888,
"delay":0.000
},
{
"type":"net_delay",
"net":
{
"log_name":"top_reveal_coretop_instance/core0/tm_u/secured_instance_1_105/secured_signal_0_141",
"phy_name":"clk150"
},
"arrive":11.441,
"delay":2.553
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":11.441,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- ------------------------ ---------------- -------- --------------------- ------
CONSTRAINT 0.000 8.888 1
OSCA001.OSCA_inst/HFCLKOUT OSC_CORE_OSC_CORE_R1C137 CLOCK LATENCY 0.000 8.888 324
top_reveal_coretop_instance/core0/tm_u/secured_instance_1_105/secured_signal_0_141
NET DELAY 2.553 11.441 324
LED3_0io.PIC_inst/CLK CLOCK PIN 0.000 11.441 1
Uncertainty -(0.000) 11.441
Common Path Skew 0.031 11.472
Setup time -(0.337) 11.135
---------------------------------------- ------------------------ ---------------- -------- --------------------- ------
Required Time 11.135
Arrival Time -(8.100)
---------------------------------------- ------------------------ ---------------- -------- --------------------- ------
Path Slack (Passed) 3.034
++++ Path 2 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Path Begin : CNT01/Couti_reg[0].ff_inst/Q (SLICE_R14C12A)
Path End : LED1_0io.PIC_inst/D (SIOLOGIC_CORE_IOL_R28B)
Source Clock : clk150 (R)
Destination Clock: clk150 (R)
Logic Level : 2
Delay Ratio : 90.5% (route), 9.5% (logic)
Clock Skew : -0.101 ns
Setup Constraint : 8.888 ns
Common Path Skew : 0.031 ns
Path Slack : 3.093 ns (Passed)
Source Clock Path
{
"path_begin":
{
"type":"pin",
"log_name":"OSCA001.OSCA_inst/HFCLKOUT",
"phy_name":"OSCA001.OSCA_inst/HFCLKOUT"
},
"path_end":
{
"type":"pin",
"log_name":"CNT01/Couti_reg[0].ff_inst/CLK",
"phy_name":"CNT01.un1_Couti_cry_0_0/CLK"
},
"path_sections":[
{
"type":"net_delay",
"net":
{
"log_name":"top_reveal_coretop_instance/core0/tm_u/secured_instance_1_105/secured_signal_0_141",
"phy_name":"clk150"
},
"arrive":2.654,
"delay":2.654
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":2.654,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- ------------------------ ---------------- -------- --------------------- ------
OSCA001.OSCA_inst/HFCLKOUT OSC_CORE_OSC_CORE_R1C137 CLOCK LATENCY 0.000 0.000 324
top_reveal_coretop_instance/core0/tm_u/secured_instance_1_105/secured_signal_0_141
NET DELAY 2.654 2.654 324
CNT01/Couti_reg[0].ff_inst/CLK CLOCK PIN 0.000 2.654 1
Data Path
{
"path_begin":
{
"type":"pin",
"log_name":"CNT01/Couti_reg[0].ff_inst/Q",
"phy_name":"CNT01.un1_Couti_cry_0_0/Q1"
},
"path_end":
{
"type":"pin",
"log_name":"LED1_0io.PIC_inst/D",
"phy_name":"LED1_pad.bb_inst_IOL/TXDATA0"
},
"path_sections":[
{
"type":"site_delay",
"pin0":
{
"log_name":"CNT01/Couti_reg[0].ff_inst/CLK",
"phy_name":"CNT01.un1_Couti_cry_0_0/CLK"
},
"pin1":
{
"log_name":"CNT01/Couti_reg[0].ff_inst/Q",
"phy_name":"CNT01.un1_Couti_cry_0_0/Q1"
},
"arrive":2.956,
"delay":0.302
},
{
"type":"net_delay",
"net":
{
"log_name":"top_reveal_coretop_instance/core0/tm_u/secured_signal_1_40",
"phy_name":"CNT1[0]"
},
"arrive":6.210,
"delay":3.254
},
{
"type":"site_delay",
"pin0":
{
"log_name":"LED1_1_cZ/A",
"phy_name":"GND_cZ/C1"
},
"pin1":
{
"log_name":"LED1_1_cZ/Z",
"phy_name":"GND_cZ/F1"
},
"arrive":6.421,
"delay":0.211
},
{
"type":"net_delay",
"net":
{
"log_name":"LED1_1",
"phy_name":"LED1_1"
},
"arrive":8.042,
"delay":1.621
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":8.042,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- ------------------------ ---------------- -------- --------------------- ------
CNT01/Couti_reg[0].ff_inst/CLK->CNT01/Couti_reg[0].ff_inst/Q
SLICE_R14C12A REG_DEL 0.302 2.956 4
top_reveal_coretop_instance/core0/tm_u/secured_signal_1_40
NET DELAY 3.254 6.210 4
LED1_1_cZ/A->LED1_1_cZ/Z SLICE_R38C117D CTOF_DEL 0.211 6.421 1
LED1_1 NET DELAY 1.621 8.042 1
LED1_0io.PIC_inst/D ENDPOINT 0.000 8.042 1
Destination Clock Path
{
"path_begin":
{
"type":"pin",
"log_name":"OSCA001.OSCA_inst/HFCLKOUT",
"phy_name":"OSCA001.OSCA_inst/HFCLKOUT"
},
"path_end":
{
"type":"pin",
"log_name":"LED1_0io.PIC_inst/CLK",
"phy_name":"LED1_pad.bb_inst_IOL/SCLKOUT"
},
"path_sections":[
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":8.888,
"delay":0.000
},
{
"type":"net_delay",
"net":
{
"log_name":"top_reveal_coretop_instance/core0/tm_u/secured_instance_1_105/secured_signal_0_141",
"phy_name":"clk150"
},
"arrive":11.441,
"delay":2.553
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":11.441,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- ------------------------ ---------------- -------- --------------------- ------
CONSTRAINT 0.000 8.888 1
OSCA001.OSCA_inst/HFCLKOUT OSC_CORE_OSC_CORE_R1C137 CLOCK LATENCY 0.000 8.888 324
top_reveal_coretop_instance/core0/tm_u/secured_instance_1_105/secured_signal_0_141
NET DELAY 2.553 11.441 324
LED1_0io.PIC_inst/CLK CLOCK PIN 0.000 11.441 1
Uncertainty -(0.000) 11.441
Common Path Skew 0.031 11.472
Setup time -(0.337) 11.135
---------------------------------------- ------------------------ ---------------- -------- --------------------- ------
Required Time 11.135
Arrival Time -(8.041)
---------------------------------------- ------------------------ ---------------- -------- --------------------- ------
Path Slack (Passed) 3.093
++++ Path 3 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Path Begin : rsti_0io.PIC_inst/Q (SIOLOGIC_CORE_IOL_R24A)
Path End : CNT03/Couti_reg[0].ff_inst/LSR (SLICE_R61C9A)
Source Clock : clk150 (R)
Destination Clock: clk150 (R)
Logic Level : 1
Delay Ratio : 90.9% (route), 9.1% (logic)
Clock Skew : -0.234 ns
Setup Constraint : 8.888 ns
Common Path Skew : 0.031 ns
Path Slack : 3.255 ns (Passed)
Source Clock Path
{
"path_begin":
{
"type":"pin",
"log_name":"OSCA001.OSCA_inst/HFCLKOUT",
"phy_name":"OSCA001.OSCA_inst/HFCLKOUT"
},
"path_end":
{
"type":"pin",
"log_name":"rsti_0io.PIC_inst/CLK",
"phy_name":"reset_pad.bb_inst_IOL/SCLKIN"
},
"path_sections":[
{
"type":"net_delay",
"net":
{
"log_name":"top_reveal_coretop_instance/core0/tm_u/secured_instance_1_105/secured_signal_0_141",
"phy_name":"clk150"
},
"arrive":2.740,
"delay":2.740
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":2.740,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- ------------------------ ---------------- -------- --------------------- ------
OSCA001.OSCA_inst/HFCLKOUT OSC_CORE_OSC_CORE_R1C137 CLOCK LATENCY 0.000 0.000 324
top_reveal_coretop_instance/core0/tm_u/secured_instance_1_105/secured_signal_0_141
NET DELAY 2.740 2.740 324
rsti_0io.PIC_inst/CLK CLOCK PIN 0.000 2.740 1
Data Path
{
"path_begin":
{
"type":"pin",
"log_name":"rsti_0io.PIC_inst/Q",
"phy_name":"reset_pad.bb_inst_IOL/INFF"
},
"path_end":
{
"type":"pin",
"log_name":"CNT03/Couti_reg[0].ff_inst/LSR",
"phy_name":"CNT03.un1_Couti_cry_0_0/LSR"
},
"path_sections":[
{
"type":"site_delay",
"pin0":
{
"log_name":"rsti_0io.PIC_inst/CLK",
"phy_name":"reset_pad.bb_inst_IOL/SCLKIN"
},
"pin1":
{
"log_name":"rsti_0io.PIC_inst/Q",
"phy_name":"reset_pad.bb_inst_IOL/INFF"
},
"arrive":3.217,
"delay":0.477
},
{
"type":"net_delay",
"net":
{
"log_name":"top_reveal_coretop_instance/core0/tm_u/secured_signal_1_89",
"phy_name":"rsti_1"
},
"arrive":7.967,
"delay":4.750
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":7.967,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- ------------------------ ---------------- -------- --------------------- ------
rsti_0io.PIC_inst/CLK->rsti_0io.PIC_inst/Q
SIOLOGIC_CORE_IOL_R24A C2INP_DEL 0.477 3.217 38
top_reveal_coretop_instance/core0/tm_u/secured_signal_1_89
NET DELAY 4.750 7.967 38
CNT03/Couti_reg[0].ff_inst/LSR ENDPOINT 0.000 7.967 1
Destination Clock Path
{
"path_begin":
{
"type":"pin",
"log_name":"OSCA001.OSCA_inst/HFCLKOUT",
"phy_name":"OSCA001.OSCA_inst/HFCLKOUT"
},
"path_end":
{
"type":"pin",
"log_name":"CNT03/Couti_reg[0].ff_inst/CLK",
"phy_name":"CNT03.un1_Couti_cry_0_0/CLK"
},
"path_sections":[
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":8.888,
"delay":0.000
},
{
"type":"net_delay",
"net":
{
"log_name":"top_reveal_coretop_instance/core0/tm_u/secured_instance_1_105/secured_signal_0_141",
"phy_name":"clk150"
},
"arrive":11.394,
"delay":2.506
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":11.394,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- ------------------------ ---------------- -------- --------------------- ------
CONSTRAINT 0.000 8.888 1
OSCA001.OSCA_inst/HFCLKOUT OSC_CORE_OSC_CORE_R1C137 CLOCK LATENCY 0.000 8.888 324
top_reveal_coretop_instance/core0/tm_u/secured_instance_1_105/secured_signal_0_141
NET DELAY 2.506 11.394 324
CNT03/Couti_reg[0].ff_inst/CLK CLOCK PIN 0.000 11.394 1
Uncertainty -(0.000) 11.394
Common Path Skew 0.031 11.425
Setup time -(0.203) 11.222
---------------------------------------- ------------------------ ---------------- -------- --------------------- ------
Required Time 11.222
Arrival Time -(7.966)
---------------------------------------- ------------------------ ---------------- -------- --------------------- ------
Path Slack (Passed) 3.255
++++ Path 4 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Path Begin : rsti_0io.PIC_inst/Q (SIOLOGIC_CORE_IOL_R24A)
Path End : {CNT03/Couti_reg[1].ff_inst/LSR CNT03/Couti_reg[2].ff_inst/LSR} (SLICE_R61C9B)
Source Clock : clk150 (R)
Destination Clock: clk150 (R)
Logic Level : 1
Delay Ratio : 90.9% (route), 9.1% (logic)
Clock Skew : -0.234 ns
Setup Constraint : 8.888 ns
Common Path Skew : 0.031 ns
Path Slack : 3.255 ns (Passed)
Source Clock Path
{
"path_begin":
{
"type":"pin",
"log_name":"OSCA001.OSCA_inst/HFCLKOUT",
"phy_name":"OSCA001.OSCA_inst/HFCLKOUT"
},
"path_end":
{
"type":"pin",
"log_name":"rsti_0io.PIC_inst/CLK",
"phy_name":"reset_pad.bb_inst_IOL/SCLKIN"
},
"path_sections":[
{
"type":"net_delay",
"net":
{
"log_name":"top_reveal_coretop_instance/core0/tm_u/secured_instance_1_105/secured_signal_0_141",
"phy_name":"clk150"
},
"arrive":2.740,
"delay":2.740
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":2.740,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- ------------------------ ---------------- -------- --------------------- ------
OSCA001.OSCA_inst/HFCLKOUT OSC_CORE_OSC_CORE_R1C137 CLOCK LATENCY 0.000 0.000 324
top_reveal_coretop_instance/core0/tm_u/secured_instance_1_105/secured_signal_0_141
NET DELAY 2.740 2.740 324
rsti_0io.PIC_inst/CLK CLOCK PIN 0.000 2.740 1
Data Path
{
"path_begin":
{
"type":"pin",
"log_name":"rsti_0io.PIC_inst/Q",
"phy_name":"reset_pad.bb_inst_IOL/INFF"
},
"path_end":
{
"type":"pin",
"log_name":"{CNT03/Couti_reg[1].ff_inst/LSR CNT03/Couti_reg[2].ff_inst/LSR}",
"phy_name":"CNT03.un1_Couti_cry_1_0/LSR"
},
"path_sections":[
{
"type":"site_delay",
"pin0":
{
"log_name":"rsti_0io.PIC_inst/CLK",
"phy_name":"reset_pad.bb_inst_IOL/SCLKIN"
},
"pin1":
{
"log_name":"rsti_0io.PIC_inst/Q",
"phy_name":"reset_pad.bb_inst_IOL/INFF"
},
"arrive":3.217,
"delay":0.477
},
{
"type":"net_delay",
"net":
{
"log_name":"top_reveal_coretop_instance/core0/tm_u/secured_signal_1_89",
"phy_name":"rsti_1"
},
"arrive":7.967,
"delay":4.750
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":7.967,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- ------------------------ ---------------- -------- --------------------- ------
rsti_0io.PIC_inst/CLK->rsti_0io.PIC_inst/Q
SIOLOGIC_CORE_IOL_R24A C2INP_DEL 0.477 3.217 38
top_reveal_coretop_instance/core0/tm_u/secured_signal_1_89
NET DELAY 4.750 7.967 38
{CNT03/Couti_reg[1].ff_inst/LSR CNT03/Couti_reg[2].ff_inst/LSR}
ENDPOINT 0.000 7.967 1
Destination Clock Path
{
"path_begin":
{
"type":"pin",
"log_name":"OSCA001.OSCA_inst/HFCLKOUT",
"phy_name":"OSCA001.OSCA_inst/HFCLKOUT"
},
"path_end":
{
"type":"pin",
"log_name":"CNT03/Couti_reg[1].ff_inst/CLK",
"phy_name":"CNT03.un1_Couti_cry_1_0/CLK"
},
"path_sections":[
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":8.888,
"delay":0.000
},
{
"type":"net_delay",
"net":
{
"log_name":"top_reveal_coretop_instance/core0/tm_u/secured_instance_1_105/secured_signal_0_141",
"phy_name":"clk150"
},
"arrive":11.394,
"delay":2.506
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":11.394,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- ------------------------ ---------------- -------- --------------------- ------
CONSTRAINT 0.000 8.888 1
OSCA001.OSCA_inst/HFCLKOUT OSC_CORE_OSC_CORE_R1C137 CLOCK LATENCY 0.000 8.888 324
top_reveal_coretop_instance/core0/tm_u/secured_instance_1_105/secured_signal_0_141
NET DELAY 2.506 11.394 324
{CNT03/Couti_reg[1].ff_inst/CLK CNT03/Couti_reg[2].ff_inst/CLK}
CLOCK PIN 0.000 11.394 1
Uncertainty -(0.000) 11.394
Common Path Skew 0.031 11.425
Setup time -(0.203) 11.222
---------------------------------------- ------------------------ ---------------- -------- --------------------- ------
Required Time 11.222
Arrival Time -(7.966)
---------------------------------------- ------------------------ ---------------- -------- --------------------- ------
Path Slack (Passed) 3.255
++++ Path 5 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Path Begin : rsti_0io.PIC_inst/Q (SIOLOGIC_CORE_IOL_R24A)
Path End : {CNT03/Couti_reg[3].ff_inst/LSR CNT03/Couti_reg[4].ff_inst/LSR} (SLICE_R61C9C)
Source Clock : clk150 (R)
Destination Clock: clk150 (R)
Logic Level : 1
Delay Ratio : 90.9% (route), 9.1% (logic)
Clock Skew : -0.234 ns
Setup Constraint : 8.888 ns
Common Path Skew : 0.031 ns
Path Slack : 3.255 ns (Passed)
Source Clock Path
{
"path_begin":
{
"type":"pin",
"log_name":"OSCA001.OSCA_inst/HFCLKOUT",
"phy_name":"OSCA001.OSCA_inst/HFCLKOUT"
},
"path_end":
{
"type":"pin",
"log_name":"rsti_0io.PIC_inst/CLK",
"phy_name":"reset_pad.bb_inst_IOL/SCLKIN"
},
"path_sections":[
{
"type":"net_delay",
"net":
{
"log_name":"top_reveal_coretop_instance/core0/tm_u/secured_instance_1_105/secured_signal_0_141",
"phy_name":"clk150"
},
"arrive":2.740,
"delay":2.740
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":2.740,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- ------------------------ ---------------- -------- --------------------- ------
OSCA001.OSCA_inst/HFCLKOUT OSC_CORE_OSC_CORE_R1C137 CLOCK LATENCY 0.000 0.000 324
top_reveal_coretop_instance/core0/tm_u/secured_instance_1_105/secured_signal_0_141
NET DELAY 2.740 2.740 324
rsti_0io.PIC_inst/CLK CLOCK PIN 0.000 2.740 1
Data Path
{
"path_begin":
{
"type":"pin",
"log_name":"rsti_0io.PIC_inst/Q",
"phy_name":"reset_pad.bb_inst_IOL/INFF"
},
"path_end":
{
"type":"pin",
"log_name":"{CNT03/Couti_reg[3].ff_inst/LSR CNT03/Couti_reg[4].ff_inst/LSR}",
"phy_name":"CNT03.un1_Couti_cry_3_0/LSR"
},
"path_sections":[
{
"type":"site_delay",
"pin0":
{
"log_name":"rsti_0io.PIC_inst/CLK",
"phy_name":"reset_pad.bb_inst_IOL/SCLKIN"
},
"pin1":
{
"log_name":"rsti_0io.PIC_inst/Q",
"phy_name":"reset_pad.bb_inst_IOL/INFF"
},
"arrive":3.217,
"delay":0.477
},
{
"type":"net_delay",
"net":
{
"log_name":"top_reveal_coretop_instance/core0/tm_u/secured_signal_1_89",
"phy_name":"rsti_1"
},
"arrive":7.967,
"delay":4.750
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":7.967,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- ------------------------ ---------------- -------- --------------------- ------
rsti_0io.PIC_inst/CLK->rsti_0io.PIC_inst/Q
SIOLOGIC_CORE_IOL_R24A C2INP_DEL 0.477 3.217 38
top_reveal_coretop_instance/core0/tm_u/secured_signal_1_89
NET DELAY 4.750 7.967 38
{CNT03/Couti_reg[3].ff_inst/LSR CNT03/Couti_reg[4].ff_inst/LSR}
ENDPOINT 0.000 7.967 1
Destination Clock Path
{
"path_begin":
{
"type":"pin",
"log_name":"OSCA001.OSCA_inst/HFCLKOUT",
"phy_name":"OSCA001.OSCA_inst/HFCLKOUT"
},
"path_end":
{
"type":"pin",
"log_name":"CNT03/Couti_reg[3].ff_inst/CLK",
"phy_name":"CNT03.un1_Couti_cry_3_0/CLK"
},
"path_sections":[
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":8.888,
"delay":0.000
},
{
"type":"net_delay",
"net":
{
"log_name":"top_reveal_coretop_instance/core0/tm_u/secured_instance_1_105/secured_signal_0_141",
"phy_name":"clk150"
},
"arrive":11.394,
"delay":2.506
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":11.394,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- ------------------------ ---------------- -------- --------------------- ------
CONSTRAINT 0.000 8.888 1
OSCA001.OSCA_inst/HFCLKOUT OSC_CORE_OSC_CORE_R1C137 CLOCK LATENCY 0.000 8.888 324
top_reveal_coretop_instance/core0/tm_u/secured_instance_1_105/secured_signal_0_141
NET DELAY 2.506 11.394 324
{CNT03/Couti_reg[3].ff_inst/CLK CNT03/Couti_reg[4].ff_inst/CLK}
CLOCK PIN 0.000 11.394 1
Uncertainty -(0.000) 11.394
Common Path Skew 0.031 11.425
Setup time -(0.203) 11.222
---------------------------------------- ------------------------ ---------------- -------- --------------------- ------
Required Time 11.222
Arrival Time -(7.966)
---------------------------------------- ------------------------ ---------------- -------- --------------------- ------
Path Slack (Passed) 3.255
++++ Path 6 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Path Begin : rsti_0io.PIC_inst/Q (SIOLOGIC_CORE_IOL_R24A)
Path End : {CNT03/Couti_reg[5].ff_inst/LSR CNT03/Couti_reg[6].ff_inst/LSR} (SLICE_R61C9D)
Source Clock : clk150 (R)
Destination Clock: clk150 (R)
Logic Level : 1
Delay Ratio : 90.9% (route), 9.1% (logic)
Clock Skew : -0.234 ns
Setup Constraint : 8.888 ns
Common Path Skew : 0.031 ns
Path Slack : 3.255 ns (Passed)
Source Clock Path
{
"path_begin":
{
"type":"pin",
"log_name":"OSCA001.OSCA_inst/HFCLKOUT",
"phy_name":"OSCA001.OSCA_inst/HFCLKOUT"
},
"path_end":
{
"type":"pin",
"log_name":"rsti_0io.PIC_inst/CLK",
"phy_name":"reset_pad.bb_inst_IOL/SCLKIN"
},
"path_sections":[
{
"type":"net_delay",
"net":
{
"log_name":"top_reveal_coretop_instance/core0/tm_u/secured_instance_1_105/secured_signal_0_141",
"phy_name":"clk150"
},
"arrive":2.740,
"delay":2.740
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":2.740,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- ------------------------ ---------------- -------- --------------------- ------
OSCA001.OSCA_inst/HFCLKOUT OSC_CORE_OSC_CORE_R1C137 CLOCK LATENCY 0.000 0.000 324
top_reveal_coretop_instance/core0/tm_u/secured_instance_1_105/secured_signal_0_141
NET DELAY 2.740 2.740 324
rsti_0io.PIC_inst/CLK CLOCK PIN 0.000 2.740 1
Data Path
{
"path_begin":
{
"type":"pin",
"log_name":"rsti_0io.PIC_inst/Q",
"phy_name":"reset_pad.bb_inst_IOL/INFF"
},
"path_end":
{
"type":"pin",
"log_name":"{CNT03/Couti_reg[5].ff_inst/LSR CNT03/Couti_reg[6].ff_inst/LSR}",
"phy_name":"CNT03.un1_Couti_cry_5_0/LSR"
},
"path_sections":[
{
"type":"site_delay",
"pin0":
{
"log_name":"rsti_0io.PIC_inst/CLK",
"phy_name":"reset_pad.bb_inst_IOL/SCLKIN"
},
"pin1":
{
"log_name":"rsti_0io.PIC_inst/Q",
"phy_name":"reset_pad.bb_inst_IOL/INFF"
},
"arrive":3.217,
"delay":0.477
},
{
"type":"net_delay",
"net":
{
"log_name":"top_reveal_coretop_instance/core0/tm_u/secured_signal_1_89",
"phy_name":"rsti_1"
},
"arrive":7.967,
"delay":4.750
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":7.967,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- ------------------------ ---------------- -------- --------------------- ------
rsti_0io.PIC_inst/CLK->rsti_0io.PIC_inst/Q
SIOLOGIC_CORE_IOL_R24A C2INP_DEL 0.477 3.217 38
top_reveal_coretop_instance/core0/tm_u/secured_signal_1_89
NET DELAY 4.750 7.967 38
{CNT03/Couti_reg[5].ff_inst/LSR CNT03/Couti_reg[6].ff_inst/LSR}
ENDPOINT 0.000 7.967 1
Destination Clock Path
{
"path_begin":
{
"type":"pin",
"log_name":"OSCA001.OSCA_inst/HFCLKOUT",
"phy_name":"OSCA001.OSCA_inst/HFCLKOUT"
},
"path_end":
{
"type":"pin",
"log_name":"CNT03/Couti_reg[5].ff_inst/CLK",
"phy_name":"CNT03.un1_Couti_cry_5_0/CLK"
},
"path_sections":[
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":8.888,
"delay":0.000
},
{
"type":"net_delay",
"net":
{
"log_name":"top_reveal_coretop_instance/core0/tm_u/secured_instance_1_105/secured_signal_0_141",
"phy_name":"clk150"
},
"arrive":11.394,
"delay":2.506
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":11.394,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- ------------------------ ---------------- -------- --------------------- ------
CONSTRAINT 0.000 8.888 1
OSCA001.OSCA_inst/HFCLKOUT OSC_CORE_OSC_CORE_R1C137 CLOCK LATENCY 0.000 8.888 324
top_reveal_coretop_instance/core0/tm_u/secured_instance_1_105/secured_signal_0_141
NET DELAY 2.506 11.394 324
{CNT03/Couti_reg[5].ff_inst/CLK CNT03/Couti_reg[6].ff_inst/CLK}
CLOCK PIN 0.000 11.394 1
Uncertainty -(0.000) 11.394
Common Path Skew 0.031 11.425
Setup time -(0.203) 11.222
---------------------------------------- ------------------------ ---------------- -------- --------------------- ------
Required Time 11.222
Arrival Time -(7.966)
---------------------------------------- ------------------------ ---------------- -------- --------------------- ------
Path Slack (Passed) 3.255
++++ Path 7 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Path Begin : rsti_0io.PIC_inst/Q (SIOLOGIC_CORE_IOL_R24A)
Path End : {CNT03/Couti_reg[7].ff_inst/LSR CNT03/Couti_reg[8].ff_inst/LSR} (SLICE_R61C10A)
Source Clock : clk150 (R)
Destination Clock: clk150 (R)
Logic Level : 1
Delay Ratio : 90.8% (route), 9.2% (logic)
Clock Skew : -0.234 ns
Setup Constraint : 8.888 ns
Common Path Skew : 0.031 ns
Path Slack : 3.292 ns (Passed)
Source Clock Path
{
"path_begin":
{
"type":"pin",
"log_name":"OSCA001.OSCA_inst/HFCLKOUT",
"phy_name":"OSCA001.OSCA_inst/HFCLKOUT"
},
"path_end":
{
"type":"pin",
"log_name":"rsti_0io.PIC_inst/CLK",
"phy_name":"reset_pad.bb_inst_IOL/SCLKIN"
},
"path_sections":[
{
"type":"net_delay",
"net":
{
"log_name":"top_reveal_coretop_instance/core0/tm_u/secured_instance_1_105/secured_signal_0_141",
"phy_name":"clk150"
},
"arrive":2.740,
"delay":2.740
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":2.740,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- ------------------------ ---------------- -------- --------------------- ------
OSCA001.OSCA_inst/HFCLKOUT OSC_CORE_OSC_CORE_R1C137 CLOCK LATENCY 0.000 0.000 324
top_reveal_coretop_instance/core0/tm_u/secured_instance_1_105/secured_signal_0_141
NET DELAY 2.740 2.740 324
rsti_0io.PIC_inst/CLK CLOCK PIN 0.000 2.740 1
Data Path
{
"path_begin":
{
"type":"pin",
"log_name":"rsti_0io.PIC_inst/Q",
"phy_name":"reset_pad.bb_inst_IOL/INFF"
},
"path_end":
{
"type":"pin",
"log_name":"{CNT03/Couti_reg[7].ff_inst/LSR CNT03/Couti_reg[8].ff_inst/LSR}",
"phy_name":"CNT03.un1_Couti_cry_7_0/LSR"
},
"path_sections":[
{
"type":"site_delay",
"pin0":
{
"log_name":"rsti_0io.PIC_inst/CLK",
"phy_name":"reset_pad.bb_inst_IOL/SCLKIN"
},
"pin1":
{
"log_name":"rsti_0io.PIC_inst/Q",
"phy_name":"reset_pad.bb_inst_IOL/INFF"
},
"arrive":3.217,
"delay":0.477
},
{
"type":"net_delay",
"net":
{
"log_name":"top_reveal_coretop_instance/core0/tm_u/secured_signal_1_89",
"phy_name":"rsti_1"
},
"arrive":7.930,
"delay":4.713
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":7.930,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- ------------------------ ---------------- -------- --------------------- ------
rsti_0io.PIC_inst/CLK->rsti_0io.PIC_inst/Q
SIOLOGIC_CORE_IOL_R24A C2INP_DEL 0.477 3.217 38
top_reveal_coretop_instance/core0/tm_u/secured_signal_1_89
NET DELAY 4.713 7.930 38
{CNT03/Couti_reg[7].ff_inst/LSR CNT03/Couti_reg[8].ff_inst/LSR}
ENDPOINT 0.000 7.930 1
Destination Clock Path
{
"path_begin":
{
"type":"pin",
"log_name":"OSCA001.OSCA_inst/HFCLKOUT",
"phy_name":"OSCA001.OSCA_inst/HFCLKOUT"
},
"path_end":
{
"type":"pin",
"log_name":"CNT03/Couti_reg[7].ff_inst/CLK",
"phy_name":"CNT03.un1_Couti_cry_7_0/CLK"
},
"path_sections":[
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":8.888,
"delay":0.000
},
{
"type":"net_delay",
"net":
{
"log_name":"top_reveal_coretop_instance/core0/tm_u/secured_instance_1_105/secured_signal_0_141",
"phy_name":"clk150"
},
"arrive":11.394,
"delay":2.506
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":11.394,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- ------------------------ ---------------- -------- --------------------- ------
CONSTRAINT 0.000 8.888 1
OSCA001.OSCA_inst/HFCLKOUT OSC_CORE_OSC_CORE_R1C137 CLOCK LATENCY 0.000 8.888 324
top_reveal_coretop_instance/core0/tm_u/secured_instance_1_105/secured_signal_0_141
NET DELAY 2.506 11.394 324
{CNT03/Couti_reg[7].ff_inst/CLK CNT03/Couti_reg[8].ff_inst/CLK}
CLOCK PIN 0.000 11.394 1
Uncertainty -(0.000) 11.394
Common Path Skew 0.031 11.425
Setup time -(0.203) 11.222
---------------------------------------- ------------------------ ---------------- -------- --------------------- ------
Required Time 11.222
Arrival Time -(7.929)
---------------------------------------- ------------------------ ---------------- -------- --------------------- ------
Path Slack (Passed) 3.292
++++ Path 8 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Path Begin : rsti_0io.PIC_inst/Q (SIOLOGIC_CORE_IOL_R24A)
Path End : {CNT03/Couti_reg[9].ff_inst/LSR CNT03/Couti_reg[10].ff_inst/LSR} (SLICE_R61C10B)
Source Clock : clk150 (R)
Destination Clock: clk150 (R)
Logic Level : 1
Delay Ratio : 90.8% (route), 9.2% (logic)
Clock Skew : -0.234 ns
Setup Constraint : 8.888 ns
Common Path Skew : 0.031 ns
Path Slack : 3.292 ns (Passed)
Source Clock Path
{
"path_begin":
{
"type":"pin",
"log_name":"OSCA001.OSCA_inst/HFCLKOUT",
"phy_name":"OSCA001.OSCA_inst/HFCLKOUT"
},
"path_end":
{
"type":"pin",
"log_name":"rsti_0io.PIC_inst/CLK",
"phy_name":"reset_pad.bb_inst_IOL/SCLKIN"
},
"path_sections":[
{
"type":"net_delay",
"net":
{
"log_name":"top_reveal_coretop_instance/core0/tm_u/secured_instance_1_105/secured_signal_0_141",
"phy_name":"clk150"
},
"arrive":2.740,
"delay":2.740
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":2.740,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- ------------------------ ---------------- -------- --------------------- ------
OSCA001.OSCA_inst/HFCLKOUT OSC_CORE_OSC_CORE_R1C137 CLOCK LATENCY 0.000 0.000 324
top_reveal_coretop_instance/core0/tm_u/secured_instance_1_105/secured_signal_0_141
NET DELAY 2.740 2.740 324
rsti_0io.PIC_inst/CLK CLOCK PIN 0.000 2.740 1
Data Path
{
"path_begin":
{
"type":"pin",
"log_name":"rsti_0io.PIC_inst/Q",
"phy_name":"reset_pad.bb_inst_IOL/INFF"
},
"path_end":
{
"type":"pin",
"log_name":"{CNT03/Couti_reg[9].ff_inst/LSR CNT03/Couti_reg[10].ff_inst/LSR}",
"phy_name":"CNT03.un1_Couti_cry_9_0/LSR"
},
"path_sections":[
{
"type":"site_delay",
"pin0":
{
"log_name":"rsti_0io.PIC_inst/CLK",
"phy_name":"reset_pad.bb_inst_IOL/SCLKIN"
},
"pin1":
{
"log_name":"rsti_0io.PIC_inst/Q",
"phy_name":"reset_pad.bb_inst_IOL/INFF"
},
"arrive":3.217,
"delay":0.477
},
{
"type":"net_delay",
"net":
{
"log_name":"top_reveal_coretop_instance/core0/tm_u/secured_signal_1_89",
"phy_name":"rsti_1"
},
"arrive":7.930,
"delay":4.713
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":7.930,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- ------------------------ ---------------- -------- --------------------- ------
rsti_0io.PIC_inst/CLK->rsti_0io.PIC_inst/Q
SIOLOGIC_CORE_IOL_R24A C2INP_DEL 0.477 3.217 38
top_reveal_coretop_instance/core0/tm_u/secured_signal_1_89
NET DELAY 4.713 7.930 38
{CNT03/Couti_reg[9].ff_inst/LSR CNT03/Couti_reg[10].ff_inst/LSR}
ENDPOINT 0.000 7.930 1
Destination Clock Path
{
"path_begin":
{
"type":"pin",
"log_name":"OSCA001.OSCA_inst/HFCLKOUT",
"phy_name":"OSCA001.OSCA_inst/HFCLKOUT"
},
"path_end":
{
"type":"pin",
"log_name":"CNT03/Couti_reg[9].ff_inst/CLK",
"phy_name":"CNT03.un1_Couti_cry_9_0/CLK"
},
"path_sections":[
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":8.888,
"delay":0.000
},
{
"type":"net_delay",
"net":
{
"log_name":"top_reveal_coretop_instance/core0/tm_u/secured_instance_1_105/secured_signal_0_141",
"phy_name":"clk150"
},
"arrive":11.394,
"delay":2.506
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":11.394,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- ------------------------ ---------------- -------- --------------------- ------
CONSTRAINT 0.000 8.888 1
OSCA001.OSCA_inst/HFCLKOUT OSC_CORE_OSC_CORE_R1C137 CLOCK LATENCY 0.000 8.888 324
top_reveal_coretop_instance/core0/tm_u/secured_instance_1_105/secured_signal_0_141
NET DELAY 2.506 11.394 324
{CNT03/Couti_reg[9].ff_inst/CLK CNT03/Couti_reg[10].ff_inst/CLK}
CLOCK PIN 0.000 11.394 1
Uncertainty -(0.000) 11.394
Common Path Skew 0.031 11.425
Setup time -(0.203) 11.222
---------------------------------------- ------------------------ ---------------- -------- --------------------- ------
Required Time 11.222
Arrival Time -(7.929)
---------------------------------------- ------------------------ ---------------- -------- --------------------- ------
Path Slack (Passed) 3.292
++++ Path 9 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Path Begin : rsti_0io.PIC_inst/Q (SIOLOGIC_CORE_IOL_R24A)
Path End : {CNT03/Couti_reg[11].ff_inst/LSR CNT03/Couti_reg[12].ff_inst/LSR} (SLICE_R61C10C)
Source Clock : clk150 (R)
Destination Clock: clk150 (R)
Logic Level : 1
Delay Ratio : 90.8% (route), 9.2% (logic)
Clock Skew : -0.234 ns
Setup Constraint : 8.888 ns
Common Path Skew : 0.031 ns
Path Slack : 3.292 ns (Passed)
Source Clock Path
{
"path_begin":
{
"type":"pin",
"log_name":"OSCA001.OSCA_inst/HFCLKOUT",
"phy_name":"OSCA001.OSCA_inst/HFCLKOUT"
},
"path_end":
{
"type":"pin",
"log_name":"rsti_0io.PIC_inst/CLK",
"phy_name":"reset_pad.bb_inst_IOL/SCLKIN"
},
"path_sections":[
{
"type":"net_delay",
"net":
{
"log_name":"top_reveal_coretop_instance/core0/tm_u/secured_instance_1_105/secured_signal_0_141",
"phy_name":"clk150"
},
"arrive":2.740,
"delay":2.740
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":2.740,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- ------------------------ ---------------- -------- --------------------- ------
OSCA001.OSCA_inst/HFCLKOUT OSC_CORE_OSC_CORE_R1C137 CLOCK LATENCY 0.000 0.000 324
top_reveal_coretop_instance/core0/tm_u/secured_instance_1_105/secured_signal_0_141
NET DELAY 2.740 2.740 324
rsti_0io.PIC_inst/CLK CLOCK PIN 0.000 2.740 1
Data Path
{
"path_begin":
{
"type":"pin",
"log_name":"rsti_0io.PIC_inst/Q",
"phy_name":"reset_pad.bb_inst_IOL/INFF"
},
"path_end":
{
"type":"pin",
"log_name":"{CNT03/Couti_reg[11].ff_inst/LSR CNT03/Couti_reg[12].ff_inst/LSR}",
"phy_name":"CNT03.un1_Couti_cry_11_0/LSR"
},
"path_sections":[
{
"type":"site_delay",
"pin0":
{
"log_name":"rsti_0io.PIC_inst/CLK",
"phy_name":"reset_pad.bb_inst_IOL/SCLKIN"
},
"pin1":
{
"log_name":"rsti_0io.PIC_inst/Q",
"phy_name":"reset_pad.bb_inst_IOL/INFF"
},
"arrive":3.217,
"delay":0.477
},
{
"type":"net_delay",
"net":
{
"log_name":"top_reveal_coretop_instance/core0/tm_u/secured_signal_1_89",
"phy_name":"rsti_1"
},
"arrive":7.930,
"delay":4.713
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":7.930,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- ------------------------ ---------------- -------- --------------------- ------
rsti_0io.PIC_inst/CLK->rsti_0io.PIC_inst/Q
SIOLOGIC_CORE_IOL_R24A C2INP_DEL 0.477 3.217 38
top_reveal_coretop_instance/core0/tm_u/secured_signal_1_89
NET DELAY 4.713 7.930 38
{CNT03/Couti_reg[11].ff_inst/LSR CNT03/Couti_reg[12].ff_inst/LSR}
ENDPOINT 0.000 7.930 1
Destination Clock Path
{
"path_begin":
{
"type":"pin",
"log_name":"OSCA001.OSCA_inst/HFCLKOUT",
"phy_name":"OSCA001.OSCA_inst/HFCLKOUT"
},
"path_end":
{
"type":"pin",
"log_name":"CNT03/Couti_reg[11].ff_inst/CLK",
"phy_name":"CNT03.un1_Couti_cry_11_0/CLK"
},
"path_sections":[
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":8.888,
"delay":0.000
},
{
"type":"net_delay",
"net":
{
"log_name":"top_reveal_coretop_instance/core0/tm_u/secured_instance_1_105/secured_signal_0_141",
"phy_name":"clk150"
},
"arrive":11.394,
"delay":2.506
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":11.394,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- ------------------------ ---------------- -------- --------------------- ------
CONSTRAINT 0.000 8.888 1
OSCA001.OSCA_inst/HFCLKOUT OSC_CORE_OSC_CORE_R1C137 CLOCK LATENCY 0.000 8.888 324
top_reveal_coretop_instance/core0/tm_u/secured_instance_1_105/secured_signal_0_141
NET DELAY 2.506 11.394 324
{CNT03/Couti_reg[11].ff_inst/CLK CNT03/Couti_reg[12].ff_inst/CLK}
CLOCK PIN 0.000 11.394 1
Uncertainty -(0.000) 11.394
Common Path Skew 0.031 11.425
Setup time -(0.203) 11.222
---------------------------------------- ------------------------ ---------------- -------- --------------------- ------
Required Time 11.222
Arrival Time -(7.929)
---------------------------------------- ------------------------ ---------------- -------- --------------------- ------
Path Slack (Passed) 3.292
++++ Path 10 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Path Begin : rsti_0io.PIC_inst/Q (SIOLOGIC_CORE_IOL_R24A)
Path End : {CNT03/Couti_reg[13].ff_inst/LSR CNT03/Couti_reg[14].ff_inst/LSR} (SLICE_R61C10D)
Source Clock : clk150 (R)
Destination Clock: clk150 (R)
Logic Level : 1
Delay Ratio : 90.8% (route), 9.2% (logic)
Clock Skew : -0.234 ns
Setup Constraint : 8.888 ns
Common Path Skew : 0.031 ns
Path Slack : 3.292 ns (Passed)
Source Clock Path
{
"path_begin":
{
"type":"pin",
"log_name":"OSCA001.OSCA_inst/HFCLKOUT",
"phy_name":"OSCA001.OSCA_inst/HFCLKOUT"
},
"path_end":
{
"type":"pin",
"log_name":"rsti_0io.PIC_inst/CLK",
"phy_name":"reset_pad.bb_inst_IOL/SCLKIN"
},
"path_sections":[
{
"type":"net_delay",
"net":
{
"log_name":"top_reveal_coretop_instance/core0/tm_u/secured_instance_1_105/secured_signal_0_141",
"phy_name":"clk150"
},
"arrive":2.740,
"delay":2.740
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":2.740,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- ------------------------ ---------------- -------- --------------------- ------
OSCA001.OSCA_inst/HFCLKOUT OSC_CORE_OSC_CORE_R1C137 CLOCK LATENCY 0.000 0.000 324
top_reveal_coretop_instance/core0/tm_u/secured_instance_1_105/secured_signal_0_141
NET DELAY 2.740 2.740 324
rsti_0io.PIC_inst/CLK CLOCK PIN 0.000 2.740 1
Data Path
{
"path_begin":
{
"type":"pin",
"log_name":"rsti_0io.PIC_inst/Q",
"phy_name":"reset_pad.bb_inst_IOL/INFF"
},
"path_end":
{
"type":"pin",
"log_name":"{CNT03/Couti_reg[13].ff_inst/LSR CNT03/Couti_reg[14].ff_inst/LSR}",
"phy_name":"CNT03.un1_Couti_cry_13_0/LSR"
},
"path_sections":[
{
"type":"site_delay",
"pin0":
{
"log_name":"rsti_0io.PIC_inst/CLK",
"phy_name":"reset_pad.bb_inst_IOL/SCLKIN"
},
"pin1":
{
"log_name":"rsti_0io.PIC_inst/Q",
"phy_name":"reset_pad.bb_inst_IOL/INFF"
},
"arrive":3.217,
"delay":0.477
},
{
"type":"net_delay",
"net":
{
"log_name":"top_reveal_coretop_instance/core0/tm_u/secured_signal_1_89",
"phy_name":"rsti_1"
},
"arrive":7.930,
"delay":4.713
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":7.930,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- ------------------------ ---------------- -------- --------------------- ------
rsti_0io.PIC_inst/CLK->rsti_0io.PIC_inst/Q
SIOLOGIC_CORE_IOL_R24A C2INP_DEL 0.477 3.217 38
top_reveal_coretop_instance/core0/tm_u/secured_signal_1_89
NET DELAY 4.713 7.930 38
{CNT03/Couti_reg[13].ff_inst/LSR CNT03/Couti_reg[14].ff_inst/LSR}
ENDPOINT 0.000 7.930 1
Destination Clock Path
{
"path_begin":
{
"type":"pin",
"log_name":"OSCA001.OSCA_inst/HFCLKOUT",
"phy_name":"OSCA001.OSCA_inst/HFCLKOUT"
},
"path_end":
{
"type":"pin",
"log_name":"CNT03/Couti_reg[13].ff_inst/CLK",
"phy_name":"CNT03.un1_Couti_cry_13_0/CLK"
},
"path_sections":[
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":8.888,
"delay":0.000
},
{
"type":"net_delay",
"net":
{
"log_name":"top_reveal_coretop_instance/core0/tm_u/secured_instance_1_105/secured_signal_0_141",
"phy_name":"clk150"
},
"arrive":11.394,
"delay":2.506
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":11.394,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- ------------------------ ---------------- -------- --------------------- ------
CONSTRAINT 0.000 8.888 1
OSCA001.OSCA_inst/HFCLKOUT OSC_CORE_OSC_CORE_R1C137 CLOCK LATENCY 0.000 8.888 324
top_reveal_coretop_instance/core0/tm_u/secured_instance_1_105/secured_signal_0_141
NET DELAY 2.506 11.394 324
{CNT03/Couti_reg[13].ff_inst/CLK CNT03/Couti_reg[14].ff_inst/CLK}
CLOCK PIN 0.000 11.394 1
Uncertainty -(0.000) 11.394
Common Path Skew 0.031 11.425
Setup time -(0.203) 11.222
---------------------------------------- ------------------------ ---------------- -------- --------------------- ------
Required Time 11.222
Arrival Time -(7.929)
---------------------------------------- ------------------------ ---------------- -------- --------------------- ------
Path Slack (Passed) 3.292
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
End of Detailed Report for timing paths
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
##########################################################
4 Hold at Speed Grade m Corner at -40 Degrees
4.1 Endpoint slacks
-------------------------------------------------------
Listing 10 End Points | Slack
-------------------------------------------------------
top_reveal_coretop_instance/core0/trig_u/tu_1/secured_instance_13_123/DF
| 0.164 ns
top_reveal_coretop_instance/core0/trig_u/tu_1/secured_instance_13_130/DF
| 0.165 ns
top_reveal_coretop_instance/core0/trig_u/tu_4/secured_instance_10_122/DF
| 0.166 ns
top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_470/DF
| 0.166 ns
top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_484/DF
| 0.166 ns
top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_468/DF
| 0.166 ns
top_reveal_coretop_instance/core0/trig_u/tu_0/secured_instance_14_23/DF
| 0.167 ns
top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_486/DF
| 0.167 ns
top_reveal_coretop_instance/core0/trig_u/tu_3/secured_instance_11_120/DF
| 0.168 ns
top_reveal_coretop_instance/core0/trig_u/tu_4/secured_instance_10_124/DF
| 0.168 ns
-------------------------------------------------------
|
Hold # of endpoints with negative slack: | 0
|
-------------------------------------------------------
4.2 Detailed Report
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
Detail report of critical paths
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Detailed Report for timing paths
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++++Path 1 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Path Begin : top_reveal_coretop_instance/core0/trig_u/tu_1/secured_instance_13_139/Q (SLICE_R39C105A)
Path End : top_reveal_coretop_instance/core0/trig_u/tu_1/secured_instance_13_123/DF (SLICE_R39C105D)
Source Clock : clk150 (R)
Destination Clock: clk150 (R)
Logic Level : 1
Delay Ratio : 31.5% (route), 68.5% (logic)
Clock Skew : 0.113 ns
Hold Constraint : 0.000 ns
Common Path Skew : -0.111 ns
Path Slack : 0.164 ns (Passed)
Source Clock Path
{
"path_begin":
{
"type":"pin",
"log_name":"OSCA001.OSCA_inst/HFCLKOUT",
"phy_name":"OSCA001.OSCA_inst/HFCLKOUT"
},
"path_end":
{
"type":"pin",
"log_name":"top_reveal_coretop_instance/core0/trig_u/tu_1/secured_instance_13_139/CLK",
"phy_name":"top_reveal_coretop_instance.core0.trig_u.tu_1.Ida5hzuEFCs00yEov7kghIB[8]/CLK"
},
"path_sections":[
{
"type":"net_delay",
"net":
{
"log_name":"top_reveal_coretop_instance/core0/tm_u/secured_instance_1_105/secured_signal_0_141",
"phy_name":"clk150"
},
"arrive":1.808,
"delay":1.808
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":1.808,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- ------------------------ ---------------- ------ --------------------- ------
OSCA001.OSCA_inst/HFCLKOUT OSC_CORE_OSC_CORE_R1C137 CLOCK LATENCY 0.000 0.000 325
top_reveal_coretop_instance/core0/tm_u/secured_instance_1_105/secured_signal_0_141
NET DELAY 1.808 1.808 325
top_reveal_coretop_instance/core0/trig_u/tu_1/secured_instance_13_139/CLK
CLOCK PIN 0.000 1.808 1
Data Path
{
"path_begin":
{
"type":"pin",
"log_name":"top_reveal_coretop_instance/core0/trig_u/tu_1/secured_instance_13_139/Q",
"phy_name":"top_reveal_coretop_instance.core0.trig_u.tu_1.Ida5hzuEFCs00yEov7kghIB[8]/Q0"
},
"path_end":
{
"type":"pin",
"log_name":"top_reveal_coretop_instance/core0/trig_u/tu_1/secured_instance_13_123/DF",
"phy_name":"top_reveal_coretop_instance.core0.trig_u.tu_1.Ix4LFxrk0hFsajtbF9Bl9/M0"
},
"path_sections":[
{
"type":"site_delay",
"pin0":
{
"log_name":"top_reveal_coretop_instance/core0/trig_u/tu_1/secured_instance_13_139/CLK",
"phy_name":"top_reveal_coretop_instance.core0.trig_u.tu_1.Ida5hzuEFCs00yEov7kghIB[8]/CLK"
},
"pin1":
{
"log_name":"top_reveal_coretop_instance/core0/trig_u/tu_1/secured_instance_13_139/Q",
"phy_name":"top_reveal_coretop_instance.core0.trig_u.tu_1.Ida5hzuEFCs00yEov7kghIB[8]/Q0"
},
"arrive":1.986,
"delay":0.178
},
{
"type":"net_delay",
"net":
{
"log_name":"top_reveal_coretop_instance/core0/trig_u/tu_1/secured_signal_13_139",
"phy_name":"top_reveal_coretop_instance.core0.trig_u.tu_1.Nc8pHcEsIxIri"
},
"arrive":2.068,
"delay":0.082
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":2.068,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- ------------------------ ---------------- ------ --------------------- ------
top_reveal_coretop_instance/core0/trig_u/tu_1/secured_instance_13_139/CLK->top_reveal_coretop_instance/core0/trig_u/tu_1/secured_instance_13_139/Q
SLICE_R39C105A REG_DEL 0.178 1.986 5
top_reveal_coretop_instance/core0/trig_u/tu_1/secured_signal_13_139
NET DELAY 0.082 2.068 5
top_reveal_coretop_instance/core0/trig_u/tu_1/secured_instance_13_123/DF
ENDPOINT 0.000 2.068 1
Destination Clock Path
{
"path_begin":
{
"type":"pin",
"log_name":"OSCA001.OSCA_inst/HFCLKOUT",
"phy_name":"OSCA001.OSCA_inst/HFCLKOUT"
},
"path_end":
{
"type":"pin",
"log_name":"top_reveal_coretop_instance/core0/trig_u/tu_1/secured_instance_13_123/CLK",
"phy_name":"top_reveal_coretop_instance.core0.trig_u.tu_1.Ix4LFxrk0hFsajtbF9Bl9/CLK"
},
"path_sections":[
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":0.000,
"delay":0.000
},
{
"type":"net_delay",
"net":
{
"log_name":"top_reveal_coretop_instance/core0/tm_u/secured_instance_1_105/secured_signal_0_141",
"phy_name":"clk150"
},
"arrive":1.921,
"delay":1.921
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":1.921,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- ------------------------ ---------------- ------ --------------------- ------
CONSTRAINT 0.000 0.000 1
OSCA001.OSCA_inst/HFCLKOUT OSC_CORE_OSC_CORE_R1C137 CLOCK LATENCY 0.000 0.000 325
top_reveal_coretop_instance/core0/tm_u/secured_instance_1_105/secured_signal_0_141
NET DELAY 1.921 1.921 325
{top_reveal_coretop_instance/core0/trig_u/tu_1/secured_instance_13_123/CLK top_reveal_coretop_instance/core0/trig_u/tu_1/secured_instance_13_124/CLK}
CLOCK PIN 0.000 1.921 1
Uncertainty 0.000 1.921
Common Path Skew -0.111 1.810
Hold time 0.094 1.904
---------------------------------------- ------------------------ ---------------- ------ --------------------- ------
Required Time -1.904
Arrival Time 2.068
---------------------------------------- ------------------------ ---------------- ------ --------------------- ------
Path Slack (Passed) 0.164
++++ Path 2 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Path Begin : top_reveal_coretop_instance/core0/trig_u/tu_1/secured_instance_13_146/Q (SLICE_R39C105C)
Path End : top_reveal_coretop_instance/core0/trig_u/tu_1/secured_instance_13_130/DF (SLICE_R39C105B)
Source Clock : clk150 (R)
Destination Clock: clk150 (R)
Logic Level : 1
Delay Ratio : 31.4% (route), 68.6% (logic)
Clock Skew : 0.113 ns
Hold Constraint : 0.000 ns
Common Path Skew : -0.111 ns
Path Slack : 0.165 ns (Passed)
Source Clock Path
{
"path_begin":
{
"type":"pin",
"log_name":"OSCA001.OSCA_inst/HFCLKOUT",
"phy_name":"OSCA001.OSCA_inst/HFCLKOUT"
},
"path_end":
{
"type":"pin",
"log_name":"top_reveal_coretop_instance/core0/trig_u/tu_1/secured_instance_13_140/CLK",
"phy_name":"top_reveal_coretop_instance.core0.trig_u.tu_1.IeJDtew0zBltkd7wB019/CLK"
},
"path_sections":[
{
"type":"net_delay",
"net":
{
"log_name":"top_reveal_coretop_instance/core0/tm_u/secured_instance_1_105/secured_signal_0_141",
"phy_name":"clk150"
},
"arrive":1.808,
"delay":1.808
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":1.808,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- ------------------------ ---------------- ------ --------------------- ------
OSCA001.OSCA_inst/HFCLKOUT OSC_CORE_OSC_CORE_R1C137 CLOCK LATENCY 0.000 0.000 325
top_reveal_coretop_instance/core0/tm_u/secured_instance_1_105/secured_signal_0_141
NET DELAY 1.808 1.808 325
{top_reveal_coretop_instance/core0/trig_u/tu_1/secured_instance_13_140/CLK top_reveal_coretop_instance/core0/trig_u/tu_1/secured_instance_13_146/CLK}
CLOCK PIN 0.000 1.808 1
Data Path
{
"path_begin":
{
"type":"pin",
"log_name":"top_reveal_coretop_instance/core0/trig_u/tu_1/secured_instance_13_146/Q",
"phy_name":"top_reveal_coretop_instance.core0.trig_u.tu_1.IeJDtew0zBltkd7wB019/Q1"
},
"path_end":
{
"type":"pin",
"log_name":"top_reveal_coretop_instance/core0/trig_u/tu_1/secured_instance_13_130/DF",
"phy_name":"top_reveal_coretop_instance.core0.trig_u.tu_1.IeJDtew0zBltkd7wB01D/M1"
},
"path_sections":[
{
"type":"site_delay",
"pin0":
{
"log_name":"top_reveal_coretop_instance/core0/trig_u/tu_1/secured_instance_13_146/CLK",
"phy_name":"top_reveal_coretop_instance.core0.trig_u.tu_1.IeJDtew0zBltkd7wB019/CLK"
},
"pin1":
{
"log_name":"top_reveal_coretop_instance/core0/trig_u/tu_1/secured_instance_13_146/Q",
"phy_name":"top_reveal_coretop_instance.core0.trig_u.tu_1.IeJDtew0zBltkd7wB019/Q1"
},
"arrive":1.987,
"delay":0.179
},
{
"type":"net_delay",
"net":
{
"log_name":"top_reveal_coretop_instance/core0/trig_u/tu_1/secured_signal_13_146",
"phy_name":"top_reveal_coretop_instance.core0.trig_u.tu_1.NoxeB5huJp20Cv"
},
"arrive":2.069,
"delay":0.082
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":2.069,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- ------------------------ ---------------- ------ --------------------- ------
top_reveal_coretop_instance/core0/trig_u/tu_1/secured_instance_13_146/CLK->top_reveal_coretop_instance/core0/trig_u/tu_1/secured_instance_13_146/Q
SLICE_R39C105C REG_DEL 0.179 1.987 5
top_reveal_coretop_instance/core0/trig_u/tu_1/secured_signal_13_146
NET DELAY 0.082 2.069 5
top_reveal_coretop_instance/core0/trig_u/tu_1/secured_instance_13_130/DF
ENDPOINT 0.000 2.069 1
Destination Clock Path
{
"path_begin":
{
"type":"pin",
"log_name":"OSCA001.OSCA_inst/HFCLKOUT",
"phy_name":"OSCA001.OSCA_inst/HFCLKOUT"
},
"path_end":
{
"type":"pin",
"log_name":"top_reveal_coretop_instance/core0/trig_u/tu_1/secured_instance_13_129/CLK",
"phy_name":"top_reveal_coretop_instance.core0.trig_u.tu_1.IeJDtew0zBltkd7wB01D/CLK"
},
"path_sections":[
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":0.000,
"delay":0.000
},
{
"type":"net_delay",
"net":
{
"log_name":"top_reveal_coretop_instance/core0/tm_u/secured_instance_1_105/secured_signal_0_141",
"phy_name":"clk150"
},
"arrive":1.921,
"delay":1.921
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":1.921,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- ------------------------ ---------------- ------ --------------------- ------
CONSTRAINT 0.000 0.000 1
OSCA001.OSCA_inst/HFCLKOUT OSC_CORE_OSC_CORE_R1C137 CLOCK LATENCY 0.000 0.000 325
top_reveal_coretop_instance/core0/tm_u/secured_instance_1_105/secured_signal_0_141
NET DELAY 1.921 1.921 325
{top_reveal_coretop_instance/core0/trig_u/tu_1/secured_instance_13_129/CLK top_reveal_coretop_instance/core0/trig_u/tu_1/secured_instance_13_130/CLK}
CLOCK PIN 0.000 1.921 1
Uncertainty 0.000 1.921
Common Path Skew -0.111 1.810
Hold time 0.094 1.904
---------------------------------------- ------------------------ ---------------- ------ --------------------- ------
Required Time -1.904
Arrival Time 2.069
---------------------------------------- ------------------------ ---------------- ------ --------------------- ------
Path Slack (Passed) 0.165
++++ Path 3 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Path Begin : top_reveal_coretop_instance/core0/trig_u/tu_4/secured_instance_10_138/Q (SLICE_R33C109C)
Path End : top_reveal_coretop_instance/core0/trig_u/tu_4/secured_instance_10_122/DF (SLICE_R33C109D)
Source Clock : clk150 (R)
Destination Clock: clk150 (R)
Logic Level : 1
Delay Ratio : 31.5% (route), 68.5% (logic)
Clock Skew : 0.113 ns
Hold Constraint : 0.000 ns
Common Path Skew : -0.113 ns
Path Slack : 0.166 ns (Passed)
Source Clock Path
{
"path_begin":
{
"type":"pin",
"log_name":"OSCA001.OSCA_inst/HFCLKOUT",
"phy_name":"OSCA001.OSCA_inst/HFCLKOUT"
},
"path_end":
{
"type":"pin",
"log_name":"top_reveal_coretop_instance/core0/trig_u/tu_4/secured_instance_10_138/CLK",
"phy_name":"top_reveal_coretop_instance.core0.trig_u.tu_4.IeJDtew0zBltkd7wB01B/CLK"
},
"path_sections":[
{
"type":"net_delay",
"net":
{
"log_name":"top_reveal_coretop_instance/core0/tm_u/secured_instance_1_105/secured_signal_0_141",
"phy_name":"clk150"
},
"arrive":1.808,
"delay":1.808
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":1.808,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- ------------------------ ---------------- ------ --------------------- ------
OSCA001.OSCA_inst/HFCLKOUT OSC_CORE_OSC_CORE_R1C137 CLOCK LATENCY 0.000 0.000 325
top_reveal_coretop_instance/core0/tm_u/secured_instance_1_105/secured_signal_0_141
NET DELAY 1.808 1.808 325
{top_reveal_coretop_instance/core0/trig_u/tu_4/secured_instance_10_138/CLK top_reveal_coretop_instance/core0/trig_u/tu_4/secured_instance_10_142/CLK}
CLOCK PIN 0.000 1.808 1
Data Path
{
"path_begin":
{
"type":"pin",
"log_name":"top_reveal_coretop_instance/core0/trig_u/tu_4/secured_instance_10_138/Q",
"phy_name":"top_reveal_coretop_instance.core0.trig_u.tu_4.IeJDtew0zBltkd7wB01B/Q0"
},
"path_end":
{
"type":"pin",
"log_name":"top_reveal_coretop_instance/core0/trig_u/tu_4/secured_instance_10_122/DF",
"phy_name":"top_reveal_coretop_instance.core0.trig_u.tu_4.Ix4LFxrk0hFsajtbF9BlB/M1"
},
"path_sections":[
{
"type":"site_delay",
"pin0":
{
"log_name":"top_reveal_coretop_instance/core0/trig_u/tu_4/secured_instance_10_138/CLK",
"phy_name":"top_reveal_coretop_instance.core0.trig_u.tu_4.IeJDtew0zBltkd7wB01B/CLK"
},
"pin1":
{
"log_name":"top_reveal_coretop_instance/core0/trig_u/tu_4/secured_instance_10_138/Q",
"phy_name":"top_reveal_coretop_instance.core0.trig_u.tu_4.IeJDtew0zBltkd7wB01B/Q0"
},
"arrive":1.986,
"delay":0.178
},
{
"type":"net_delay",
"net":
{
"log_name":"top_reveal_coretop_instance/core0/trig_u/tu_4/secured_signal_10_138",
"phy_name":"top_reveal_coretop_instance.core0.trig_u.tu_4.Nc8pHcEsIxIrh"
},
"arrive":2.068,
"delay":0.082
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":2.068,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- ------------------------ ---------------- ------ --------------------- ------
top_reveal_coretop_instance/core0/trig_u/tu_4/secured_instance_10_138/CLK->top_reveal_coretop_instance/core0/trig_u/tu_4/secured_instance_10_138/Q
SLICE_R33C109C REG_DEL 0.178 1.986 5
top_reveal_coretop_instance/core0/trig_u/tu_4/secured_signal_10_138
NET DELAY 0.082 2.068 5
top_reveal_coretop_instance/core0/trig_u/tu_4/secured_instance_10_122/DF
ENDPOINT 0.000 2.068 1
Destination Clock Path
{
"path_begin":
{
"type":"pin",
"log_name":"OSCA001.OSCA_inst/HFCLKOUT",
"phy_name":"OSCA001.OSCA_inst/HFCLKOUT"
},
"path_end":
{
"type":"pin",
"log_name":"top_reveal_coretop_instance/core0/trig_u/tu_4/secured_instance_10_121/CLK",
"phy_name":"top_reveal_coretop_instance.core0.trig_u.tu_4.Ix4LFxrk0hFsajtbF9BlB/CLK"
},
"path_sections":[
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":0.000,
"delay":0.000
},
{
"type":"net_delay",
"net":
{
"log_name":"top_reveal_coretop_instance/core0/tm_u/secured_instance_1_105/secured_signal_0_141",
"phy_name":"clk150"
},
"arrive":1.921,
"delay":1.921
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":1.921,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- ------------------------ ---------------- ------ --------------------- ------
CONSTRAINT 0.000 0.000 1
OSCA001.OSCA_inst/HFCLKOUT OSC_CORE_OSC_CORE_R1C137 CLOCK LATENCY 0.000 0.000 325
top_reveal_coretop_instance/core0/tm_u/secured_instance_1_105/secured_signal_0_141
NET DELAY 1.921 1.921 325
{top_reveal_coretop_instance/core0/trig_u/tu_4/secured_instance_10_121/CLK top_reveal_coretop_instance/core0/trig_u/tu_4/secured_instance_10_122/CLK}
CLOCK PIN 0.000 1.921 1
Uncertainty 0.000 1.921
Common Path Skew -0.113 1.808
Hold time 0.094 1.902
---------------------------------------- ------------------------ ---------------- ------ --------------------- ------
Required Time -1.902
Arrival Time 2.068
---------------------------------------- ------------------------ ---------------- ------ --------------------- ------
Path Slack (Passed) 0.166
++++ Path 4 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Path Begin : top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_469/Q (SLICE_R44C108C)
Path End : top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_470/DF (SLICE_R44C108C)
Source Clock : clk150 (R)
Destination Clock: clk150 (R)
Logic Level : 1
Delay Ratio : 31.5% (route), 68.5% (logic)
Clock Skew : 0.113 ns
Hold Constraint : 0.000 ns
Common Path Skew : -0.113 ns
Path Slack : 0.166 ns (Passed)
Source Clock Path
{
"path_begin":
{
"type":"pin",
"log_name":"OSCA001.OSCA_inst/HFCLKOUT",
"phy_name":"OSCA001.OSCA_inst/HFCLKOUT"
},
"path_end":
{
"type":"pin",
"log_name":"top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_469/CLK",
"phy_name":"top_reveal_coretop_instance.core0.jtag_int_u.Ic4KmarKEnFbd/CLK"
},
"path_sections":[
{
"type":"net_delay",
"net":
{
"log_name":"top_reveal_coretop_instance/core0/tm_u/secured_instance_1_105/secured_signal_0_141",
"phy_name":"clk150"
},
"arrive":1.808,
"delay":1.808
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":1.808,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- ------------------------ ---------------- ------ --------------------- ------
OSCA001.OSCA_inst/HFCLKOUT OSC_CORE_OSC_CORE_R1C137 CLOCK LATENCY 0.000 0.000 325
top_reveal_coretop_instance/core0/tm_u/secured_instance_1_105/secured_signal_0_141
NET DELAY 1.808 1.808 325
{top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_469/CLK top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_470/CLK}
CLOCK PIN 0.000 1.808 1
Data Path
{
"path_begin":
{
"type":"pin",
"log_name":"top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_469/Q",
"phy_name":"top_reveal_coretop_instance.core0.jtag_int_u.Ic4KmarKEnFbd/Q0"
},
"path_end":
{
"type":"pin",
"log_name":"top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_470/DF",
"phy_name":"top_reveal_coretop_instance.core0.jtag_int_u.Ic4KmarKEnFbd/M1"
},
"path_sections":[
{
"type":"site_delay",
"pin0":
{
"log_name":"top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_469/CLK",
"phy_name":"top_reveal_coretop_instance.core0.jtag_int_u.Ic4KmarKEnFbd/CLK"
},
"pin1":
{
"log_name":"top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_469/Q",
"phy_name":"top_reveal_coretop_instance.core0.jtag_int_u.Ic4KmarKEnFbd/Q0"
},
"arrive":1.986,
"delay":0.178
},
{
"type":"net_delay",
"net":
{
"log_name":"top_reveal_coretop_instance/core0/jtag_int_u/secured_signal_2_156",
"phy_name":"top_reveal_coretop_instance.core0.jtag_int_u.Ne3nFILyd5q303pD9C8l[2]"
},
"arrive":2.068,
"delay":0.082
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":2.068,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- ------------------------ ---------------- ------ --------------------- ------
top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_469/CLK->top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_469/Q
SLICE_R44C108C REG_DEL 0.178 1.986 5
top_reveal_coretop_instance/core0/jtag_int_u/secured_signal_2_156
NET DELAY 0.082 2.068 5
top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_470/DF
ENDPOINT 0.000 2.068 1
Destination Clock Path
{
"path_begin":
{
"type":"pin",
"log_name":"OSCA001.OSCA_inst/HFCLKOUT",
"phy_name":"OSCA001.OSCA_inst/HFCLKOUT"
},
"path_end":
{
"type":"pin",
"log_name":"top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_469/CLK",
"phy_name":"top_reveal_coretop_instance.core0.jtag_int_u.Ic4KmarKEnFbd/CLK"
},
"path_sections":[
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":0.000,
"delay":0.000
},
{
"type":"net_delay",
"net":
{
"log_name":"top_reveal_coretop_instance/core0/tm_u/secured_instance_1_105/secured_signal_0_141",
"phy_name":"clk150"
},
"arrive":1.921,
"delay":1.921
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":1.921,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- ------------------------ ---------------- ------ --------------------- ------
CONSTRAINT 0.000 0.000 1
OSCA001.OSCA_inst/HFCLKOUT OSC_CORE_OSC_CORE_R1C137 CLOCK LATENCY 0.000 0.000 325
top_reveal_coretop_instance/core0/tm_u/secured_instance_1_105/secured_signal_0_141
NET DELAY 1.921 1.921 325
{top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_469/CLK top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_470/CLK}
CLOCK PIN 0.000 1.921 1
Uncertainty 0.000 1.921
Common Path Skew -0.113 1.808
Hold time 0.094 1.902
---------------------------------------- ------------------------ ---------------- ------ --------------------- ------
Required Time -1.902
Arrival Time 2.068
---------------------------------------- ------------------------ ---------------- ------ --------------------- ------
Path Slack (Passed) 0.166
++++ Path 5 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Path Begin : top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_483/Q (SLICE_R42C113D)
Path End : top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_484/DF (SLICE_R42C113D)
Source Clock : clk150 (R)
Destination Clock: clk150 (R)
Logic Level : 1
Delay Ratio : 31.5% (route), 68.5% (logic)
Clock Skew : 0.113 ns
Hold Constraint : 0.000 ns
Common Path Skew : -0.113 ns
Path Slack : 0.166 ns (Passed)
Source Clock Path
{
"path_begin":
{
"type":"pin",
"log_name":"OSCA001.OSCA_inst/HFCLKOUT",
"phy_name":"OSCA001.OSCA_inst/HFCLKOUT"
},
"path_end":
{
"type":"pin",
"log_name":"top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_483/CLK",
"phy_name":"top_reveal_coretop_instance.core0.jtag_int_u.Ieo15zDnCIDBEJ3zgix1[0].ff_inst/CLK"
},
"path_sections":[
{
"type":"net_delay",
"net":
{
"log_name":"top_reveal_coretop_instance/core0/tm_u/secured_instance_1_105/secured_signal_0_141",
"phy_name":"clk150"
},
"arrive":1.808,
"delay":1.808
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":1.808,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- ------------------------ ---------------- ------ --------------------- ------
OSCA001.OSCA_inst/HFCLKOUT OSC_CORE_OSC_CORE_R1C137 CLOCK LATENCY 0.000 0.000 325
top_reveal_coretop_instance/core0/tm_u/secured_instance_1_105/secured_signal_0_141
NET DELAY 1.808 1.808 325
{top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_483/CLK top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_484/CLK}
CLOCK PIN 0.000 1.808 1
Data Path
{
"path_begin":
{
"type":"pin",
"log_name":"top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_483/Q",
"phy_name":"top_reveal_coretop_instance.core0.jtag_int_u.Ieo15zDnCIDBEJ3zgix1[0].ff_inst/Q0"
},
"path_end":
{
"type":"pin",
"log_name":"top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_484/DF",
"phy_name":"top_reveal_coretop_instance.core0.jtag_int_u.Ieo15zDnCIDBEJ3zgix1[0].ff_inst/M1"
},
"path_sections":[
{
"type":"site_delay",
"pin0":
{
"log_name":"top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_483/CLK",
"phy_name":"top_reveal_coretop_instance.core0.jtag_int_u.Ieo15zDnCIDBEJ3zgix1[0].ff_inst/CLK"
},
"pin1":
{
"log_name":"top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_483/Q",
"phy_name":"top_reveal_coretop_instance.core0.jtag_int_u.Ieo15zDnCIDBEJ3zgix1[0].ff_inst/Q0"
},
"arrive":1.986,
"delay":0.178
},
{
"type":"net_delay",
"net":
{
"log_name":"top_reveal_coretop_instance/core0/jtag_int_u/secured_signal_2_162",
"phy_name":"top_reveal_coretop_instance.core0.jtag_int_u.Neo15zDnCIDBEJ3zgix1[0]"
},
"arrive":2.068,
"delay":0.082
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":2.068,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- ------------------------ ---------------- ------ --------------------- ------
top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_483/CLK->top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_483/Q
SLICE_R42C113D REG_DEL 0.178 1.986 1
top_reveal_coretop_instance/core0/jtag_int_u/secured_signal_2_162
NET DELAY 0.082 2.068 1
top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_484/DF
ENDPOINT 0.000 2.068 1
Destination Clock Path
{
"path_begin":
{
"type":"pin",
"log_name":"OSCA001.OSCA_inst/HFCLKOUT",
"phy_name":"OSCA001.OSCA_inst/HFCLKOUT"
},
"path_end":
{
"type":"pin",
"log_name":"top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_483/CLK",
"phy_name":"top_reveal_coretop_instance.core0.jtag_int_u.Ieo15zDnCIDBEJ3zgix1[0].ff_inst/CLK"
},
"path_sections":[
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":0.000,
"delay":0.000
},
{
"type":"net_delay",
"net":
{
"log_name":"top_reveal_coretop_instance/core0/tm_u/secured_instance_1_105/secured_signal_0_141",
"phy_name":"clk150"
},
"arrive":1.921,
"delay":1.921
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":1.921,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- ------------------------ ---------------- ------ --------------------- ------
CONSTRAINT 0.000 0.000 1
OSCA001.OSCA_inst/HFCLKOUT OSC_CORE_OSC_CORE_R1C137 CLOCK LATENCY 0.000 0.000 325
top_reveal_coretop_instance/core0/tm_u/secured_instance_1_105/secured_signal_0_141
NET DELAY 1.921 1.921 325
{top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_483/CLK top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_484/CLK}
CLOCK PIN 0.000 1.921 1
Uncertainty 0.000 1.921
Common Path Skew -0.113 1.808
Hold time 0.094 1.902
---------------------------------------- ------------------------ ---------------- ------ --------------------- ------
Required Time -1.902
Arrival Time 2.068
---------------------------------------- ------------------------ ---------------- ------ --------------------- ------
Path Slack (Passed) 0.166
++++ Path 6 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Path Begin : top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_467/Q (SLICE_R44C110D)
Path End : top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_468/DF (SLICE_R44C110D)
Source Clock : clk150 (R)
Destination Clock: clk150 (R)
Logic Level : 1
Delay Ratio : 31.5% (route), 68.5% (logic)
Clock Skew : 0.113 ns
Hold Constraint : 0.000 ns
Common Path Skew : -0.113 ns
Path Slack : 0.166 ns (Passed)
Source Clock Path
{
"path_begin":
{
"type":"pin",
"log_name":"OSCA001.OSCA_inst/HFCLKOUT",
"phy_name":"OSCA001.OSCA_inst/HFCLKOUT"
},
"path_end":
{
"type":"pin",
"log_name":"top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_467/CLK",
"phy_name":"top_reveal_coretop_instance.core0.jtag_int_u.Ie3nFILyd5q303pD9C8l[0].ff_inst/CLK"
},
"path_sections":[
{
"type":"net_delay",
"net":
{
"log_name":"top_reveal_coretop_instance/core0/tm_u/secured_instance_1_105/secured_signal_0_141",
"phy_name":"clk150"
},
"arrive":1.808,
"delay":1.808
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":1.808,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- ------------------------ ---------------- ------ --------------------- ------
OSCA001.OSCA_inst/HFCLKOUT OSC_CORE_OSC_CORE_R1C137 CLOCK LATENCY 0.000 0.000 325
top_reveal_coretop_instance/core0/tm_u/secured_instance_1_105/secured_signal_0_141
NET DELAY 1.808 1.808 325
{top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_467/CLK top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_468/CLK}
CLOCK PIN 0.000 1.808 1
Data Path
{
"path_begin":
{
"type":"pin",
"log_name":"top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_467/Q",
"phy_name":"top_reveal_coretop_instance.core0.jtag_int_u.Ie3nFILyd5q303pD9C8l[0].ff_inst/Q0"
},
"path_end":
{
"type":"pin",
"log_name":"top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_468/DF",
"phy_name":"top_reveal_coretop_instance.core0.jtag_int_u.Ie3nFILyd5q303pD9C8l[0].ff_inst/M1"
},
"path_sections":[
{
"type":"site_delay",
"pin0":
{
"log_name":"top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_467/CLK",
"phy_name":"top_reveal_coretop_instance.core0.jtag_int_u.Ie3nFILyd5q303pD9C8l[0].ff_inst/CLK"
},
"pin1":
{
"log_name":"top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_467/Q",
"phy_name":"top_reveal_coretop_instance.core0.jtag_int_u.Ie3nFILyd5q303pD9C8l[0].ff_inst/Q0"
},
"arrive":1.986,
"delay":0.178
},
{
"type":"net_delay",
"net":
{
"log_name":"top_reveal_coretop_instance/core0/jtag_int_u/secured_signal_2_158",
"phy_name":"top_reveal_coretop_instance.core0.jtag_int_u.Ne3nFILyd5q303pD9C8l[0]"
},
"arrive":2.068,
"delay":0.082
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":2.068,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- ------------------------ ---------------- ------ --------------------- ------
top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_467/CLK->top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_467/Q
SLICE_R44C110D REG_DEL 0.178 1.986 1
top_reveal_coretop_instance/core0/jtag_int_u/secured_signal_2_158
NET DELAY 0.082 2.068 1
top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_468/DF
ENDPOINT 0.000 2.068 1
Destination Clock Path
{
"path_begin":
{
"type":"pin",
"log_name":"OSCA001.OSCA_inst/HFCLKOUT",
"phy_name":"OSCA001.OSCA_inst/HFCLKOUT"
},
"path_end":
{
"type":"pin",
"log_name":"top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_467/CLK",
"phy_name":"top_reveal_coretop_instance.core0.jtag_int_u.Ie3nFILyd5q303pD9C8l[0].ff_inst/CLK"
},
"path_sections":[
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":0.000,
"delay":0.000
},
{
"type":"net_delay",
"net":
{
"log_name":"top_reveal_coretop_instance/core0/tm_u/secured_instance_1_105/secured_signal_0_141",
"phy_name":"clk150"
},
"arrive":1.921,
"delay":1.921
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":1.921,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- ------------------------ ---------------- ------ --------------------- ------
CONSTRAINT 0.000 0.000 1
OSCA001.OSCA_inst/HFCLKOUT OSC_CORE_OSC_CORE_R1C137 CLOCK LATENCY 0.000 0.000 325
top_reveal_coretop_instance/core0/tm_u/secured_instance_1_105/secured_signal_0_141
NET DELAY 1.921 1.921 325
{top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_467/CLK top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_468/CLK}
CLOCK PIN 0.000 1.921 1
Uncertainty 0.000 1.921
Common Path Skew -0.113 1.808
Hold time 0.094 1.902
---------------------------------------- ------------------------ ---------------- ------ --------------------- ------
Required Time -1.902
Arrival Time 2.068
---------------------------------------- ------------------------ ---------------- ------ --------------------- ------
Path Slack (Passed) 0.166
++++ Path 7 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Path Begin : top_reveal_coretop_instance/core0/trig_u/tu_0/secured_instance_14_24/Q (SLICE_R45C109D)
Path End : top_reveal_coretop_instance/core0/trig_u/tu_0/secured_instance_14_23/DF (SLICE_R45C109D)
Source Clock : clk150 (R)
Destination Clock: clk150 (R)
Logic Level : 1
Delay Ratio : 31.4% (route), 68.6% (logic)
Clock Skew : 0.113 ns
Hold Constraint : 0.000 ns
Common Path Skew : -0.113 ns
Path Slack : 0.167 ns (Passed)
Source Clock Path
{
"path_begin":
{
"type":"pin",
"log_name":"OSCA001.OSCA_inst/HFCLKOUT",
"phy_name":"OSCA001.OSCA_inst/HFCLKOUT"
},
"path_end":
{
"type":"pin",
"log_name":"top_reveal_coretop_instance/core0/trig_u/tu_0/secured_instance_14_23/CLK",
"phy_name":"top_reveal_coretop_instance.core0.trig_u.tcnt_0.IeJBDr8Dxu2CCavJGJsb/CLK"
},
"path_sections":[
{
"type":"net_delay",
"net":
{
"log_name":"top_reveal_coretop_instance/core0/tm_u/secured_instance_1_105/secured_signal_0_141",
"phy_name":"clk150"
},
"arrive":1.808,
"delay":1.808
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":1.808,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- ------------------------ ---------------- ------ --------------------- ------
OSCA001.OSCA_inst/HFCLKOUT OSC_CORE_OSC_CORE_R1C137 CLOCK LATENCY 0.000 0.000 325
top_reveal_coretop_instance/core0/tm_u/secured_instance_1_105/secured_signal_0_141
NET DELAY 1.808 1.808 325
{top_reveal_coretop_instance/core0/trig_u/tu_0/secured_instance_14_23/CLK top_reveal_coretop_instance/core0/trig_u/tu_0/secured_instance_14_24/CLK}
CLOCK PIN 0.000 1.808 1
Data Path
{
"path_begin":
{
"type":"pin",
"log_name":"top_reveal_coretop_instance/core0/trig_u/tu_0/secured_instance_14_24/Q",
"phy_name":"top_reveal_coretop_instance.core0.trig_u.tcnt_0.IeJBDr8Dxu2CCavJGJsb/Q1"
},
"path_end":
{
"type":"pin",
"log_name":"top_reveal_coretop_instance/core0/trig_u/tu_0/secured_instance_14_23/DF",
"phy_name":"top_reveal_coretop_instance.core0.trig_u.tcnt_0.IeJBDr8Dxu2CCavJGJsb/M0"
},
"path_sections":[
{
"type":"site_delay",
"pin0":
{
"log_name":"top_reveal_coretop_instance/core0/trig_u/tu_0/secured_instance_14_24/CLK",
"phy_name":"top_reveal_coretop_instance.core0.trig_u.tcnt_0.IeJBDr8Dxu2CCavJGJsb/CLK"
},
"pin1":
{
"log_name":"top_reveal_coretop_instance/core0/trig_u/tu_0/secured_instance_14_24/Q",
"phy_name":"top_reveal_coretop_instance.core0.trig_u.tcnt_0.IeJBDr8Dxu2CCavJGJsb/Q1"
},
"arrive":1.987,
"delay":0.179
},
{
"type":"net_delay",
"net":
{
"log_name":"top_reveal_coretop_instance/core0/trig_u/tu_0/secured_signal_14_18",
"phy_name":"top_reveal_coretop_instance.core0.trig_u.tu_0.NbvqsJxiwzrIDIH7[0]"
},
"arrive":2.069,
"delay":0.082
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":2.069,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- ------------------------ ---------------- ------ --------------------- ------
top_reveal_coretop_instance/core0/trig_u/tu_0/secured_instance_14_24/CLK->top_reveal_coretop_instance/core0/trig_u/tu_0/secured_instance_14_24/Q
SLICE_R45C109D REG_DEL 0.179 1.987 6
top_reveal_coretop_instance/core0/trig_u/tu_0/secured_signal_14_18
NET DELAY 0.082 2.069 6
top_reveal_coretop_instance/core0/trig_u/tu_0/secured_instance_14_23/DF
ENDPOINT 0.000 2.069 1
Destination Clock Path
{
"path_begin":
{
"type":"pin",
"log_name":"OSCA001.OSCA_inst/HFCLKOUT",
"phy_name":"OSCA001.OSCA_inst/HFCLKOUT"
},
"path_end":
{
"type":"pin",
"log_name":"top_reveal_coretop_instance/core0/trig_u/tu_0/secured_instance_14_23/CLK",
"phy_name":"top_reveal_coretop_instance.core0.trig_u.tcnt_0.IeJBDr8Dxu2CCavJGJsb/CLK"
},
"path_sections":[
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":0.000,
"delay":0.000
},
{
"type":"net_delay",
"net":
{
"log_name":"top_reveal_coretop_instance/core0/tm_u/secured_instance_1_105/secured_signal_0_141",
"phy_name":"clk150"
},
"arrive":1.921,
"delay":1.921
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":1.921,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- ------------------------ ---------------- ------ --------------------- ------
CONSTRAINT 0.000 0.000 1
OSCA001.OSCA_inst/HFCLKOUT OSC_CORE_OSC_CORE_R1C137 CLOCK LATENCY 0.000 0.000 325
top_reveal_coretop_instance/core0/tm_u/secured_instance_1_105/secured_signal_0_141
NET DELAY 1.921 1.921 325
{top_reveal_coretop_instance/core0/trig_u/tu_0/secured_instance_14_23/CLK top_reveal_coretop_instance/core0/trig_u/tu_0/secured_instance_14_24/CLK}
CLOCK PIN 0.000 1.921 1
Uncertainty 0.000 1.921
Common Path Skew -0.113 1.808
Hold time 0.094 1.902
---------------------------------------- ------------------------ ---------------- ------ --------------------- ------
Required Time -1.902
Arrival Time 2.069
---------------------------------------- ------------------------ ---------------- ------ --------------------- ------
Path Slack (Passed) 0.167
++++ Path 8 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Path Begin : top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_485/Q (SLICE_R45C112C)
Path End : top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_486/DF (SLICE_R45C112C)
Source Clock : clk150 (R)
Destination Clock: clk150 (R)
Logic Level : 1
Delay Ratio : 31.4% (route), 68.6% (logic)
Clock Skew : 0.113 ns
Hold Constraint : 0.000 ns
Common Path Skew : -0.113 ns
Path Slack : 0.167 ns (Passed)
Source Clock Path
{
"path_begin":
{
"type":"pin",
"log_name":"OSCA001.OSCA_inst/HFCLKOUT",
"phy_name":"OSCA001.OSCA_inst/HFCLKOUT"
},
"path_end":
{
"type":"pin",
"log_name":"top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_486/CLK",
"phy_name":"top_reveal_coretop_instance.core0.jtag_int_u.Ihm26k1oo75gFIeIH/CLK"
},
"path_sections":[
{
"type":"net_delay",
"net":
{
"log_name":"top_reveal_coretop_instance/core0/tm_u/secured_instance_1_105/secured_signal_0_141",
"phy_name":"clk150"
},
"arrive":1.808,
"delay":1.808
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":1.808,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- ------------------------ ---------------- ------ --------------------- ------
OSCA001.OSCA_inst/HFCLKOUT OSC_CORE_OSC_CORE_R1C137 CLOCK LATENCY 0.000 0.000 325
top_reveal_coretop_instance/core0/tm_u/secured_instance_1_105/secured_signal_0_141
NET DELAY 1.808 1.808 325
{top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_486/CLK top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_485/CLK}
CLOCK PIN 0.000 1.808 1
Data Path
{
"path_begin":
{
"type":"pin",
"log_name":"top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_485/Q",
"phy_name":"top_reveal_coretop_instance.core0.jtag_int_u.Ihm26k1oo75gFIeIH/Q1"
},
"path_end":
{
"type":"pin",
"log_name":"top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_486/DF",
"phy_name":"top_reveal_coretop_instance.core0.jtag_int_u.Ihm26k1oo75gFIeIH/M0"
},
"path_sections":[
{
"type":"site_delay",
"pin0":
{
"log_name":"top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_485/CLK",
"phy_name":"top_reveal_coretop_instance.core0.jtag_int_u.Ihm26k1oo75gFIeIH/CLK"
},
"pin1":
{
"log_name":"top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_485/Q",
"phy_name":"top_reveal_coretop_instance.core0.jtag_int_u.Ihm26k1oo75gFIeIH/Q1"
},
"arrive":1.987,
"delay":0.179
},
{
"type":"net_delay",
"net":
{
"log_name":"top_reveal_coretop_instance/core0/jtag_int_u/secured_signal_2_160",
"phy_name":"top_reveal_coretop_instance.core0.jtag_int_u.Neo15zDnCIDBEJ3zgix1[2]"
},
"arrive":2.069,
"delay":0.082
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":2.069,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- ------------------------ ---------------- ------ --------------------- ------
top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_485/CLK->top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_485/Q
SLICE_R45C112C REG_DEL 0.179 1.987 2
top_reveal_coretop_instance/core0/jtag_int_u/secured_signal_2_160
NET DELAY 0.082 2.069 2
top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_486/DF
ENDPOINT 0.000 2.069 1
Destination Clock Path
{
"path_begin":
{
"type":"pin",
"log_name":"OSCA001.OSCA_inst/HFCLKOUT",
"phy_name":"OSCA001.OSCA_inst/HFCLKOUT"
},
"path_end":
{
"type":"pin",
"log_name":"top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_486/CLK",
"phy_name":"top_reveal_coretop_instance.core0.jtag_int_u.Ihm26k1oo75gFIeIH/CLK"
},
"path_sections":[
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":0.000,
"delay":0.000
},
{
"type":"net_delay",
"net":
{
"log_name":"top_reveal_coretop_instance/core0/tm_u/secured_instance_1_105/secured_signal_0_141",
"phy_name":"clk150"
},
"arrive":1.921,
"delay":1.921
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":1.921,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- ------------------------ ---------------- ------ --------------------- ------
CONSTRAINT 0.000 0.000 1
OSCA001.OSCA_inst/HFCLKOUT OSC_CORE_OSC_CORE_R1C137 CLOCK LATENCY 0.000 0.000 325
top_reveal_coretop_instance/core0/tm_u/secured_instance_1_105/secured_signal_0_141
NET DELAY 1.921 1.921 325
{top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_486/CLK top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_485/CLK}
CLOCK PIN 0.000 1.921 1
Uncertainty 0.000 1.921
Common Path Skew -0.113 1.808
Hold time 0.094 1.902
---------------------------------------- ------------------------ ---------------- ------ --------------------- ------
Required Time -1.902
Arrival Time 2.069
---------------------------------------- ------------------------ ---------------- ------ --------------------- ------
Path Slack (Passed) 0.167
++++ Path 9 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Path Begin : top_reveal_coretop_instance/core0/trig_u/tu_3/secured_instance_11_136/Q (SLICE_R34C109A)
Path End : top_reveal_coretop_instance/core0/trig_u/tu_3/secured_instance_11_120/DF (SLICE_R34C109D)
Source Clock : clk150 (R)
Destination Clock: clk150 (R)
Logic Level : 1
Delay Ratio : 32.6% (route), 67.4% (logic)
Clock Skew : 0.113 ns
Hold Constraint : 0.000 ns
Common Path Skew : -0.111 ns
Path Slack : 0.168 ns (Passed)
Source Clock Path
{
"path_begin":
{
"type":"pin",
"log_name":"OSCA001.OSCA_inst/HFCLKOUT",
"phy_name":"OSCA001.OSCA_inst/HFCLKOUT"
},
"path_end":
{
"type":"pin",
"log_name":"top_reveal_coretop_instance/core0/trig_u/tu_3/secured_instance_11_136/CLK",
"phy_name":"top_reveal_coretop_instance.core0.trig_u.tu_3.IeJDtew0zBltkd7wB017/CLK"
},
"path_sections":[
{
"type":"net_delay",
"net":
{
"log_name":"top_reveal_coretop_instance/core0/tm_u/secured_instance_1_105/secured_signal_0_141",
"phy_name":"clk150"
},
"arrive":1.808,
"delay":1.808
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":1.808,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- ------------------------ ---------------- ------ --------------------- ------
OSCA001.OSCA_inst/HFCLKOUT OSC_CORE_OSC_CORE_R1C137 CLOCK LATENCY 0.000 0.000 325
top_reveal_coretop_instance/core0/tm_u/secured_instance_1_105/secured_signal_0_141
NET DELAY 1.808 1.808 325
top_reveal_coretop_instance/core0/trig_u/tu_3/secured_instance_11_136/CLK
CLOCK PIN 0.000 1.808 1
Data Path
{
"path_begin":
{
"type":"pin",
"log_name":"top_reveal_coretop_instance/core0/trig_u/tu_3/secured_instance_11_136/Q",
"phy_name":"top_reveal_coretop_instance.core0.trig_u.tu_3.IeJDtew0zBltkd7wB017/Q0"
},
"path_end":
{
"type":"pin",
"log_name":"top_reveal_coretop_instance/core0/trig_u/tu_3/secured_instance_11_120/DF",
"phy_name":"top_reveal_coretop_instance.core0.trig_u.tu_3.Ic4fpnm1ElzI6bcfzK4C4rc/M1"
},
"path_sections":[
{
"type":"site_delay",
"pin0":
{
"log_name":"top_reveal_coretop_instance/core0/trig_u/tu_3/secured_instance_11_136/CLK",
"phy_name":"top_reveal_coretop_instance.core0.trig_u.tu_3.IeJDtew0zBltkd7wB017/CLK"
},
"pin1":
{
"log_name":"top_reveal_coretop_instance/core0/trig_u/tu_3/secured_instance_11_136/Q",
"phy_name":"top_reveal_coretop_instance.core0.trig_u.tu_3.IeJDtew0zBltkd7wB017/Q0"
},
"arrive":1.986,
"delay":0.178
},
{
"type":"net_delay",
"net":
{
"log_name":"top_reveal_coretop_instance/core0/trig_u/tu_3/secured_signal_11_136",
"phy_name":"top_reveal_coretop_instance.core0.trig_u.tu_3.Nc8pHcEsIxIrf"
},
"arrive":2.072,
"delay":0.086
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":2.072,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- ------------------------ ---------------- ------ --------------------- ------
top_reveal_coretop_instance/core0/trig_u/tu_3/secured_instance_11_136/CLK->top_reveal_coretop_instance/core0/trig_u/tu_3/secured_instance_11_136/Q
SLICE_R34C109A REG_DEL 0.178 1.986 5
top_reveal_coretop_instance/core0/trig_u/tu_3/secured_signal_11_136
NET DELAY 0.086 2.072 5
top_reveal_coretop_instance/core0/trig_u/tu_3/secured_instance_11_120/DF
ENDPOINT 0.000 2.072 1
Destination Clock Path
{
"path_begin":
{
"type":"pin",
"log_name":"OSCA001.OSCA_inst/HFCLKOUT",
"phy_name":"OSCA001.OSCA_inst/HFCLKOUT"
},
"path_end":
{
"type":"pin",
"log_name":"top_reveal_coretop_instance/core0/trig_u/tu_3/secured_instance_11_119/CLK",
"phy_name":"top_reveal_coretop_instance.core0.trig_u.tu_3.Ic4fpnm1ElzI6bcfzK4C4rc/CLK"
},
"path_sections":[
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":0.000,
"delay":0.000
},
{
"type":"net_delay",
"net":
{
"log_name":"top_reveal_coretop_instance/core0/tm_u/secured_instance_1_105/secured_signal_0_141",
"phy_name":"clk150"
},
"arrive":1.921,
"delay":1.921
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":1.921,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- ------------------------ ---------------- ------ --------------------- ------
CONSTRAINT 0.000 0.000 1
OSCA001.OSCA_inst/HFCLKOUT OSC_CORE_OSC_CORE_R1C137 CLOCK LATENCY 0.000 0.000 325
top_reveal_coretop_instance/core0/tm_u/secured_instance_1_105/secured_signal_0_141
NET DELAY 1.921 1.921 325
{top_reveal_coretop_instance/core0/trig_u/tu_3/secured_instance_11_119/CLK top_reveal_coretop_instance/core0/trig_u/tu_3/secured_instance_11_120/CLK}
CLOCK PIN 0.000 1.921 1
Uncertainty 0.000 1.921
Common Path Skew -0.111 1.810
Hold time 0.094 1.904
---------------------------------------- ------------------------ ---------------- ------ --------------------- ------
Required Time -1.904
Arrival Time 2.072
---------------------------------------- ------------------------ ---------------- ------ --------------------- ------
Path Slack (Passed) 0.168
++++ Path 10 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Path Begin : top_reveal_coretop_instance/core0/trig_u/tu_4/secured_instance_10_140/Q (SLICE_R36C111C)
Path End : top_reveal_coretop_instance/core0/trig_u/tu_4/secured_instance_10_124/DF (SLICE_R36C111A)
Source Clock : clk150 (R)
Destination Clock: clk150 (R)
Logic Level : 1
Delay Ratio : 32.6% (route), 67.4% (logic)
Clock Skew : 0.113 ns
Hold Constraint : 0.000 ns
Common Path Skew : -0.111 ns
Path Slack : 0.168 ns (Passed)
Source Clock Path
{
"path_begin":
{
"type":"pin",
"log_name":"OSCA001.OSCA_inst/HFCLKOUT",
"phy_name":"OSCA001.OSCA_inst/HFCLKOUT"
},
"path_end":
{
"type":"pin",
"log_name":"top_reveal_coretop_instance/core0/trig_u/tu_4/secured_instance_10_140/CLK",
"phy_name":"top_reveal_coretop_instance.core0.trig_u.tu_4.Ix4LFxrk0hFsajtbF9Bl9/CLK"
},
"path_sections":[
{
"type":"net_delay",
"net":
{
"log_name":"top_reveal_coretop_instance/core0/tm_u/secured_instance_1_105/secured_signal_0_141",
"phy_name":"clk150"
},
"arrive":1.808,
"delay":1.808
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":1.808,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- ------------------------ ---------------- ------ --------------------- ------
OSCA001.OSCA_inst/HFCLKOUT OSC_CORE_OSC_CORE_R1C137 CLOCK LATENCY 0.000 0.000 325
top_reveal_coretop_instance/core0/tm_u/secured_instance_1_105/secured_signal_0_141
NET DELAY 1.808 1.808 325
top_reveal_coretop_instance/core0/trig_u/tu_4/secured_instance_10_140/CLK
CLOCK PIN 0.000 1.808 1
Data Path
{
"path_begin":
{
"type":"pin",
"log_name":"top_reveal_coretop_instance/core0/trig_u/tu_4/secured_instance_10_140/Q",
"phy_name":"top_reveal_coretop_instance.core0.trig_u.tu_4.Ix4LFxrk0hFsajtbF9Bl9/Q0"
},
"path_end":
{
"type":"pin",
"log_name":"top_reveal_coretop_instance/core0/trig_u/tu_4/secured_instance_10_124/DF",
"phy_name":"top_reveal_coretop_instance.core0.trig_u.tu_4.Iqdwih5fnEIfCyvfjH35whIB[8]/M1"
},
"path_sections":[
{
"type":"site_delay",
"pin0":
{
"log_name":"top_reveal_coretop_instance/core0/trig_u/tu_4/secured_instance_10_140/CLK",
"phy_name":"top_reveal_coretop_instance.core0.trig_u.tu_4.Ix4LFxrk0hFsajtbF9Bl9/CLK"
},
"pin1":
{
"log_name":"top_reveal_coretop_instance/core0/trig_u/tu_4/secured_instance_10_140/Q",
"phy_name":"top_reveal_coretop_instance.core0.trig_u.tu_4.Ix4LFxrk0hFsajtbF9Bl9/Q0"
},
"arrive":1.986,
"delay":0.178
},
{
"type":"net_delay",
"net":
{
"log_name":"top_reveal_coretop_instance/core0/trig_u/tu_4/secured_signal_10_140",
"phy_name":"top_reveal_coretop_instance.core0.trig_u.tu_4.Nc8pHcEsIxIrj"
},
"arrive":2.072,
"delay":0.086
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":2.072,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- ------------------------ ---------------- ------ --------------------- ------
top_reveal_coretop_instance/core0/trig_u/tu_4/secured_instance_10_140/CLK->top_reveal_coretop_instance/core0/trig_u/tu_4/secured_instance_10_140/Q
SLICE_R36C111C REG_DEL 0.178 1.986 5
top_reveal_coretop_instance/core0/trig_u/tu_4/secured_signal_10_140
NET DELAY 0.086 2.072 5
top_reveal_coretop_instance/core0/trig_u/tu_4/secured_instance_10_124/DF
ENDPOINT 0.000 2.072 1
Destination Clock Path
{
"path_begin":
{
"type":"pin",
"log_name":"OSCA001.OSCA_inst/HFCLKOUT",
"phy_name":"OSCA001.OSCA_inst/HFCLKOUT"
},
"path_end":
{
"type":"pin",
"log_name":"top_reveal_coretop_instance/core0/trig_u/tu_4/secured_instance_10_123/CLK",
"phy_name":"top_reveal_coretop_instance.core0.trig_u.tu_4.Iqdwih5fnEIfCyvfjH35whIB[8]/CLK"
},
"path_sections":[
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":0.000,
"delay":0.000
},
{
"type":"net_delay",
"net":
{
"log_name":"top_reveal_coretop_instance/core0/tm_u/secured_instance_1_105/secured_signal_0_141",
"phy_name":"clk150"
},
"arrive":1.921,
"delay":1.921
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":1.921,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- ------------------------ ---------------- ------ --------------------- ------
CONSTRAINT 0.000 0.000 1
OSCA001.OSCA_inst/HFCLKOUT OSC_CORE_OSC_CORE_R1C137 CLOCK LATENCY 0.000 0.000 325
top_reveal_coretop_instance/core0/tm_u/secured_instance_1_105/secured_signal_0_141
NET DELAY 1.921 1.921 325
{top_reveal_coretop_instance/core0/trig_u/tu_4/secured_instance_10_123/CLK top_reveal_coretop_instance/core0/trig_u/tu_4/secured_instance_10_124/CLK}
CLOCK PIN 0.000 1.921 1
Uncertainty 0.000 1.921
Common Path Skew -0.111 1.810
Hold time 0.094 1.904
---------------------------------------- ------------------------ ---------------- ------ --------------------- ------
Required Time -1.904
Arrival Time 2.072
---------------------------------------- ------------------------ ---------------- ------ --------------------- ------
Path Slack (Passed) 0.168
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
End of Detailed Report for timing paths
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
##########################################################