Lattice Timing Report - Setup and Hold, Version Radiant Software (64-bit) 2023.1.1.200.1 Wed Nov 29 09:46:34 2023 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2023 Lattice Semiconductor Corporation, All rights reserved. Command line: timing -sethld -v 10 -u 10 -endpoints 10 -nperend 1 -sp 9_High-Performance_1.0V -hsp m -pwrprd -html -rpt LAB04_imp1.twr LAB04_imp1.udb -gui ------------------------------------------- Design: Top Family: LFCPNX Device: LFCPNX-100 Package: LFG672 Performance: 9_High-Performance_1.0V Package Status: Final Version 16 Performance Hardware Data Status : Final Version 3.9 ------------------------------------------- ===================================================================== Table of Contents ===================================================================== 1 DESIGN CHECKING 1.1 SDC Constraints 1.2 Constraint Coverage 1.3 Overall Summary 1.4 Unconstrained Report 1.5 Combinational Loop 2 Setup at Speed Grade 9_High-Performance_1.0V Corner at 85 Degrees 2.1 Clock Summary 2.2 Endpoint slacks 2.3 Detailed Report 3 Hold at Speed Grade m Corner at 0 Degrees 3.1 Endpoint slacks 3.2 Detailed Report ===================================================================== End of Table of Contents ===================================================================== ============================================== 1 DESIGN CHECKING ============================================== 1.1 SDC Constraints ===================== create_clock -name {CLK} -period 6.66667 [get_pins {OSCA001.OSCA_inst/HFCLKOUT }] create_clock -name {rvltck} -period 33.33 -waveform {0.000 16.665} [get_ports TCK] set_clock_groups -group [get_clocks CLK] -group [get_clocks rvltck] -asynchronous 1.2 Constraint Coverage --------------------------- Constraint Coverage: 95.5932% 1.3 Overall Summary --------------------------- Setup at Speed Grade 9_High-Performance_1.0V Corner at 85 Degrees Timing Errors: 0 endpoints; Total Negative Slack: 0.000 ns Hold at Speed Grade m Corner at 0 Degrees Timing Errors: 0 endpoints; Total Negative Slack: 0.000 ns 1.4 Unconstrained Report =========================== 1.4.1 Unconstrained Start/End Points -------------------------------------- Clocked but unconstrained timing start points ------------------------------------------------------------------- Listing 4 Start Points | Type ------------------------------------------------------------------- LED4_0io.PIC_inst/Q | No required time LED3_0io.PIC_inst/Q | No required time LED2_0io.PIC_inst/Q | No required time LED1_0io.PIC_inst/Q | No required time ------------------------------------------------------------------- | Number of unconstrained timing start po | ints | 4 | ------------------------------------------------------------------- Clocked but unconstrained timing end points ------------------------------------------------------------------- Listing 10 End Points | Type ------------------------------------------------------------------- CNT01/Couti[15].ff_inst/LSR | No arrival time {CNT01/Couti[13].ff_inst/LSR CNT01/Couti[14].ff_inst/LSR} | No arrival time {CNT01/Couti[11].ff_inst/LSR CNT01/Couti[12].ff_inst/LSR} | No arrival time {CNT01/Couti[9].ff_inst/LSR CNT01/Couti[10].ff_inst/LSR} | No arrival time {CNT01/Couti[7].ff_inst/LSR CNT01/Couti[8].ff_inst/LSR} | No arrival time {CNT01/Couti[5].ff_inst/LSR CNT01/Couti[6].ff_inst/LSR} | No arrival time {CNT01/Couti[3].ff_inst/LSR CNT01/Couti[4].ff_inst/LSR} | No arrival time {CNT01/Couti[1].ff_inst/LSR CNT01/Couti[2].ff_inst/LSR} | No arrival time CNT01/Couti[0].ff_inst/LSR | No arrival time CNT02/Couti[15].ff_inst/LSR | No arrival time ------------------------------------------------------------------- | Number of unconstrained timing end poin | ts | 43 | ------------------------------------------------------------------- 1.4.2 Start/End Points Without Timing Constraints --------------------------------------------------- I/O ports without constraint ---------------------------- Possible constraints to use on I/O ports are: set_input_delay, set_output_delay, set_max_delay, create_clock, create_generated_clock, ... ------------------------------------------------------------------- Listing 5 Start or End Points | Type ------------------------------------------------------------------- RST_N | input LED4 | output LED3 | output LED2 | output LED1 | output ------------------------------------------------------------------- | Number of I/O ports without constraint | 5 | ------------------------------------------------------------------- Nets without clock definition Define a clock on a top level port or a generated clock on a clock divider pin associated with this net(s). -------------------------------------------------- There is no instance satisfying reporting criteria 1.5 Combinational Loop ======================== None =============================================================== 2 Setup at Speed Grade 9_High-Performance_1.0V Corner at 85 Degrees =============================================================== 2.1 Clock Summary ======================= 2.1.1 Clock "CLK" ======================= create_clock -name {CLK} -period 6.66667 [get_pins {OSCA001.OSCA_inst/HFCLKOUT }] Single Clock Domain ------------------------------------------------------------------------------------------------------- Clock CLK | | Period | Frequency ------------------------------------------------------------------------------------------------------- From CLK | Target | 6.667 ns | 150.000 MHz | Actual (all paths) | 5.750 ns | 173.913 MHz OSCA001.OSCA_inst/HFCLKOUT (MPW) | (50% duty cycle) | 4.354 ns | 229.674 MHz ------------------------------------------------------------------------------------------------------- Clock Domain Crossing ------------------------------------------------------------------------------------------------------ Clock CLK | Worst Time Between Edges | Comment ------------------------------------------------------------------------------------------------------ From rvltck | ---- | False path ------------------------------------------------------------------------------------------------------ 2.1.2 Clock "rvltck" ======================= create_clock -name {rvltck} -period 33.33 -waveform {0.000 16.665} [get_ports TCK] Single Clock Domain ------------------------------------------------------------------------------------------------------- Clock rvltck | | Period | Frequency ------------------------------------------------------------------------------------------------------- From rvltck | Target | 33.330 ns | 30.003 MHz | Actual (all paths) | 12.678 ns | 78.877 MHz jtaghub_inst/IB_inst2.bb_inst/B (MPW) | (50% duty cycle) | 5.000 ns | 200.000 MHz ------------------------------------------------------------------------------------------------------- Clock Domain Crossing ------------------------------------------------------------------------------------------------------ Clock rvltck | Worst Time Between Edges | Comment ------------------------------------------------------------------------------------------------------ From CLK | ---- | False path ------------------------------------------------------------------------------------------------------ 2.2 Endpoint slacks ======================= ------------------------------------------------------- Listing 10 End Points | Slack ------------------------------------------------------- LED3_0io.PIC_inst/D | 0.917 ns LED1_0io.PIC_inst/D | 0.935 ns top_reveal_coretop_instance/core0/trig_u/tu_3/secured_instance_9_94/DF | 1.887 ns top_reveal_coretop_instance/core0/trig_u/te_1/secured_instance_5_264/CE | 2.154 ns {top_reveal_coretop_instance/core0/trig_u/te_1/secured_instance_5_258/CE top_reveal_coretop_instance/core0/trig_u/te_1/secured_instance_5_263/CE} | 2.154 ns top_reveal_coretop_instance/core0/trig_u/te_1/secured_instance_5_252/CE | 2.201 ns {top_reveal_coretop_instance/core0/trig_u/te_1/secured_instance_5_246/CE top_reveal_coretop_instance/core0/trig_u/te_1/secured_instance_5_247/CE} | 2.201 ns {top_reveal_coretop_instance/core0/trig_u/te_0/secured_instance_7_103/CE top_reveal_coretop_instance/core0/trig_u/te_0/secured_instance_7_105/CE} | 2.274 ns {top_reveal_coretop_instance/core0/trig_u/te_0/secured_instance_7_98/CE top_reveal_coretop_instance/core0/trig_u/te_0/secured_instance_7_101/CE} | 2.274 ns {top_reveal_coretop_instance/core0/trig_u/te_0/secured_instance_7_83/CE top_reveal_coretop_instance/core0/trig_u/te_0/secured_instance_7_85/CE} | 2.274 ns ------------------------------------------------------- | Setup # of endpoints with negative slack:| 0 | ------------------------------------------------------- 2.3 Detailed Report ======================= XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX Detail report of critical paths XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Detailed Report for timing paths +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ ++++Path 1 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Path Begin : CNT03/Couti[13].ff_inst/Q (SLICE_R60C10D) Path End : LED3_0io.PIC_inst/D (SIOLOGIC_CORE_IOL_R31A) Source Clock : CLK (R) Destination Clock: CLK (R) Logic Level : 2 Delay Ratio : 90.7% (route), 9.3% (logic) Clock Skew : 0.084 ns Setup Constraint : 6.666 ns Path Slack : 0.916 ns (Passed) Source Clock Path Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- ------------------------ ------------- -------- --------------------- ------ OSCA001.OSCA_inst/HFCLKOUT OSC_CORE_OSC_CORE_R1C137 CLOCK LATENCY 0.000 0.000 353 top_reveal_coretop_instance/core0/tm_u/secured_instance_1_108/secured_signal_0_140 NET DELAY 0.361 0.361 353 CE001/DCC01/CLKI->CE001/DCC01/CLKO DCC_DCC_R1 DCC_DEL 0.000 0.361 40 CE001/CLK1 NET DELAY 2.066 2.427 40 {CNT03/Couti[13].ff_inst/CLK CNT03/Couti[14].ff_inst/CLK} 0.000 2.427 1 Data Path Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- ------------------------ ------------- -------- --------------------- ------ CNT03/Couti[13].ff_inst/CLK->CNT03/Couti[13].ff_inst/Q SLICE_R60C10D REG_DEL 0.304 2.731 4 top_reveal_coretop_instance/core0/tm_u/secured_signal_1_60 NET DELAY 3.298 6.029 4 LED3_1_cZ/B->LED3_1_cZ/Z SLICE_R41C117D CTOF_DEL 0.213 6.242 1 LED3_1 NET DELAY 1.725 7.967 1 LED3_0io.PIC_inst/D 0.000 7.967 1 Destination Clock Path Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- ------------------------ ------------- -------- --------------------- ------ CONSTRAINT 0.000 6.666 1 OSCA001.OSCA_inst/HFCLKOUT OSC_CORE_OSC_CORE_R1C137 CLOCK LATENCY 0.000 6.666 353 top_reveal_coretop_instance/core0/tm_u/secured_instance_1_108/secured_signal_0_140 NET DELAY 0.361 7.027 353 CE001/DCC01/CLKI->CE001/DCC01/CLKO DCC_DCC_R1 DCC_DEL 0.000 7.027 40 CE001/CLK1 NET DELAY 2.150 9.177 40 LED3_0io.PIC_inst/CLK 0.000 9.177 1 Uncertainty -(0.000) 9.177 Setup time -(0.294) 8.883 ---------------------------------------- ------------------------ ------------- -------- --------------------- ------ Required Time 8.883 Arrival Time -(7.966) ---------------------------------------- ------------------------ ------------- -------- --------------------- ------ Path Slack (Passed) 0.916 ++++ Path 2 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Path Begin : CNT01/Couti[0].ff_inst/Q (SLICE_R14C12A) Path End : LED1_0io.PIC_inst/D (SIOLOGIC_CORE_IOL_R28B) Source Clock : CLK (R) Destination Clock: CLK (R) Logic Level : 2 Delay Ratio : 90.6% (route), 9.4% (logic) Clock Skew : 0.084 ns Setup Constraint : 6.666 ns Path Slack : 0.934 ns (Passed) Source Clock Path Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- ------------------------ ------------- -------- --------------------- ------ OSCA001.OSCA_inst/HFCLKOUT OSC_CORE_OSC_CORE_R1C137 CLOCK LATENCY 0.000 0.000 353 top_reveal_coretop_instance/core0/tm_u/secured_instance_1_108/secured_signal_0_140 NET DELAY 0.361 0.361 353 CE001/DCC01/CLKI->CE001/DCC01/CLKO DCC_DCC_R1 DCC_DEL 0.000 0.361 40 CE001/CLK1 NET DELAY 2.066 2.427 40 CNT01/Couti[0].ff_inst/CLK 0.000 2.427 1 Data Path Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- ------------------------ ------------- -------- --------------------- ------ CNT01/Couti[0].ff_inst/CLK->CNT01/Couti[0].ff_inst/Q SLICE_R14C12A REG_DEL 0.307 2.734 4 top_reveal_coretop_instance/core0/tm_u/secured_signal_1_41 NET DELAY 3.340 6.074 4 LED1_1_cZ/A->LED1_1_cZ/Z SLICE_R38C117D CTOF_DEL 0.213 6.287 1 LED1_1 NET DELAY 1.662 7.949 1 LED1_0io.PIC_inst/D 0.000 7.949 1 Destination Clock Path Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- ------------------------ ------------- -------- --------------------- ------ CONSTRAINT 0.000 6.666 1 OSCA001.OSCA_inst/HFCLKOUT OSC_CORE_OSC_CORE_R1C137 CLOCK LATENCY 0.000 6.666 353 top_reveal_coretop_instance/core0/tm_u/secured_instance_1_108/secured_signal_0_140 NET DELAY 0.361 7.027 353 CE001/DCC01/CLKI->CE001/DCC01/CLKO DCC_DCC_R1 DCC_DEL 0.000 7.027 40 CE001/CLK1 NET DELAY 2.150 9.177 40 LED1_0io.PIC_inst/CLK 0.000 9.177 1 Uncertainty -(0.000) 9.177 Setup time -(0.294) 8.883 ---------------------------------------- ------------------------ ------------- -------- --------------------- ------ Required Time 8.883 Arrival Time -(7.948) ---------------------------------------- ------------------------ ------------- -------- --------------------- ------ Path Slack (Passed) 0.934 ++++ Path 3 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Path Begin : top_reveal_coretop_instance/core0/trig_u/tu_3/secured_instance_9_133/Q (SLICE_R56C112C) Path End : top_reveal_coretop_instance/core0/trig_u/tu_3/secured_instance_9_94/DF (SLICE_R52C110D) Source Clock : CLK (R) Destination Clock: CLK (R) Logic Level : 10 Delay Ratio : 55.8% (route), 44.2% (logic) Clock Skew : 0.000 ns Setup Constraint : 6.666 ns Path Slack : 1.886 ns (Passed) Source Clock Path Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- ------------------------ ------------- --------- --------------------- ------ OSCA001.OSCA_inst/HFCLKOUT OSC_CORE_OSC_CORE_R1C137 CLOCK LATENCY 0.000 0.000 353 top_reveal_coretop_instance/core0/tm_u/secured_instance_1_108/secured_signal_0_140 NET DELAY 2.427 2.427 353 top_reveal_coretop_instance/core0/trig_u/tu_3/secured_instance_9_133/CLK 0.000 2.427 1 Data Path Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- ------------------------ ------------- --------- --------------------- ------ top_reveal_coretop_instance/core0/trig_u/tu_3/secured_instance_9_133/CLK->top_reveal_coretop_instance/core0/trig_u/tu_3/secured_instance_9_133/Q SLICE_R56C112C REG_DEL 0.304 2.731 5 top_reveal_coretop_instance/core0/trig_u/tu_3/secured_signal_9_133 NET DELAY 0.826 3.557 5 top_reveal_coretop_instance/core0/trig_u/tu_3/secured_instance_9_70/C->top_reveal_coretop_instance/core0/trig_u/tu_3/secured_instance_9_70/Z SLICE_R54C111D CTOF_DEL 0.213 3.770 1 top_reveal_coretop_instance/core0/trig_u/tu_3/secured_signal_9_196 NET DELAY 0.247 4.017 1 top_reveal_coretop_instance/core0/trig_u/tu_3/secured_instance_9_71/D->top_reveal_coretop_instance/core0/trig_u/tu_3/secured_instance_9_71/Z SLICE_R54C111D CTOF_DEL 0.213 4.230 1 top_reveal_coretop_instance/core0/trig_u/tu_3/secured_signal_9_159 NET DELAY 0.463 4.693 1 top_reveal_coretop_instance/core0/trig_u/tu_3/secured_instance_9_77/A0->top_reveal_coretop_instance/core0/trig_u/tu_3/secured_instance_9_77/COUT SLICE_R57C110B C0TOFCO_DEL 0.316 5.009 1 top_reveal_coretop_instance/core0/trig_u/tu_3/secured_signal_9_110 NET DELAY 0.000 5.009 1 top_reveal_coretop_instance/core0/trig_u/tu_3/secured_instance_9_76/CIN->top_reveal_coretop_instance/core0/trig_u/tu_3/secured_instance_9_76/COUT SLICE_R57C110C FCITOFCO_DEL 0.054 5.063 1 top_reveal_coretop_instance/core0/trig_u/tu_3/secured_signal_9_109 NET DELAY 0.000 5.063 1 top_reveal_coretop_instance/core0/trig_u/tu_3/secured_instance_9_75/CIN->top_reveal_coretop_instance/core0/trig_u/tu_3/secured_instance_9_75/COUT SLICE_R57C110D FCITOFCO_DEL 0.054 5.117 1 top_reveal_coretop_instance/core0/trig_u/tu_3/secured_signal_9_108 NET DELAY 0.000 5.117 1 top_reveal_coretop_instance/core0/trig_u/tu_3/secured_instance_9_74/CIN->top_reveal_coretop_instance/core0/trig_u/tu_3/secured_instance_9_74/S1 SLICE_R57C111A FCITOF1_DEL 0.280 5.397 3 top_reveal_coretop_instance/core0/trig_u/tu_3/secured_signal_9_129 NET DELAY 0.532 5.929 3 top_reveal_coretop_instance/core0/trig_u/tu_3/secured_instance_9_51/B->top_reveal_coretop_instance/core0/trig_u/tu_3/secured_instance_9_51/Z SLICE_R53C111C CTOF_DEL 0.213 6.142 1 top_reveal_coretop_instance/core0/trig_u/tu_3/secured_signal_9_162 NET DELAY 0.246 6.388 1 top_reveal_coretop_instance/core0/trig_u/tu_3/secured_instance_9_89/D->top_reveal_coretop_instance/core0/trig_u/tu_3/secured_instance_9_89/Z SLICE_R53C111B CTOOF_DEL 0.277 6.665 1 top_reveal_coretop_instance/core0/trig_u/tu_3/secured_signal_9_164 NET DELAY 0.387 7.052 1 top_reveal_coretop_instance/core0/trig_u/tu_3/secured_instance_9_57/B->top_reveal_coretop_instance/core0/trig_u/tu_3/secured_instance_9_57/Z SLICE_R52C110D CTOF_DEL 0.213 7.265 1 top_reveal_coretop_instance/core0/trig_u/tu_3/secured_signal_9_149 NET DELAY 0.000 7.265 1 top_reveal_coretop_instance/core0/trig_u/tu_3/secured_instance_9_94/DF 0.000 7.265 1 Destination Clock Path Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- ------------------------ ------------- --------- --------------------- ------ CONSTRAINT 0.000 6.666 1 OSCA001.OSCA_inst/HFCLKOUT OSC_CORE_OSC_CORE_R1C137 CLOCK LATENCY 0.000 6.666 353 top_reveal_coretop_instance/core0/tm_u/secured_instance_1_108/secured_signal_0_140 NET DELAY 2.427 9.093 353 {top_reveal_coretop_instance/core0/trig_u/tu_3/secured_instance_9_94/CLK top_reveal_coretop_instance/core0/trig_u/tu_2/secured_instance_10_94/CLK} 0.000 9.093 1 Uncertainty -(0.000) 9.093 Setup time -(-0.058) 9.151 ---------------------------------------- ------------------------ ------------- --------- --------------------- ------ Required Time 9.151 Arrival Time -(7.264) ---------------------------------------- ------------------------ ------------- --------- --------------------- ------ Path Slack (Passed) 1.886 ++++ Path 4 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Path Begin : top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_479/Q (SLICE_R44C120B) Path End : top_reveal_coretop_instance/core0/trig_u/te_1/secured_instance_5_264/CE (SLICE_R53C125B) Source Clock : CLK (R) Destination Clock: CLK (R) Logic Level : 8 Delay Ratio : 58.4% (route), 41.6% (logic) Clock Skew : 0.000 ns Setup Constraint : 6.666 ns Path Slack : 2.153 ns (Passed) Source Clock Path Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- ------------------------ ------------- -------- --------------------- ------ OSCA001.OSCA_inst/HFCLKOUT OSC_CORE_OSC_CORE_R1C137 CLOCK LATENCY 0.000 0.000 353 top_reveal_coretop_instance/core0/tm_u/secured_instance_1_108/secured_signal_0_140 NET DELAY 2.427 2.427 353 {top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_478/CLK top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_479/CLK} 0.000 2.427 1 Data Path Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- ------------------------ ------------- -------- --------------------- ------ top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_479/CLK->top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_479/Q SLICE_R44C120B REG_DEL 0.307 2.734 4 top_reveal_coretop_instance/core0/jtag_int_u/secured_signal_2_161 NET DELAY 0.203 2.937 4 top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_240/B->top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_240/Z SLICE_R44C120B CTOF_DEL 0.213 3.150 1 top_reveal_coretop_instance/core0/jtag_int_u/secured_signal_2_586 NET DELAY 0.160 3.310 1 top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_218/D->top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_218/Z SLICE_R44C120D CTOF_DEL 0.213 3.523 7 top_reveal_coretop_instance/core0/tm_u/secured_signal_1_158 NET DELAY 0.160 3.683 7 top_reveal_coretop_instance/core0/trig_u/decode_u/secured_instance_13_13/C->top_reveal_coretop_instance/core0/trig_u/decode_u/secured_instance_13_13/Z SLICE_R44C120A CTOF_DEL 0.213 3.896 3 top_reveal_coretop_instance/core0/trig_u/decode_u/secured_signal_13_26 NET DELAY 0.410 4.306 3 top_reveal_coretop_instance/core0/trig_u/decode_u/secured_instance_13_2/A->top_reveal_coretop_instance/core0/trig_u/decode_u/secured_instance_13_2/Z SLICE_R44C116C CTOF_DEL 0.213 4.519 4 top_reveal_coretop_instance/core0/trig_u/decode_u/secured_signal_13_28 NET DELAY 0.549 5.068 4 top_reveal_coretop_instance/core0/trig_u/decode_u/secured_instance_13_0/B->top_reveal_coretop_instance/core0/trig_u/decode_u/secured_instance_13_0/Z SLICE_R48C122B CTOF_DEL 0.213 5.281 9 top_reveal_coretop_instance/core0/trig_u/te_1/secured_signal_5_37 NET DELAY 0.159 5.440 9 top_reveal_coretop_instance/core0/trig_u/te_1/secured_instance_5_97/B->top_reveal_coretop_instance/core0/trig_u/te_1/secured_instance_5_97/Z SLICE_R48C122A CTOF_DEL 0.213 5.653 4 top_reveal_coretop_instance/core0/trig_u/te_1/secured_signal_5_225 NET DELAY 0.577 6.230 4 top_reveal_coretop_instance/core0/trig_u/te_1/secured_instance_5_83/A->top_reveal_coretop_instance/core0/trig_u/te_1/secured_instance_5_83/Z SLICE_R53C123B CTOF_DEL 0.213 6.443 2 top_reveal_coretop_instance/core0/trig_u/te_1/secured_signal_5_199 NET DELAY 0.304 6.747 2 top_reveal_coretop_instance/core0/trig_u/te_1/secured_instance_5_264/CE 0.000 6.747 1 Destination Clock Path Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- ------------------------ ------------- -------- --------------------- ------ CONSTRAINT 0.000 6.666 1 OSCA001.OSCA_inst/HFCLKOUT OSC_CORE_OSC_CORE_R1C137 CLOCK LATENCY 0.000 6.666 353 top_reveal_coretop_instance/core0/tm_u/secured_instance_1_108/secured_signal_0_140 NET DELAY 2.427 9.093 353 top_reveal_coretop_instance/core0/trig_u/te_1/secured_instance_5_264/CLK 0.000 9.093 1 Uncertainty -(0.000) 9.093 Setup time -(0.193) 8.900 ---------------------------------------- ------------------------ ------------- -------- --------------------- ------ Required Time 8.900 Arrival Time -(6.746) ---------------------------------------- ------------------------ ------------- -------- --------------------- ------ Path Slack (Passed) 2.153 ++++ Path 5 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Path Begin : top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_479/Q (SLICE_R44C120B) Path End : {top_reveal_coretop_instance/core0/trig_u/te_1/secured_instance_5_258/CE top_reveal_coretop_instance/core0/trig_u/te_1/secured_instance_5_263/CE} (SLICE_R53C124B) Source Clock : CLK (R) Destination Clock: CLK (R) Logic Level : 8 Delay Ratio : 58.4% (route), 41.6% (logic) Clock Skew : 0.000 ns Setup Constraint : 6.666 ns Path Slack : 2.153 ns (Passed) Source Clock Path Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- ------------------------ ------------- -------- --------------------- ------ OSCA001.OSCA_inst/HFCLKOUT OSC_CORE_OSC_CORE_R1C137 CLOCK LATENCY 0.000 0.000 353 top_reveal_coretop_instance/core0/tm_u/secured_instance_1_108/secured_signal_0_140 NET DELAY 2.427 2.427 353 {top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_478/CLK top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_479/CLK} 0.000 2.427 1 Data Path Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- ------------------------ ------------- -------- --------------------- ------ top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_479/CLK->top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_479/Q SLICE_R44C120B REG_DEL 0.307 2.734 4 top_reveal_coretop_instance/core0/jtag_int_u/secured_signal_2_161 NET DELAY 0.203 2.937 4 top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_240/B->top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_240/Z SLICE_R44C120B CTOF_DEL 0.213 3.150 1 top_reveal_coretop_instance/core0/jtag_int_u/secured_signal_2_586 NET DELAY 0.160 3.310 1 top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_218/D->top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_218/Z SLICE_R44C120D CTOF_DEL 0.213 3.523 7 top_reveal_coretop_instance/core0/tm_u/secured_signal_1_158 NET DELAY 0.160 3.683 7 top_reveal_coretop_instance/core0/trig_u/decode_u/secured_instance_13_13/C->top_reveal_coretop_instance/core0/trig_u/decode_u/secured_instance_13_13/Z SLICE_R44C120A CTOF_DEL 0.213 3.896 3 top_reveal_coretop_instance/core0/trig_u/decode_u/secured_signal_13_26 NET DELAY 0.410 4.306 3 top_reveal_coretop_instance/core0/trig_u/decode_u/secured_instance_13_2/A->top_reveal_coretop_instance/core0/trig_u/decode_u/secured_instance_13_2/Z SLICE_R44C116C CTOF_DEL 0.213 4.519 4 top_reveal_coretop_instance/core0/trig_u/decode_u/secured_signal_13_28 NET DELAY 0.549 5.068 4 top_reveal_coretop_instance/core0/trig_u/decode_u/secured_instance_13_0/B->top_reveal_coretop_instance/core0/trig_u/decode_u/secured_instance_13_0/Z SLICE_R48C122B CTOF_DEL 0.213 5.281 9 top_reveal_coretop_instance/core0/trig_u/te_1/secured_signal_5_37 NET DELAY 0.159 5.440 9 top_reveal_coretop_instance/core0/trig_u/te_1/secured_instance_5_97/B->top_reveal_coretop_instance/core0/trig_u/te_1/secured_instance_5_97/Z SLICE_R48C122A CTOF_DEL 0.213 5.653 4 top_reveal_coretop_instance/core0/trig_u/te_1/secured_signal_5_225 NET DELAY 0.577 6.230 4 top_reveal_coretop_instance/core0/trig_u/te_1/secured_instance_5_83/A->top_reveal_coretop_instance/core0/trig_u/te_1/secured_instance_5_83/Z SLICE_R53C123B CTOF_DEL 0.213 6.443 2 top_reveal_coretop_instance/core0/trig_u/te_1/secured_signal_5_199 NET DELAY 0.304 6.747 2 {top_reveal_coretop_instance/core0/trig_u/te_1/secured_instance_5_258/CE top_reveal_coretop_instance/core0/trig_u/te_1/secured_instance_5_263/CE} 0.000 6.747 1 Destination Clock Path Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- ------------------------ ------------- -------- --------------------- ------ CONSTRAINT 0.000 6.666 1 OSCA001.OSCA_inst/HFCLKOUT OSC_CORE_OSC_CORE_R1C137 CLOCK LATENCY 0.000 6.666 353 top_reveal_coretop_instance/core0/tm_u/secured_instance_1_108/secured_signal_0_140 NET DELAY 2.427 9.093 353 {top_reveal_coretop_instance/core0/trig_u/te_1/secured_instance_5_258/CLK top_reveal_coretop_instance/core0/trig_u/te_1/secured_instance_5_263/CLK} 0.000 9.093 1 Uncertainty -(0.000) 9.093 Setup time -(0.193) 8.900 ---------------------------------------- ------------------------ ------------- -------- --------------------- ------ Required Time 8.900 Arrival Time -(6.746) ---------------------------------------- ------------------------ ------------- -------- --------------------- ------ Path Slack (Passed) 2.153 ++++ Path 6 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Path Begin : top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_479/Q (SLICE_R44C120B) Path End : top_reveal_coretop_instance/core0/trig_u/te_1/secured_instance_5_252/CE (SLICE_R56C122C) Source Clock : CLK (R) Destination Clock: CLK (R) Logic Level : 7 Delay Ratio : 62.9% (route), 37.1% (logic) Clock Skew : 0.000 ns Setup Constraint : 6.666 ns Path Slack : 2.200 ns (Passed) Source Clock Path Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- ------------------------ ------------- -------- --------------------- ------ OSCA001.OSCA_inst/HFCLKOUT OSC_CORE_OSC_CORE_R1C137 CLOCK LATENCY 0.000 0.000 353 top_reveal_coretop_instance/core0/tm_u/secured_instance_1_108/secured_signal_0_140 NET DELAY 2.427 2.427 353 {top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_478/CLK top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_479/CLK} 0.000 2.427 1 Data Path Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- ------------------------ ------------- -------- --------------------- ------ top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_479/CLK->top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_479/Q SLICE_R44C120B REG_DEL 0.307 2.734 4 top_reveal_coretop_instance/core0/jtag_int_u/secured_signal_2_161 NET DELAY 0.203 2.937 4 top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_240/B->top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_240/Z SLICE_R44C120B CTOF_DEL 0.213 3.150 1 top_reveal_coretop_instance/core0/jtag_int_u/secured_signal_2_586 NET DELAY 0.160 3.310 1 top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_218/D->top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_218/Z SLICE_R44C120D CTOF_DEL 0.213 3.523 7 top_reveal_coretop_instance/core0/tm_u/secured_signal_1_158 NET DELAY 0.160 3.683 7 top_reveal_coretop_instance/core0/trig_u/decode_u/secured_instance_13_13/C->top_reveal_coretop_instance/core0/trig_u/decode_u/secured_instance_13_13/Z SLICE_R44C120A CTOF_DEL 0.213 3.896 3 top_reveal_coretop_instance/core0/trig_u/decode_u/secured_signal_13_26 NET DELAY 0.410 4.306 3 top_reveal_coretop_instance/core0/trig_u/decode_u/secured_instance_13_2/A->top_reveal_coretop_instance/core0/trig_u/decode_u/secured_instance_13_2/Z SLICE_R44C116C CTOF_DEL 0.213 4.519 4 top_reveal_coretop_instance/core0/trig_u/decode_u/secured_signal_13_28 NET DELAY 0.549 5.068 4 top_reveal_coretop_instance/core0/trig_u/decode_u/secured_instance_13_0/B->top_reveal_coretop_instance/core0/trig_u/decode_u/secured_instance_13_0/Z SLICE_R48C122B CTOF_DEL 0.213 5.281 9 top_reveal_coretop_instance/core0/trig_u/te_1/secured_signal_5_37 NET DELAY 0.614 5.895 9 top_reveal_coretop_instance/core0/trig_u/te_1/secured_instance_5_111/C->top_reveal_coretop_instance/core0/trig_u/te_1/secured_instance_5_111/Z SLICE_R48C120D CTOF_DEL 0.213 6.108 2 top_reveal_coretop_instance/core0/trig_u/te_1/secured_signal_5_215 NET DELAY 0.592 6.700 2 top_reveal_coretop_instance/core0/trig_u/te_1/secured_instance_5_252/CE 0.000 6.700 1 Destination Clock Path Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- ------------------------ ------------- -------- --------------------- ------ CONSTRAINT 0.000 6.666 1 OSCA001.OSCA_inst/HFCLKOUT OSC_CORE_OSC_CORE_R1C137 CLOCK LATENCY 0.000 6.666 353 top_reveal_coretop_instance/core0/tm_u/secured_instance_1_108/secured_signal_0_140 NET DELAY 2.427 9.093 353 top_reveal_coretop_instance/core0/trig_u/te_1/secured_instance_5_252/CLK 0.000 9.093 1 Uncertainty -(0.000) 9.093 Setup time -(0.193) 8.900 ---------------------------------------- ------------------------ ------------- -------- --------------------- ------ Required Time 8.900 Arrival Time -(6.699) ---------------------------------------- ------------------------ ------------- -------- --------------------- ------ Path Slack (Passed) 2.200 ++++ Path 7 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Path Begin : top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_479/Q (SLICE_R44C120B) Path End : {top_reveal_coretop_instance/core0/trig_u/te_1/secured_instance_5_246/CE top_reveal_coretop_instance/core0/trig_u/te_1/secured_instance_5_247/CE} (SLICE_R56C122D) Source Clock : CLK (R) Destination Clock: CLK (R) Logic Level : 7 Delay Ratio : 62.9% (route), 37.1% (logic) Clock Skew : 0.000 ns Setup Constraint : 6.666 ns Path Slack : 2.200 ns (Passed) Source Clock Path Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- ------------------------ ------------- -------- --------------------- ------ OSCA001.OSCA_inst/HFCLKOUT OSC_CORE_OSC_CORE_R1C137 CLOCK LATENCY 0.000 0.000 353 top_reveal_coretop_instance/core0/tm_u/secured_instance_1_108/secured_signal_0_140 NET DELAY 2.427 2.427 353 {top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_478/CLK top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_479/CLK} 0.000 2.427 1 Data Path Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- ------------------------ ------------- -------- --------------------- ------ top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_479/CLK->top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_479/Q SLICE_R44C120B REG_DEL 0.307 2.734 4 top_reveal_coretop_instance/core0/jtag_int_u/secured_signal_2_161 NET DELAY 0.203 2.937 4 top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_240/B->top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_240/Z SLICE_R44C120B CTOF_DEL 0.213 3.150 1 top_reveal_coretop_instance/core0/jtag_int_u/secured_signal_2_586 NET DELAY 0.160 3.310 1 top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_218/D->top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_218/Z SLICE_R44C120D CTOF_DEL 0.213 3.523 7 top_reveal_coretop_instance/core0/tm_u/secured_signal_1_158 NET DELAY 0.160 3.683 7 top_reveal_coretop_instance/core0/trig_u/decode_u/secured_instance_13_13/C->top_reveal_coretop_instance/core0/trig_u/decode_u/secured_instance_13_13/Z SLICE_R44C120A CTOF_DEL 0.213 3.896 3 top_reveal_coretop_instance/core0/trig_u/decode_u/secured_signal_13_26 NET DELAY 0.410 4.306 3 top_reveal_coretop_instance/core0/trig_u/decode_u/secured_instance_13_2/A->top_reveal_coretop_instance/core0/trig_u/decode_u/secured_instance_13_2/Z SLICE_R44C116C CTOF_DEL 0.213 4.519 4 top_reveal_coretop_instance/core0/trig_u/decode_u/secured_signal_13_28 NET DELAY 0.549 5.068 4 top_reveal_coretop_instance/core0/trig_u/decode_u/secured_instance_13_0/B->top_reveal_coretop_instance/core0/trig_u/decode_u/secured_instance_13_0/Z SLICE_R48C122B CTOF_DEL 0.213 5.281 9 top_reveal_coretop_instance/core0/trig_u/te_1/secured_signal_5_37 NET DELAY 0.614 5.895 9 top_reveal_coretop_instance/core0/trig_u/te_1/secured_instance_5_111/C->top_reveal_coretop_instance/core0/trig_u/te_1/secured_instance_5_111/Z SLICE_R48C120D CTOF_DEL 0.213 6.108 2 top_reveal_coretop_instance/core0/trig_u/te_1/secured_signal_5_215 NET DELAY 0.592 6.700 2 {top_reveal_coretop_instance/core0/trig_u/te_1/secured_instance_5_246/CE top_reveal_coretop_instance/core0/trig_u/te_1/secured_instance_5_247/CE} 0.000 6.700 1 Destination Clock Path Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- ------------------------ ------------- -------- --------------------- ------ CONSTRAINT 0.000 6.666 1 OSCA001.OSCA_inst/HFCLKOUT OSC_CORE_OSC_CORE_R1C137 CLOCK LATENCY 0.000 6.666 353 top_reveal_coretop_instance/core0/tm_u/secured_instance_1_108/secured_signal_0_140 NET DELAY 2.427 9.093 353 {top_reveal_coretop_instance/core0/trig_u/te_1/secured_instance_5_246/CLK top_reveal_coretop_instance/core0/trig_u/te_1/secured_instance_5_247/CLK} 0.000 9.093 1 Uncertainty -(0.000) 9.093 Setup time -(0.193) 8.900 ---------------------------------------- ------------------------ ------------- -------- --------------------- ------ Required Time 8.900 Arrival Time -(6.699) ---------------------------------------- ------------------------ ------------- -------- --------------------- ------ Path Slack (Passed) 2.200 ++++ Path 8 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Path Begin : top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_479/Q (SLICE_R44C120B) Path End : {top_reveal_coretop_instance/core0/trig_u/te_0/secured_instance_7_103/CE top_reveal_coretop_instance/core0/trig_u/te_0/secured_instance_7_105/CE} (SLICE_R53C119C) Source Clock : CLK (R) Destination Clock: CLK (R) Logic Level : 7 Delay Ratio : 62.3% (route), 37.7% (logic) Clock Skew : 0.000 ns Setup Constraint : 6.666 ns Path Slack : 2.273 ns (Passed) Source Clock Path Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- ------------------------ ------------- -------- --------------------- ------ OSCA001.OSCA_inst/HFCLKOUT OSC_CORE_OSC_CORE_R1C137 CLOCK LATENCY 0.000 0.000 353 top_reveal_coretop_instance/core0/tm_u/secured_instance_1_108/secured_signal_0_140 NET DELAY 2.427 2.427 353 {top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_478/CLK top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_479/CLK} 0.000 2.427 1 Data Path Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- ------------------------ ------------- -------- --------------------- ------ top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_479/CLK->top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_479/Q SLICE_R44C120B REG_DEL 0.307 2.734 4 top_reveal_coretop_instance/core0/jtag_int_u/secured_signal_2_161 NET DELAY 0.203 2.937 4 top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_240/B->top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_240/Z SLICE_R44C120B CTOF_DEL 0.213 3.150 1 top_reveal_coretop_instance/core0/jtag_int_u/secured_signal_2_586 NET DELAY 0.160 3.310 1 top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_218/D->top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_218/Z SLICE_R44C120D CTOF_DEL 0.213 3.523 7 top_reveal_coretop_instance/core0/tm_u/secured_signal_1_158 NET DELAY 0.160 3.683 7 top_reveal_coretop_instance/core0/trig_u/decode_u/secured_instance_13_13/C->top_reveal_coretop_instance/core0/trig_u/decode_u/secured_instance_13_13/Z SLICE_R44C120A CTOF_DEL 0.213 3.896 3 top_reveal_coretop_instance/core0/trig_u/decode_u/secured_signal_13_26 NET DELAY 0.410 4.306 3 top_reveal_coretop_instance/core0/trig_u/decode_u/secured_instance_13_2/A->top_reveal_coretop_instance/core0/trig_u/decode_u/secured_instance_13_2/Z SLICE_R44C116C CTOF_DEL 0.213 4.519 4 top_reveal_coretop_instance/core0/trig_u/decode_u/secured_signal_13_28 NET DELAY 0.587 5.106 4 top_reveal_coretop_instance/core0/trig_u/decode_u/secured_instance_13_1/B->top_reveal_coretop_instance/core0/trig_u/decode_u/secured_instance_13_1/Z SLICE_R48C118D CTOF_DEL 0.213 5.319 5 top_reveal_coretop_instance/core0/trig_u/te_0/secured_signal_7_34 NET DELAY 0.543 5.862 5 top_reveal_coretop_instance/core0/trig_u/te_0/secured_instance_7_27/C->top_reveal_coretop_instance/core0/trig_u/te_0/secured_instance_7_27/Z SLICE_R48C120B CTOF_DEL 0.213 6.075 8 top_reveal_coretop_instance/core0/trig_u/te_0/secured_signal_7_137 NET DELAY 0.552 6.627 8 {top_reveal_coretop_instance/core0/trig_u/te_0/secured_instance_7_103/CE top_reveal_coretop_instance/core0/trig_u/te_0/secured_instance_7_105/CE} 0.000 6.627 1 Destination Clock Path Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- ------------------------ ------------- -------- --------------------- ------ CONSTRAINT 0.000 6.666 1 OSCA001.OSCA_inst/HFCLKOUT OSC_CORE_OSC_CORE_R1C137 CLOCK LATENCY 0.000 6.666 353 top_reveal_coretop_instance/core0/tm_u/secured_instance_1_108/secured_signal_0_140 NET DELAY 2.427 9.093 353 {top_reveal_coretop_instance/core0/trig_u/te_0/secured_instance_7_103/CLK top_reveal_coretop_instance/core0/trig_u/te_0/secured_instance_7_105/CLK} 0.000 9.093 1 Uncertainty -(0.000) 9.093 Setup time -(0.193) 8.900 ---------------------------------------- ------------------------ ------------- -------- --------------------- ------ Required Time 8.900 Arrival Time -(6.626) ---------------------------------------- ------------------------ ------------- -------- --------------------- ------ Path Slack (Passed) 2.273 ++++ Path 9 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Path Begin : top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_479/Q (SLICE_R44C120B) Path End : {top_reveal_coretop_instance/core0/trig_u/te_0/secured_instance_7_98/CE top_reveal_coretop_instance/core0/trig_u/te_0/secured_instance_7_101/CE} (SLICE_R53C119D) Source Clock : CLK (R) Destination Clock: CLK (R) Logic Level : 7 Delay Ratio : 62.3% (route), 37.7% (logic) Clock Skew : 0.000 ns Setup Constraint : 6.666 ns Path Slack : 2.273 ns (Passed) Source Clock Path Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- ------------------------ ------------- -------- --------------------- ------ OSCA001.OSCA_inst/HFCLKOUT OSC_CORE_OSC_CORE_R1C137 CLOCK LATENCY 0.000 0.000 353 top_reveal_coretop_instance/core0/tm_u/secured_instance_1_108/secured_signal_0_140 NET DELAY 2.427 2.427 353 {top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_478/CLK top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_479/CLK} 0.000 2.427 1 Data Path Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- ------------------------ ------------- -------- --------------------- ------ top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_479/CLK->top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_479/Q SLICE_R44C120B REG_DEL 0.307 2.734 4 top_reveal_coretop_instance/core0/jtag_int_u/secured_signal_2_161 NET DELAY 0.203 2.937 4 top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_240/B->top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_240/Z SLICE_R44C120B CTOF_DEL 0.213 3.150 1 top_reveal_coretop_instance/core0/jtag_int_u/secured_signal_2_586 NET DELAY 0.160 3.310 1 top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_218/D->top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_218/Z SLICE_R44C120D CTOF_DEL 0.213 3.523 7 top_reveal_coretop_instance/core0/tm_u/secured_signal_1_158 NET DELAY 0.160 3.683 7 top_reveal_coretop_instance/core0/trig_u/decode_u/secured_instance_13_13/C->top_reveal_coretop_instance/core0/trig_u/decode_u/secured_instance_13_13/Z SLICE_R44C120A CTOF_DEL 0.213 3.896 3 top_reveal_coretop_instance/core0/trig_u/decode_u/secured_signal_13_26 NET DELAY 0.410 4.306 3 top_reveal_coretop_instance/core0/trig_u/decode_u/secured_instance_13_2/A->top_reveal_coretop_instance/core0/trig_u/decode_u/secured_instance_13_2/Z SLICE_R44C116C CTOF_DEL 0.213 4.519 4 top_reveal_coretop_instance/core0/trig_u/decode_u/secured_signal_13_28 NET DELAY 0.587 5.106 4 top_reveal_coretop_instance/core0/trig_u/decode_u/secured_instance_13_1/B->top_reveal_coretop_instance/core0/trig_u/decode_u/secured_instance_13_1/Z SLICE_R48C118D CTOF_DEL 0.213 5.319 5 top_reveal_coretop_instance/core0/trig_u/te_0/secured_signal_7_34 NET DELAY 0.543 5.862 5 top_reveal_coretop_instance/core0/trig_u/te_0/secured_instance_7_27/C->top_reveal_coretop_instance/core0/trig_u/te_0/secured_instance_7_27/Z SLICE_R48C120B CTOF_DEL 0.213 6.075 8 top_reveal_coretop_instance/core0/trig_u/te_0/secured_signal_7_137 NET DELAY 0.552 6.627 8 {top_reveal_coretop_instance/core0/trig_u/te_0/secured_instance_7_98/CE top_reveal_coretop_instance/core0/trig_u/te_0/secured_instance_7_101/CE} 0.000 6.627 1 Destination Clock Path Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- ------------------------ ------------- -------- --------------------- ------ CONSTRAINT 0.000 6.666 1 OSCA001.OSCA_inst/HFCLKOUT OSC_CORE_OSC_CORE_R1C137 CLOCK LATENCY 0.000 6.666 353 top_reveal_coretop_instance/core0/tm_u/secured_instance_1_108/secured_signal_0_140 NET DELAY 2.427 9.093 353 {top_reveal_coretop_instance/core0/trig_u/te_0/secured_instance_7_98/CLK top_reveal_coretop_instance/core0/trig_u/te_0/secured_instance_7_101/CLK} 0.000 9.093 1 Uncertainty -(0.000) 9.093 Setup time -(0.193) 8.900 ---------------------------------------- ------------------------ ------------- -------- --------------------- ------ Required Time 8.900 Arrival Time -(6.626) ---------------------------------------- ------------------------ ------------- -------- --------------------- ------ Path Slack (Passed) 2.273 ++++ Path 10 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Path Begin : top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_479/Q (SLICE_R44C120B) Path End : {top_reveal_coretop_instance/core0/trig_u/te_0/secured_instance_7_83/CE top_reveal_coretop_instance/core0/trig_u/te_0/secured_instance_7_85/CE} (SLICE_R49C118B) Source Clock : CLK (R) Destination Clock: CLK (R) Logic Level : 7 Delay Ratio : 62.3% (route), 37.7% (logic) Clock Skew : 0.000 ns Setup Constraint : 6.666 ns Path Slack : 2.273 ns (Passed) Source Clock Path Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- ------------------------ ------------- -------- --------------------- ------ OSCA001.OSCA_inst/HFCLKOUT OSC_CORE_OSC_CORE_R1C137 CLOCK LATENCY 0.000 0.000 353 top_reveal_coretop_instance/core0/tm_u/secured_instance_1_108/secured_signal_0_140 NET DELAY 2.427 2.427 353 {top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_478/CLK top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_479/CLK} 0.000 2.427 1 Data Path Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- ------------------------ ------------- -------- --------------------- ------ top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_479/CLK->top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_479/Q SLICE_R44C120B REG_DEL 0.307 2.734 4 top_reveal_coretop_instance/core0/jtag_int_u/secured_signal_2_161 NET DELAY 0.203 2.937 4 top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_240/B->top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_240/Z SLICE_R44C120B CTOF_DEL 0.213 3.150 1 top_reveal_coretop_instance/core0/jtag_int_u/secured_signal_2_586 NET DELAY 0.160 3.310 1 top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_218/D->top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_218/Z SLICE_R44C120D CTOF_DEL 0.213 3.523 7 top_reveal_coretop_instance/core0/tm_u/secured_signal_1_158 NET DELAY 0.160 3.683 7 top_reveal_coretop_instance/core0/trig_u/decode_u/secured_instance_13_13/C->top_reveal_coretop_instance/core0/trig_u/decode_u/secured_instance_13_13/Z SLICE_R44C120A CTOF_DEL 0.213 3.896 3 top_reveal_coretop_instance/core0/trig_u/decode_u/secured_signal_13_26 NET DELAY 0.410 4.306 3 top_reveal_coretop_instance/core0/trig_u/decode_u/secured_instance_13_2/A->top_reveal_coretop_instance/core0/trig_u/decode_u/secured_instance_13_2/Z SLICE_R44C116C CTOF_DEL 0.213 4.519 4 top_reveal_coretop_instance/core0/trig_u/decode_u/secured_signal_13_28 NET DELAY 0.587 5.106 4 top_reveal_coretop_instance/core0/trig_u/decode_u/secured_instance_13_1/B->top_reveal_coretop_instance/core0/trig_u/decode_u/secured_instance_13_1/Z SLICE_R48C118D CTOF_DEL 0.213 5.319 5 top_reveal_coretop_instance/core0/trig_u/te_0/secured_signal_7_34 NET DELAY 0.543 5.862 5 top_reveal_coretop_instance/core0/trig_u/te_0/secured_instance_7_27/C->top_reveal_coretop_instance/core0/trig_u/te_0/secured_instance_7_27/Z SLICE_R48C120B CTOF_DEL 0.213 6.075 8 top_reveal_coretop_instance/core0/trig_u/te_0/secured_signal_7_137 NET DELAY 0.552 6.627 8 {top_reveal_coretop_instance/core0/trig_u/te_0/secured_instance_7_83/CE top_reveal_coretop_instance/core0/trig_u/te_0/secured_instance_7_85/CE} 0.000 6.627 1 Destination Clock Path Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- ------------------------ ------------- -------- --------------------- ------ CONSTRAINT 0.000 6.666 1 OSCA001.OSCA_inst/HFCLKOUT OSC_CORE_OSC_CORE_R1C137 CLOCK LATENCY 0.000 6.666 353 top_reveal_coretop_instance/core0/tm_u/secured_instance_1_108/secured_signal_0_140 NET DELAY 2.427 9.093 353 {top_reveal_coretop_instance/core0/trig_u/te_0/secured_instance_7_83/CLK top_reveal_coretop_instance/core0/trig_u/te_0/secured_instance_7_85/CLK} 0.000 9.093 1 Uncertainty -(0.000) 9.093 Setup time -(0.193) 8.900 ---------------------------------------- ------------------------ ------------- -------- --------------------- ------ Required Time 8.900 Arrival Time -(6.626) ---------------------------------------- ------------------------ ------------- -------- --------------------- ------ Path Slack (Passed) 2.273 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ End of Detailed Report for timing paths +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ ########################################################## =============================================================== 3 Hold at Speed Grade m Corner at 0 Degrees =============================================================== 3.1 Endpoint slacks ======================= ------------------------------------------------------- Listing 10 End Points | Slack ------------------------------------------------------- top_reveal_coretop_instance/core0/tm_u/secured_instance_1_108/secured_instance_0_235/WD0 | 0.083 ns top_reveal_coretop_instance/core0/tm_u/secured_instance_1_108/secured_instance_0_211/WD0 | 0.083 ns top_reveal_coretop_instance/core0/tm_u/secured_instance_1_108/secured_instance_0_282/WD0 | 0.088 ns top_reveal_coretop_instance/core0/tm_u/secured_instance_1_108/secured_instance_0_264/WD0 | 0.088 ns top_reveal_coretop_instance/core0/tm_u/secured_instance_1_108/secured_instance_0_229/WD0 | 0.088 ns top_reveal_coretop_instance/core0/tm_u/secured_instance_1_108/secured_instance_0_214/WD0 | 0.088 ns top_reveal_coretop_instance/core0/tm_u/secured_instance_1_108/secured_instance_0_202/WD0 | 0.088 ns top_reveal_coretop_instance/core0/tm_u/secured_instance_1_108/secured_instance_0_291/WD0 | 0.090 ns top_reveal_coretop_instance/core0/tm_u/secured_instance_1_108/secured_instance_0_285/WD0 | 0.090 ns top_reveal_coretop_instance/core0/tm_u/secured_instance_1_108/secured_instance_0_276/WD0 | 0.096 ns ------------------------------------------------------- | Hold # of endpoints with negative slack: | 0 | ------------------------------------------------------- 3.2 Detailed Report ======================= XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX Detail report of critical paths XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Detailed Report for timing paths +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ ++++Path 1 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Path Begin : top_reveal_coretop_instance/core0/tm_u/secured_instance_1_196/Q (SLICE_R52C116D) Path End : top_reveal_coretop_instance/core0/tm_u/secured_instance_1_108/secured_instance_0_235/WD0 (SLICE_R52C117C) Source Clock : CLK (R) Destination Clock: CLK (R) Logic Level : 1 Delay Ratio : 35.7% (route), 64.3% (logic) Clock Skew : 0.000 ns Hold Constraint : 0.000 ns Path Slack : 0.083 ns (Passed) Source Clock Path Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- ------------------------ ------------- ----- --------------------- ------ OSCA001.OSCA_inst/HFCLKOUT OSC_CORE_OSC_CORE_R1C137 CLOCK LATENCY 0.000 0.000 354 top_reveal_coretop_instance/core0/tm_u/secured_instance_1_108/secured_signal_0_140 NET DELAY 1.762 1.762 354 {top_reveal_coretop_instance/core0/tm_u/secured_instance_1_196/CLK top_reveal_coretop_instance/core0/tm_u/secured_instance_1_197/CLK} 0.000 1.762 1 Data Path Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- ------------------------ ------------- ----- --------------------- ------ top_reveal_coretop_instance/core0/tm_u/secured_instance_1_196/CLK->top_reveal_coretop_instance/core0/tm_u/secured_instance_1_196/Q SLICE_R52C116D REG_DEL 0.178 1.940 2 top_reveal_coretop_instance/core0/tm_u/secured_instance_1_108/secured_signal_0_52 NET DELAY 0.099 2.039 2 top_reveal_coretop_instance/core0/tm_u/secured_instance_1_108/secured_instance_0_235/WD0 0.000 2.039 1 Destination Clock Path Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- ------------------------ ------------- ----- --------------------- ------ CONSTRAINT 0.000 0.000 1 OSCA001.OSCA_inst/HFCLKOUT OSC_CORE_OSC_CORE_R1C137 CLOCK LATENCY 0.000 0.000 354 top_reveal_coretop_instance/core0/tm_u/secured_instance_1_108/secured_signal_0_140 NET DELAY 1.762 1.762 354 top_reveal_coretop_instance/core0/tm_u/secured_instance_1_108/secured_instance_0_235/WCK 0.000 1.762 1 Uncertainty 0.000 1.762 Hold time 0.194 1.956 ---------------------------------------- ------------------------ ------------- ----- --------------------- ------ Required Time -1.956 Arrival Time 2.039 ---------------------------------------- ------------------------ ------------- ----- --------------------- ------ Path Slack (Passed) 0.083 ++++ Path 2 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Path Begin : top_reveal_coretop_instance/core0/tm_u/secured_instance_1_228/Q (SLICE_R49C113D) Path End : top_reveal_coretop_instance/core0/tm_u/secured_instance_1_108/secured_instance_0_211/WD0 (SLICE_R49C111C) Source Clock : CLK (R) Destination Clock: CLK (R) Logic Level : 1 Delay Ratio : 35.7% (route), 64.3% (logic) Clock Skew : 0.000 ns Hold Constraint : 0.000 ns Path Slack : 0.083 ns (Passed) Source Clock Path Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- ------------------------ ------------- ----- --------------------- ------ OSCA001.OSCA_inst/HFCLKOUT OSC_CORE_OSC_CORE_R1C137 CLOCK LATENCY 0.000 0.000 354 top_reveal_coretop_instance/core0/tm_u/secured_instance_1_108/secured_signal_0_140 NET DELAY 1.762 1.762 354 {top_reveal_coretop_instance/core0/tm_u/secured_instance_1_228/CLK top_reveal_coretop_instance/core0/tm_u/secured_instance_1_229/CLK} 0.000 1.762 1 Data Path Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- ------------------------ ------------- ----- --------------------- ------ top_reveal_coretop_instance/core0/tm_u/secured_instance_1_228/CLK->top_reveal_coretop_instance/core0/tm_u/secured_instance_1_228/Q SLICE_R49C113D REG_DEL 0.178 1.940 2 top_reveal_coretop_instance/core0/tm_u/secured_instance_1_108/secured_signal_0_20 NET DELAY 0.099 2.039 2 top_reveal_coretop_instance/core0/tm_u/secured_instance_1_108/secured_instance_0_211/WD0 0.000 2.039 1 Destination Clock Path Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- ------------------------ ------------- ----- --------------------- ------ CONSTRAINT 0.000 0.000 1 OSCA001.OSCA_inst/HFCLKOUT OSC_CORE_OSC_CORE_R1C137 CLOCK LATENCY 0.000 0.000 354 top_reveal_coretop_instance/core0/tm_u/secured_instance_1_108/secured_signal_0_140 NET DELAY 1.762 1.762 354 top_reveal_coretop_instance/core0/tm_u/secured_instance_1_108/secured_instance_0_211/WCK 0.000 1.762 1 Uncertainty 0.000 1.762 Hold time 0.194 1.956 ---------------------------------------- ------------------------ ------------- ----- --------------------- ------ Required Time -1.956 Arrival Time 2.039 ---------------------------------------- ------------------------ ------------- ----- --------------------- ------ Path Slack (Passed) 0.083 ++++ Path 3 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Path Begin : top_reveal_coretop_instance/core0/tm_u/secured_instance_1_200/Q (SLICE_R53C114B) Path End : top_reveal_coretop_instance/core0/tm_u/secured_instance_1_108/secured_instance_0_282/WD0 (SLICE_R52C114C) Source Clock : CLK (R) Destination Clock: CLK (R) Logic Level : 1 Delay Ratio : 36.9% (route), 63.1% (logic) Clock Skew : 0.000 ns Hold Constraint : 0.000 ns Path Slack : 0.088 ns (Passed) Source Clock Path Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- ------------------------ ------------- ----- --------------------- ------ OSCA001.OSCA_inst/HFCLKOUT OSC_CORE_OSC_CORE_R1C137 CLOCK LATENCY 0.000 0.000 354 top_reveal_coretop_instance/core0/tm_u/secured_instance_1_108/secured_signal_0_140 NET DELAY 1.762 1.762 354 {top_reveal_coretop_instance/core0/tm_u/secured_instance_1_200/CLK top_reveal_coretop_instance/core0/tm_u/secured_instance_1_201/CLK} 0.000 1.762 1 Data Path Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- ------------------------ ------------- ----- --------------------- ------ top_reveal_coretop_instance/core0/tm_u/secured_instance_1_200/CLK->top_reveal_coretop_instance/core0/tm_u/secured_instance_1_200/Q SLICE_R53C114B REG_DEL 0.178 1.940 2 top_reveal_coretop_instance/core0/tm_u/secured_instance_1_108/secured_signal_0_48 NET DELAY 0.104 2.044 2 top_reveal_coretop_instance/core0/tm_u/secured_instance_1_108/secured_instance_0_282/WD0 0.000 2.044 1 Destination Clock Path Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- ------------------------ ------------- ----- --------------------- ------ CONSTRAINT 0.000 0.000 1 OSCA001.OSCA_inst/HFCLKOUT OSC_CORE_OSC_CORE_R1C137 CLOCK LATENCY 0.000 0.000 354 top_reveal_coretop_instance/core0/tm_u/secured_instance_1_108/secured_signal_0_140 NET DELAY 1.762 1.762 354 top_reveal_coretop_instance/core0/tm_u/secured_instance_1_108/secured_instance_0_282/WCK 0.000 1.762 1 Uncertainty 0.000 1.762 Hold time 0.194 1.956 ---------------------------------------- ------------------------ ------------- ----- --------------------- ------ Required Time -1.956 Arrival Time 2.044 ---------------------------------------- ------------------------ ------------- ----- --------------------- ------ Path Slack (Passed) 0.088 ++++ Path 4 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Path Begin : top_reveal_coretop_instance/core0/tm_u/secured_instance_1_224/Q (SLICE_R47C113D) Path End : top_reveal_coretop_instance/core0/tm_u/secured_instance_1_108/secured_instance_0_264/WD0 (SLICE_R47C114C) Source Clock : CLK (R) Destination Clock: CLK (R) Logic Level : 1 Delay Ratio : 36.9% (route), 63.1% (logic) Clock Skew : 0.000 ns Hold Constraint : 0.000 ns Path Slack : 0.088 ns (Passed) Source Clock Path Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- ------------------------ ------------- ----- --------------------- ------ OSCA001.OSCA_inst/HFCLKOUT OSC_CORE_OSC_CORE_R1C137 CLOCK LATENCY 0.000 0.000 354 top_reveal_coretop_instance/core0/tm_u/secured_instance_1_108/secured_signal_0_140 NET DELAY 1.762 1.762 354 {top_reveal_coretop_instance/core0/tm_u/secured_instance_1_224/CLK top_reveal_coretop_instance/core0/tm_u/secured_instance_1_225/CLK} 0.000 1.762 1 Data Path Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- ------------------------ ------------- ----- --------------------- ------ top_reveal_coretop_instance/core0/tm_u/secured_instance_1_224/CLK->top_reveal_coretop_instance/core0/tm_u/secured_instance_1_224/Q SLICE_R47C113D REG_DEL 0.178 1.940 2 top_reveal_coretop_instance/core0/tm_u/secured_instance_1_108/secured_signal_0_24 NET DELAY 0.104 2.044 2 top_reveal_coretop_instance/core0/tm_u/secured_instance_1_108/secured_instance_0_264/WD0 0.000 2.044 1 Destination Clock Path Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- ------------------------ ------------- ----- --------------------- ------ CONSTRAINT 0.000 0.000 1 OSCA001.OSCA_inst/HFCLKOUT OSC_CORE_OSC_CORE_R1C137 CLOCK LATENCY 0.000 0.000 354 top_reveal_coretop_instance/core0/tm_u/secured_instance_1_108/secured_signal_0_140 NET DELAY 1.762 1.762 354 top_reveal_coretop_instance/core0/tm_u/secured_instance_1_108/secured_instance_0_264/WCK 0.000 1.762 1 Uncertainty 0.000 1.762 Hold time 0.194 1.956 ---------------------------------------- ------------------------ ------------- ----- --------------------- ------ Required Time -1.956 Arrival Time 2.044 ---------------------------------------- ------------------------ ------------- ----- --------------------- ------ Path Slack (Passed) 0.088 ++++ Path 5 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Path Begin : top_reveal_coretop_instance/core0/tm_u/secured_instance_1_204/Q (SLICE_R50C115B) Path End : top_reveal_coretop_instance/core0/tm_u/secured_instance_1_108/secured_instance_0_229/WD0 (SLICE_R49C115C) Source Clock : CLK (R) Destination Clock: CLK (R) Logic Level : 1 Delay Ratio : 36.9% (route), 63.1% (logic) Clock Skew : 0.000 ns Hold Constraint : 0.000 ns Path Slack : 0.088 ns (Passed) Source Clock Path Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- ------------------------ ------------- ----- --------------------- ------ OSCA001.OSCA_inst/HFCLKOUT OSC_CORE_OSC_CORE_R1C137 CLOCK LATENCY 0.000 0.000 354 top_reveal_coretop_instance/core0/tm_u/secured_instance_1_108/secured_signal_0_140 NET DELAY 1.762 1.762 354 {top_reveal_coretop_instance/core0/tm_u/secured_instance_1_204/CLK top_reveal_coretop_instance/core0/tm_u/secured_instance_1_205/CLK} 0.000 1.762 1 Data Path Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- ------------------------ ------------- ----- --------------------- ------ top_reveal_coretop_instance/core0/tm_u/secured_instance_1_204/CLK->top_reveal_coretop_instance/core0/tm_u/secured_instance_1_204/Q SLICE_R50C115B REG_DEL 0.178 1.940 2 top_reveal_coretop_instance/core0/tm_u/secured_instance_1_108/secured_signal_0_44 NET DELAY 0.104 2.044 2 top_reveal_coretop_instance/core0/tm_u/secured_instance_1_108/secured_instance_0_229/WD0 0.000 2.044 1 Destination Clock Path Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- ------------------------ ------------- ----- --------------------- ------ CONSTRAINT 0.000 0.000 1 OSCA001.OSCA_inst/HFCLKOUT OSC_CORE_OSC_CORE_R1C137 CLOCK LATENCY 0.000 0.000 354 top_reveal_coretop_instance/core0/tm_u/secured_instance_1_108/secured_signal_0_140 NET DELAY 1.762 1.762 354 top_reveal_coretop_instance/core0/tm_u/secured_instance_1_108/secured_instance_0_229/WCK 0.000 1.762 1 Uncertainty 0.000 1.762 Hold time 0.194 1.956 ---------------------------------------- ------------------------ ------------- ----- --------------------- ------ Required Time -1.956 Arrival Time 2.044 ---------------------------------------- ------------------------ ------------- ----- --------------------- ------ Path Slack (Passed) 0.088 ++++ Path 6 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Path Begin : top_reveal_coretop_instance/core0/tm_u/secured_instance_1_224/Q (SLICE_R47C113D) Path End : top_reveal_coretop_instance/core0/tm_u/secured_instance_1_108/secured_instance_0_214/WD0 (SLICE_R47C115C) Source Clock : CLK (R) Destination Clock: CLK (R) Logic Level : 1 Delay Ratio : 36.9% (route), 63.1% (logic) Clock Skew : 0.000 ns Hold Constraint : 0.000 ns Path Slack : 0.088 ns (Passed) Source Clock Path Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- ------------------------ ------------- ----- --------------------- ------ OSCA001.OSCA_inst/HFCLKOUT OSC_CORE_OSC_CORE_R1C137 CLOCK LATENCY 0.000 0.000 354 top_reveal_coretop_instance/core0/tm_u/secured_instance_1_108/secured_signal_0_140 NET DELAY 1.762 1.762 354 {top_reveal_coretop_instance/core0/tm_u/secured_instance_1_224/CLK top_reveal_coretop_instance/core0/tm_u/secured_instance_1_225/CLK} 0.000 1.762 1 Data Path Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- ------------------------ ------------- ----- --------------------- ------ top_reveal_coretop_instance/core0/tm_u/secured_instance_1_224/CLK->top_reveal_coretop_instance/core0/tm_u/secured_instance_1_224/Q SLICE_R47C113D REG_DEL 0.178 1.940 2 top_reveal_coretop_instance/core0/tm_u/secured_instance_1_108/secured_signal_0_24 NET DELAY 0.104 2.044 2 top_reveal_coretop_instance/core0/tm_u/secured_instance_1_108/secured_instance_0_214/WD0 0.000 2.044 1 Destination Clock Path Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- ------------------------ ------------- ----- --------------------- ------ CONSTRAINT 0.000 0.000 1 OSCA001.OSCA_inst/HFCLKOUT OSC_CORE_OSC_CORE_R1C137 CLOCK LATENCY 0.000 0.000 354 top_reveal_coretop_instance/core0/tm_u/secured_instance_1_108/secured_signal_0_140 NET DELAY 1.762 1.762 354 top_reveal_coretop_instance/core0/tm_u/secured_instance_1_108/secured_instance_0_214/WCK 0.000 1.762 1 Uncertainty 0.000 1.762 Hold time 0.194 1.956 ---------------------------------------- ------------------------ ------------- ----- --------------------- ------ Required Time -1.956 Arrival Time 2.044 ---------------------------------------- ------------------------ ------------- ----- --------------------- ------ Path Slack (Passed) 0.088 ++++ Path 7 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Path Begin : top_reveal_coretop_instance/core0/tm_u/secured_instance_1_240/Q (SLICE_R43C115B) Path End : top_reveal_coretop_instance/core0/tm_u/secured_instance_1_108/secured_instance_0_202/WD0 (SLICE_R45C115C) Source Clock : CLK (R) Destination Clock: CLK (R) Logic Level : 1 Delay Ratio : 36.9% (route), 63.1% (logic) Clock Skew : 0.000 ns Hold Constraint : 0.000 ns Path Slack : 0.088 ns (Passed) Source Clock Path Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- ------------------------ ------------- ----- --------------------- ------ OSCA001.OSCA_inst/HFCLKOUT OSC_CORE_OSC_CORE_R1C137 CLOCK LATENCY 0.000 0.000 354 top_reveal_coretop_instance/core0/tm_u/secured_instance_1_108/secured_signal_0_140 NET DELAY 1.762 1.762 354 {top_reveal_coretop_instance/core0/tm_u/secured_instance_1_240/CLK top_reveal_coretop_instance/core0/tm_u/secured_instance_1_241/CLK} 0.000 1.762 1 Data Path Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- ------------------------ ------------- ----- --------------------- ------ top_reveal_coretop_instance/core0/tm_u/secured_instance_1_240/CLK->top_reveal_coretop_instance/core0/tm_u/secured_instance_1_240/Q SLICE_R43C115B REG_DEL 0.178 1.940 2 top_reveal_coretop_instance/core0/tm_u/secured_instance_1_108/secured_signal_0_8 NET DELAY 0.104 2.044 2 top_reveal_coretop_instance/core0/tm_u/secured_instance_1_108/secured_instance_0_202/WD0 0.000 2.044 1 Destination Clock Path Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- ------------------------ ------------- ----- --------------------- ------ CONSTRAINT 0.000 0.000 1 OSCA001.OSCA_inst/HFCLKOUT OSC_CORE_OSC_CORE_R1C137 CLOCK LATENCY 0.000 0.000 354 top_reveal_coretop_instance/core0/tm_u/secured_instance_1_108/secured_signal_0_140 NET DELAY 1.762 1.762 354 top_reveal_coretop_instance/core0/tm_u/secured_instance_1_108/secured_instance_0_202/WCK 0.000 1.762 1 Uncertainty 0.000 1.762 Hold time 0.194 1.956 ---------------------------------------- ------------------------ ------------- ----- --------------------- ------ Required Time -1.956 Arrival Time 2.044 ---------------------------------------- ------------------------ ------------- ----- --------------------- ------ Path Slack (Passed) 0.088 ++++ Path 8 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Path Begin : top_reveal_coretop_instance/core0/tm_u/secured_instance_1_188/Q (SLICE_R53C114D) Path End : top_reveal_coretop_instance/core0/tm_u/secured_instance_1_108/secured_instance_0_291/WD0 (SLICE_R54C114C) Source Clock : CLK (R) Destination Clock: CLK (R) Logic Level : 1 Delay Ratio : 37.3% (route), 62.7% (logic) Clock Skew : 0.000 ns Hold Constraint : 0.000 ns Path Slack : 0.090 ns (Passed) Source Clock Path Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- ------------------------ ------------- ----- --------------------- ------ OSCA001.OSCA_inst/HFCLKOUT OSC_CORE_OSC_CORE_R1C137 CLOCK LATENCY 0.000 0.000 354 top_reveal_coretop_instance/core0/tm_u/secured_instance_1_108/secured_signal_0_140 NET DELAY 1.762 1.762 354 {top_reveal_coretop_instance/core0/tm_u/secured_instance_1_188/CLK top_reveal_coretop_instance/core0/tm_u/secured_instance_1_189/CLK} 0.000 1.762 1 Data Path Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- ------------------------ ------------- ----- --------------------- ------ top_reveal_coretop_instance/core0/tm_u/secured_instance_1_188/CLK->top_reveal_coretop_instance/core0/tm_u/secured_instance_1_188/Q SLICE_R53C114D REG_DEL 0.178 1.940 2 top_reveal_coretop_instance/core0/tm_u/secured_instance_1_108/secured_signal_0_60 NET DELAY 0.106 2.046 2 top_reveal_coretop_instance/core0/tm_u/secured_instance_1_108/secured_instance_0_291/WD0 0.000 2.046 1 Destination Clock Path Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- ------------------------ ------------- ----- --------------------- ------ CONSTRAINT 0.000 0.000 1 OSCA001.OSCA_inst/HFCLKOUT OSC_CORE_OSC_CORE_R1C137 CLOCK LATENCY 0.000 0.000 354 top_reveal_coretop_instance/core0/tm_u/secured_instance_1_108/secured_signal_0_140 NET DELAY 1.762 1.762 354 top_reveal_coretop_instance/core0/tm_u/secured_instance_1_108/secured_instance_0_291/WCK 0.000 1.762 1 Uncertainty 0.000 1.762 Hold time 0.194 1.956 ---------------------------------------- ------------------------ ------------- ----- --------------------- ------ Required Time -1.956 Arrival Time 2.046 ---------------------------------------- ------------------------ ------------- ----- --------------------- ------ Path Slack (Passed) 0.090 ++++ Path 9 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Path Begin : top_reveal_coretop_instance/core0/tm_u/secured_instance_1_196/Q (SLICE_R52C116D) Path End : top_reveal_coretop_instance/core0/tm_u/secured_instance_1_108/secured_instance_0_285/WD0 (SLICE_R53C116C) Source Clock : CLK (R) Destination Clock: CLK (R) Logic Level : 1 Delay Ratio : 37.3% (route), 62.7% (logic) Clock Skew : 0.000 ns Hold Constraint : 0.000 ns Path Slack : 0.090 ns (Passed) Source Clock Path Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- ------------------------ ------------- ----- --------------------- ------ OSCA001.OSCA_inst/HFCLKOUT OSC_CORE_OSC_CORE_R1C137 CLOCK LATENCY 0.000 0.000 354 top_reveal_coretop_instance/core0/tm_u/secured_instance_1_108/secured_signal_0_140 NET DELAY 1.762 1.762 354 {top_reveal_coretop_instance/core0/tm_u/secured_instance_1_196/CLK top_reveal_coretop_instance/core0/tm_u/secured_instance_1_197/CLK} 0.000 1.762 1 Data Path Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- ------------------------ ------------- ----- --------------------- ------ top_reveal_coretop_instance/core0/tm_u/secured_instance_1_196/CLK->top_reveal_coretop_instance/core0/tm_u/secured_instance_1_196/Q SLICE_R52C116D REG_DEL 0.178 1.940 2 top_reveal_coretop_instance/core0/tm_u/secured_instance_1_108/secured_signal_0_52 NET DELAY 0.106 2.046 2 top_reveal_coretop_instance/core0/tm_u/secured_instance_1_108/secured_instance_0_285/WD0 0.000 2.046 1 Destination Clock Path Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- ------------------------ ------------- ----- --------------------- ------ CONSTRAINT 0.000 0.000 1 OSCA001.OSCA_inst/HFCLKOUT OSC_CORE_OSC_CORE_R1C137 CLOCK LATENCY 0.000 0.000 354 top_reveal_coretop_instance/core0/tm_u/secured_instance_1_108/secured_signal_0_140 NET DELAY 1.762 1.762 354 top_reveal_coretop_instance/core0/tm_u/secured_instance_1_108/secured_instance_0_285/WCK 0.000 1.762 1 Uncertainty 0.000 1.762 Hold time 0.194 1.956 ---------------------------------------- ------------------------ ------------- ----- --------------------- ------ Required Time -1.956 Arrival Time 2.046 ---------------------------------------- ------------------------ ------------- ----- --------------------- ------ Path Slack (Passed) 0.090 ++++ Path 10 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Path Begin : top_reveal_coretop_instance/core0/tm_u/secured_instance_1_208/Q (SLICE_R49C112D) Path End : top_reveal_coretop_instance/core0/tm_u/secured_instance_1_108/secured_instance_0_276/WD0 (SLICE_R50C112C) Source Clock : CLK (R) Destination Clock: CLK (R) Logic Level : 1 Delay Ratio : 38.6% (route), 61.4% (logic) Clock Skew : 0.000 ns Hold Constraint : 0.000 ns Path Slack : 0.096 ns (Passed) Source Clock Path Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- ------------------------ ------------- ----- --------------------- ------ OSCA001.OSCA_inst/HFCLKOUT OSC_CORE_OSC_CORE_R1C137 CLOCK LATENCY 0.000 0.000 354 top_reveal_coretop_instance/core0/tm_u/secured_instance_1_108/secured_signal_0_140 NET DELAY 1.762 1.762 354 {top_reveal_coretop_instance/core0/tm_u/secured_instance_1_208/CLK top_reveal_coretop_instance/core0/tm_u/secured_instance_1_209/CLK} 0.000 1.762 1 Data Path Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- ------------------------ ------------- ----- --------------------- ------ top_reveal_coretop_instance/core0/tm_u/secured_instance_1_208/CLK->top_reveal_coretop_instance/core0/tm_u/secured_instance_1_208/Q SLICE_R49C112D REG_DEL 0.178 1.940 2 top_reveal_coretop_instance/core0/tm_u/secured_instance_1_108/secured_signal_0_40 NET DELAY 0.112 2.052 2 top_reveal_coretop_instance/core0/tm_u/secured_instance_1_108/secured_instance_0_276/WD0 0.000 2.052 1 Destination Clock Path Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- ------------------------ ------------- ----- --------------------- ------ CONSTRAINT 0.000 0.000 1 OSCA001.OSCA_inst/HFCLKOUT OSC_CORE_OSC_CORE_R1C137 CLOCK LATENCY 0.000 0.000 354 top_reveal_coretop_instance/core0/tm_u/secured_instance_1_108/secured_signal_0_140 NET DELAY 1.762 1.762 354 top_reveal_coretop_instance/core0/tm_u/secured_instance_1_108/secured_instance_0_276/WCK 0.000 1.762 1 Uncertainty 0.000 1.762 Hold time 0.194 1.956 ---------------------------------------- ------------------------ ------------- ----- --------------------- ------ Required Time -1.956 Arrival Time 2.052 ---------------------------------------- ------------------------ ------------- ----- --------------------- ------ Path Slack (Passed) 0.096 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ End of Detailed Report for timing paths +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 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