Copyright (c) 2002-2022 Lattice Semiconductor Corporation, All rights reserved. Mon Sep 9 14:38:59 2024 Command Line: par -w -n 1 -t 1 -s 1 -cores 1 -pack 0 -hsp m -exp \ parPathBased=ON LAB04_Async_rst_map.udb LAB04_Async_rst.udb Cost Table Summary Level/ Number Estimated Timing Estimated Worst Timing Run Run Cost [udb] Unrouted Worst Slack Score Slack(hold) Score(hold) Time Status ---------- -------- ----------- ------ --------------- ----------- ---- ------ 5_1 * 0 2.801 0 0.167 0 30 Completed * : Design saved. Total (real) run time for 1-seed: 31 secs par done! Lattice Place and Route Report for Design "LAB04_Async_rst_map.udb" Mon Sep 9 14:38:59 2024 Best Par Run PAR: Place And Route Radiant Software (64-bit) 2024.1.0.34.2. Command Line: par -w -t 1 -cores 1 -pack 0 -hsp m -exp parPathBased=ON \ LAB04_Async_rst_map.udb LAB04_Async_rst_par.dir/5_1.udb Loading LAB04_Async_rst_map.udb ... Loading device for application GENERIC from file 'jd5d80.nph' in environment: C:/lscc/radiant/2024.1/ispfpga. Package Status: Final Version 16. Performance Hardware Data Status: Final Version 3.9. Design: Top Family: LFCPNX Device: LFCPNX-100 Package: LFG672 Performance Grade: 9_High-Performance_1.0V Constraint Summary Total number of constraints: 23 Total number of constraints dropped: 0 Device SLICE utilization summary after final SLICE packing: SLICE 755/39936 1% used Number of Signals: 2578 Number of Connections: 7109 Device utilization summary: VHI 1/1 100% used SIOLOGIC 3/300 1% used EBR 2/208 1% used SEIO18A 1/132 1% used 1/132 0% bonded SEIO33 9/299 3% used 9/167 5% bonded OSC 1/1 100% used CONFIG_JTAG 1/1 100% used SLICE 755/39936 2% used LUT 1498/79872 2% used REG 1008/79872 1% used Pin Constraint Summary: 6 out of 10 pins locked (60% locked). Starting Placer Phase 0 (HIER). CPU time: 6 secs , REAL time: 6 secs ............ Finished Placer Phase 0 (HIER). CPU time: 6 secs , REAL time: 6 secs Starting Placer Phase 1. CPU time: 6 secs , REAL time: 6 secs .. .. ............... Placer score = 757222. Finished Placer Phase 1. CPU time: 10 secs , REAL time: 11 secs Starting Placer Phase 2. . Placer score = 751964 Finished Placer Phase 2. CPU time: 10 secs , REAL time: 11 secs Clock Report Global Clock Resources: CLK_PIN : 0 out of 26 (0%) PLL : 0 out of 4 (0%) PCS : 0 out of 2 (0%) DCS : 0 out of 2 (0%) DCC : 0 out of 62 (0%) ECLKDIV : 0 out of 12 (0%) PCLKDIV : 0 out of 2 (0%) OSC : 1 out of 1 (100%) Global Clocks: PRIMARY "clk150" from HFCLKOUT on comp "OSCA001.OSCA_inst" on site "OSC_CORE_R1C137", clk load = 335, ce load = 0, sr load = 0 PRIMARY "jtck" from JTCK on comp "jtaghub_inst.jtagg_u" on site "TCONFIG_JTAG_CORE145", clk load = 249, ce load = 0, sr load = 0 PRIMARY "top_reveal_coretop_instance.core0.reset_rvl_n" from F0 on comp "top_reveal_coretop_instance.core0.reset_rvl_n_cZ" on site "R38C74A", clk load = 0, ce load = 0, sr load = 302 PRIMARY : 3 out of 16 (18%) Edge Clocks: No edge clock selected. I/O Usage Summary (final): 9 out of 299 (3.0%) SEIO33 sites used. 9 out of 167 (5.4%) bonded SEIO33 sites used. Number of SEIO33 components: 9; differential: 0 Number of Vref pins used: 0 1 out of 132 (0.8%) SEIO18 sites used. 1 out of 132 (0.8%) bonded SEIO18 sites used. Number of SEIO18 components: 1; differential: 0 0 out of 66 (0.0%) DIFFIO18 sites used. 0 out of 66 (0.0%) bonded DIFFIO18 sites used. Number of DIFFIO18 components: 0; differential: 0 I/O Bank Usage Summary: +----------+---------------+------------+------------+------------+ | I/O Bank | Usage | Bank Vccio | Bank Vref1 | Bank Vref2 | +----------+---------------+------------+------------+------------+ | 0 | 0 / 24 ( 0%) | - | - | - | | 1 | 9 / 39 ( 23%) | 3.3V | - | - | | 2 | 0 / 32 ( 0%) | - | - | - | | 3 | 0 / 48 ( 0%) | - | - | - | | 4 | 0 / 48 ( 0%) | - | - | - | | 5 | 1 / 36 ( 2%) | 1.8V | - | - | | 6 | 0 / 32 ( 0%) | - | - | - | | 7 | 0 / 40 ( 0%) | - | - | - | +----------+---------------+------------+------------+------------+ Total Placer CPU time: 11 secs , REAL time: 11 secs Checksum -- place: c4c51c779b0b3d263d44ff17644a61e4a6451bcd Writing design to file LAB04_Async_rst_par.dir/5_1.udb ... Start NBR router at 14:39:10 09/09/24 ***************************************************************** Info: NBR allows conflicts(one node used by more than one signal) in the earlier iterations. In each iteration, it tries to solve the conflicts while keeping the critical connections routed as short as possible. The routing process is said to be completed when no conflicts exist and all connections are routed. Note: NBR uses a different method to calculate timing slacks. The worst slack and total negative slack may not be the same as that in timing report. You should always run the timing tool to verify your design. ***************************************************************** Starting routing resource preassignment Preassignment Summary: -------------------------------------------------------------------------------- 359 connections routed with dedicated routing resources 3 global clock signals routed 1533 connections routed (of 7109 total) (21.56%) --------------------------------------------------------- Clock routing summary: Primary clocks (12 used out of 64 available): Signal "jtck" (4, 20, 36, 52) Clock loads: 249 out of 249 routed (100.00%) Signal "top_reveal_coretop_instance.core0.reset_rvl_n" (0, 16, 32, 48) Control loads: 302 out of 302 routed (100.00%) Data loads: 0 out of 1 routed ( 0.00%) Signal "clk150" (3, 19, 35, 51) Clock loads: 335 out of 335 routed (100.00%) --------------------------------------------------------- -------------------------------------------------------------------------------- Completed routing resource preassignment Start NBR section for initial routing at 14:39:23 09/09/24 Level 4, iteration 1 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Routing in Serial Mode ...... +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 1493(0.03%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; Estimated worst slack/total negative slack<setup>: 2.801ns/0.000ns; real time: 14 secs Info: Initial congestion level at 75.00% usage is 0 Info: Initial congestion area at 75.00% usage is 8 (0.07%) Start NBR section for normal routing at 14:39:24 09/09/24 Level 4, iteration 1 1031(0.02%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; Estimated worst slack/total negative slack<setup>: 2.801ns/0.000ns; real time: 15 secs Level 4, iteration 2 508(0.01%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; Estimated worst slack/total negative slack<setup>: 2.801ns/0.000ns; real time: 15 secs Level 4, iteration 3 326(0.01%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; Estimated worst slack/total negative slack<setup>: 2.801ns/0.000ns; real time: 15 secs Level 4, iteration 4 204(0.00%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; Estimated worst slack/total negative slack<setup>: 2.801ns/0.000ns; real time: 16 secs Level 4, iteration 5 176(0.00%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; Estimated worst slack/total negative slack<setup>: 2.801ns/0.000ns; real time: 16 secs Level 4, iteration 6 113(0.00%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; Estimated worst slack/total negative slack<setup>: 2.801ns/0.000ns; real time: 16 secs Level 4, iteration 7 101(0.00%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; Estimated worst slack/total negative slack<setup>: 2.801ns/0.000ns; real time: 16 secs Level 4, iteration 8 54(0.00%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; Estimated worst slack/total negative slack<setup>: 2.801ns/0.000ns; real time: 16 secs Level 4, iteration 9 43(0.00%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; Estimated worst slack/total negative slack<setup>: 2.801ns/0.000ns; real time: 16 secs Level 4, iteration 10 26(0.00%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; Estimated worst slack/total negative slack<setup>: 2.801ns/0.000ns; real time: 16 secs Level 4, iteration 11 17(0.00%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; Estimated worst slack/total negative slack<setup>: 2.801ns/0.000ns; real time: 17 secs Level 4, iteration 12 7(0.00%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; Estimated worst slack/total negative slack<setup>: 2.801ns/0.000ns; real time: 17 secs Level 4, iteration 13 6(0.00%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; Estimated worst slack/total negative slack<setup>: 2.801ns/0.000ns; real time: 17 secs Level 4, iteration 14 3(0.00%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; Estimated worst slack/total negative slack<setup>: 2.801ns/0.000ns; real time: 17 secs Level 4, iteration 15 3(0.00%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; Estimated worst slack/total negative slack<setup>: 2.801ns/0.000ns; real time: 17 secs Level 4, iteration 16 2(0.00%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; Estimated worst slack/total negative slack<setup>: 2.801ns/0.000ns; real time: 17 secs Level 4, iteration 17 0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; Estimated worst slack/total negative slack<setup>: 2.801ns/0.000ns; real time: 17 secs Start NBR section for setup/hold timing optimization with effort level 3 at 14:39:27 09/09/24 Start NBR section for post-routing at 14:39:28 09/09/24 End NBR router with 0 unrouted connection(s) Checksum -- route: 3a5da016eb404dbca7a20af02f1f1fb11adc1931 Total CPU time 18 secs Total REAL time: 19 secs Completely routed. End of route. 7109 routed (100.00%); 0 unrouted. Writing design to file LAB04_Async_rst_par.dir/5_1.udb ... All signals are completely routed. PAR_SUMMARY::Run status = Completed PAR_SUMMARY::Number of unrouted conns = 0 PAR_SUMMARY::Estimated worst slack<setup/<ns>> = 2.801 PAR_SUMMARY::Timing score<setup/<ns>> = 0.000 PAR_SUMMARY::Estimated worst slack<hold/<ns>> = 0.167 PAR_SUMMARY::Timing score<hold/<ns>> = 0.000 PAR_SUMMARY::Number of errors = 0 Note: user must run 'timing' for timing closure signoff. Total CPU Time: 30 secs Total REAL Time: 31 secs Peak Memory Usage: 1251.25 MB par done! Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2024 Lattice Semiconductor Corporation, All rights reserved.