Project Settings |
---|
Project Name | proj_1 | Device Name | Async_rst: Lattice LFCPNX : LFCPNX_100 |
Implementation Name | Async_rst | Top Module | Top |
Pipelining | 1 | Retiming | 0 |
Resource Sharing | 1 | Fanout Guide | 1000 |
Disable I/O Insertion | 0 | Disable Sequential Optimizations | 0 |
Clock Conversion | 0 | FSM Compiler | 1 |
Run Status |
Job Name |
Status |
|
|
|
CPU Time |
Real Time |
Memory |
Date/Time |
(compiler) | Complete |
164 |
30 |
0 |
- |
00m:15s |
- |
9/5/2024 1:08 PM |
(premap) | Complete |
5 |
121 |
0 |
0m:04s |
0m:04s |
266MB |
9/5/2024 1:08 PM |
(fpga_mapper) | Complete |
8 |
203 |
0 |
0m:07s |
0m:07s |
285MB |
9/5/2024 1:08 PM |
Multi-srs Generator |
Complete | | | | 00m:02s | | | 9/5/2024 1:08 PM |
Area Summary |
|
Register bits | 946 |
I/O cells | 6 |
Block RAMs
(v_ram) | 2 |
DSPs
(dsp_used) | 0 |
LUTs
(total_luts) | 925 |
| |
Timing Summary |
|
Clock Name | Req Freq | Est Freq | Slack |
Top|clk150 | 1.0 MHz | 252.0 MHz | 996.033 |
Top|jtck_inferred_clock | 1.0 MHz | 178.0 MHz | 994.384 |
System | 1.0 MHz | 339.0 MHz | 997.050 |
Optimizations Summary |
Combined Clock Conversion | 2 / 0 |
| |
|