Project Settings
Project Name proj_1 Device Name Async_rst: Lattice LFCPNX : LFCPNX_100
Implementation Name Async_rst Top Module Top
Pipelining 1 Retiming 0
Resource Sharing 1 Fanout Guide 1000
Disable I/O Insertion 0 Disable Sequential Optimizations 0
Clock Conversion 0 FSM Compiler 1

Run Status
Job Name Status CPU Time Real Time Memory Date/Time
(compiler)Complete 167 30 0 - 00m:09s - 9/9/2024
2:38 PM
(premap)Complete 5 131 0 0m:02s 0m:02s 266MB 9/9/2024
2:38 PM
(fpga_mapper)Complete 11 203 0 0m:06s 0m:06s 288MB 9/9/2024
2:38 PM
Multi-srs Generator Complete00m:01s9/9/2024
2:38 PM

Area Summary
Register bits 962 I/O cells 6
Block RAMs (v_ram) 2 DSPs (dsp_used) 0
LUTs (total_luts) 974

Timing Summary
Clock NameReq FreqEst FreqSlack
Top|clk1501.0 MHz257.8 MHz996.121
Top|jtck_inferred_clock1.0 MHz182.3 MHz994.515
System1.0 MHz309.8 MHz996.772

Optimizations Summary
Combined Clock Conversion 2 / 0