Lattice Timing Report -  Setup  and Hold, Version Radiant Software (64-bit) 2024.1.0.34.2

Thu Sep  5 12:43:40 2024

Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp.   All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
Copyright (c) 2001 Agere Systems   All rights reserved.
Copyright (c) 2002-2024 Lattice Semiconductor Corporation,  All rights reserved.

Command line:    timing -sethld -v 10 -u 10 -endpoints 10 -nperend 1 -sp 9_High-Performance_1.0V -hsp m -pwrprd -html -rpt LAB01_Async_rst.twr LAB01_Async_rst.udb -gui -msgset C:/Users/qnoor/Downloads/LAB01_Async_rst/LAB01_Async_rst/promote.xml

-------------------------------------------
Design:          Top
Family:          LFCPNX
Device:          LFCPNX-100
Package:         LFG672
Performance:     9_High-Performance_1.0V
Package Status:                     Final          Version 16
Performance Hardware Data Status :   Final Version 3.9
-------------------------------------------


=====================================================================
                    Table of Contents
=====================================================================
    1  Timing Overview
        1.1  SDC Constraints
        1.2  Constraint Coverage
        1.3  Overall Summary
        1.4  Unconstrained Report
        1.5  Combinational Loop
    2  Setup at Speed Grade 9_High-Performance_1.0V Corner at 100 Degrees
        2.1  Clock Summary
        2.2  Endpoint slacks
        2.3  Detailed Report
    3  Setup at Speed Grade 9_High-Performance_1.0V Corner at -40 Degrees
        3.1  Clock Summary
        3.2  Endpoint slacks
        3.3  Detailed Report
    4  Hold at Speed Grade m Corner at -40 Degrees
        4.1  Endpoint slacks
        4.2  Detailed Report

=====================================================================
                    End of Table of Contents
=====================================================================

==============================================
1  Timing Overview
==============================================

1.1  SDC Constraints
=====================
create_clock -name {clk150} -period 8.88889 [get_pins {OSCA001.OSCA_inst/HFCLKOUT }] 
create_clock -name {rvltck} -period 33.33 [get_ports TCK]
set_false_path -to [get_clocks rvltck]
set_false_path -from [get_clocks rvltck]
create_generated_clock -name {rvjtck} -source [get_ports TCK] [get_nets jtck]
set_false_path -to [get_clocks rvjtck]
set_false_path -from [get_clocks rvjtck]
set_clock_groups -group [get_clocks clk150] -group [get_clocks rvltck] -asynchronous

1.2  Constraint Coverage
---------------------------
Constraint Coverage: 99.1309%


1.3  Overall Summary
---------------------------
 Setup at Speed Grade 9_High-Performance_1.0V Corner at 100 Degrees   Timing Errors: 0 endpoints;  Total Negative Slack: 0.000 ns 
 Setup at Speed Grade 9_High-Performance_1.0V Corner at -40 Degrees   Timing Errors: 0 endpoints;  Total Negative Slack: 0.000 ns 
 Hold at Speed Grade m Corner at -40 Degrees                          Timing Errors: 0 endpoints;  Total Negative Slack: 0.000 ns 

1.4  Unconstrained Report
===========================

1.4.1  Unconstrained Start/End Points
--------------------------------------

Clocked but unconstrained timing start points
-------------------------------------------------------------------
         Listing 4 Start Points         |           Type           
-------------------------------------------------------------------
LED4_0io.PIC_inst/Q                     |          No required time
LED3_0io.PIC_inst/Q                     |          No required time
LED2_0io.PIC_inst/Q                     |          No required time
LED1_0io.PIC_inst/Q                     |          No required time
-------------------------------------------------------------------
                                        |                          
Number of unconstrained timing start po |                          
ints                                    |                         4
                                        |                          
-------------------------------------------------------------------

Clocked but unconstrained timing end points
-------------------------------------------------------------------
         Listing 10 End Points          |           Type           
-------------------------------------------------------------------
CNT01/Couti_reg[15].ff_inst/LSR         |           No arrival time
{CNT01/Couti_reg[13].ff_inst/LSR   CNT01/Couti_reg[14].ff_inst/LSR}                           
                                        |           No arrival time
{CNT01/Couti_reg[11].ff_inst/LSR   CNT01/Couti_reg[12].ff_inst/LSR}                           
                                        |           No arrival time
{CNT01/Couti_reg[9].ff_inst/LSR   CNT01/Couti_reg[10].ff_inst/LSR}                           
                                        |           No arrival time
{CNT01/Couti_reg[7].ff_inst/LSR   CNT01/Couti_reg[8].ff_inst/LSR}                           
                                        |           No arrival time
{CNT01/Couti_reg[5].ff_inst/LSR   CNT01/Couti_reg[6].ff_inst/LSR}                           
                                        |           No arrival time
{CNT01/Couti_reg[3].ff_inst/LSR   CNT01/Couti_reg[4].ff_inst/LSR}                           
                                        |           No arrival time
{CNT01/Couti_reg[1].ff_inst/LSR   CNT01/Couti_reg[2].ff_inst/LSR}                           
                                        |           No arrival time
CNT01/Couti_reg[0].ff_inst/LSR          |           No arrival time
CNT02/Couti_reg[15].ff_inst/LSR         |           No arrival time
-------------------------------------------------------------------
                                        |                          
Number of unconstrained timing end poin |                          
ts                                      |                        38
                                        |                          
-------------------------------------------------------------------

1.4.2  Start/End Points Without Timing Constraints
---------------------------------------------------

I/O ports without constraint
----------------------------
Possible constraints to use on I/O ports are:
set_input_delay,
set_output_delay,
set_max_delay,
create_clock,
create_generated_clock,
...

-------------------------------------------------------------------
     Listing 6 Start or End Points      |           Type           
-------------------------------------------------------------------
en                                      |                     input
reset                                   |                     input
LED4                                    |                    output
LED3                                    |                    output
LED2                                    |                    output
LED1                                    |                    output
-------------------------------------------------------------------
                                        |                          
Number of I/O ports without constraint  |                         6
                                        |                          
-------------------------------------------------------------------

Nets without clock definition
Define a clock on a top level port or a generated clock on a clock divider pin associated with this net(s).
--------------------------------------------------
There is no instance satisfying reporting criteria



1.5  Combinational Loop
========================
None

===============================================================
2  Setup at Speed Grade 9_High-Performance_1.0V Corner at 100 Degrees
===============================================================

2.1  Clock Summary
=======================

2.1.1 Clock "clk150"
=======================
create_clock -name {clk150} -period 8.88889 [get_pins {OSCA001.OSCA_inst/HFCLKOUT }] 

Single Clock Domain
-------------------------------------------------------------------------------------------------------
              Clock clk150              |                    |       Period       |     Frequency      
-------------------------------------------------------------------------------------------------------
 From clk150                            |             Target |           8.889 ns |        112.500 MHz 
                                        | Actual (all paths) |           5.962 ns |        167.729 MHz 
OSCA001.OSCA_inst/HFCLKOUT (MPW)        |   (50% duty cycle) |           4.358 ns |        229.463 MHz 
-------------------------------------------------------------------------------------------------------

Clock Domain Crossing
------------------------------------------------------------------------------------------------------
              Clock clk150              |   Worst Time Between Edges   |           Comment            
------------------------------------------------------------------------------------------------------
 From rvltck                            |                         ---- |                   False path 
 From rvjtck                            |                         ---- |                   False path 
------------------------------------------------------------------------------------------------------

2.1.2 Clock "rvltck"
=======================
create_clock -name {rvltck} -period 33.33 [get_ports TCK]

Single Clock Domain
-------------------------------------------------------------------------------------------------------
              Clock rvltck              |                    |       Period       |     Frequency      
-------------------------------------------------------------------------------------------------------
 From rvltck                            |             Target |          33.330 ns |         30.003 MHz 
                                        | Actual (all paths) |           5.000 ns |        200.000 MHz 
jtaghub_inst/IB_inst2.bb_inst/B (MPW)   |   (50% duty cycle) |           5.000 ns |        200.000 MHz 
-------------------------------------------------------------------------------------------------------

Clock Domain Crossing
------------------------------------------------------------------------------------------------------
              Clock rvltck              |   Worst Time Between Edges   |           Comment            
------------------------------------------------------------------------------------------------------
 From clk150                            |                         ---- |                   False path 
 From rvjtck                            |                         ---- |                   False path 
------------------------------------------------------------------------------------------------------

2.1.3 Clock "rvjtck"
=======================
create_generated_clock -name {rvjtck} -source [get_ports TCK] [get_nets jtck]

Single Clock Domain
-------------------------------------------------------------------------------------------------------
              Clock rvjtck              |                    |       Period       |     Frequency      
-------------------------------------------------------------------------------------------------------
 From rvjtck                            |             Target |          33.330 ns |         30.003 MHz 
                                        | Actual (all paths) |           2.920 ns |        342.466 MHz 
top_reveal_coretop_instance/core0/tm_u/secured_instance_1_105/secured_instance_0_65/CLKR (MPW)                                                                
                                        |   (50% duty cycle) |           2.920 ns |        342.466 MHz 
-------------------------------------------------------------------------------------------------------

Clock Domain Crossing
------------------------------------------------------------------------------------------------------
              Clock rvjtck              |   Worst Time Between Edges   |           Comment            
------------------------------------------------------------------------------------------------------
 From clk150                            |                         ---- |                   False path 
 From rvltck                            |                         ---- |                   False path 
------------------------------------------------------------------------------------------------------

2.2  Endpoint slacks
=======================
-------------------------------------------------------
          Listing 10 End Points          |    Slack    
-------------------------------------------------------
LED3_0io.PIC_inst/D                      |    2.927 ns 
LED1_0io.PIC_inst/D                      |    2.996 ns 
{top_reveal_coretop_instance/core0/trig_u/tu_1/secured_instance_13_154/CE   top_reveal_coretop_instance/core0/trig_u/tu_1/secured_instance_13_153/CE}              
                                         |    3.710 ns 
{top_reveal_coretop_instance/core0/trig_u/tu_1/secured_instance_13_148/CE   top_reveal_coretop_instance/core0/trig_u/tu_1/secured_instance_13_147/CE}              
                                         |    3.710 ns 
top_reveal_coretop_instance/core0/trig_u/tu_3/secured_instance_11_95/DF              
                                         |    3.740 ns 
{top_reveal_coretop_instance/core0/trig_u/tu_1/secured_instance_13_162/CE   top_reveal_coretop_instance/core0/trig_u/tu_1/secured_instance_13_161/CE}              
                                         |    3.823 ns 
{top_reveal_coretop_instance/core0/trig_u/tu_1/secured_instance_13_150/CE   top_reveal_coretop_instance/core0/trig_u/tu_1/secured_instance_13_149/CE}              
                                         |    3.823 ns 
{top_reveal_coretop_instance/core0/trig_u/tu_1/secured_instance_13_152/CE   top_reveal_coretop_instance/core0/trig_u/tu_1/secured_instance_13_151/CE}              
                                         |    3.823 ns 
{top_reveal_coretop_instance/core0/trig_u/tu_1/secured_instance_13_156/CE   top_reveal_coretop_instance/core0/trig_u/tu_1/secured_instance_13_155/CE}              
                                         |    3.823 ns 
{top_reveal_coretop_instance/core0/trig_u/tu_1/secured_instance_13_160/CE   top_reveal_coretop_instance/core0/trig_u/tu_1/secured_instance_13_159/CE}              
                                         |    3.835 ns 
-------------------------------------------------------
                                         |             
Setup # of endpoints with negative slack:|           0 
                                         |             
-------------------------------------------------------

2.3  Detailed Report
=======================


XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

Detail report of critical paths

XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
                    Detailed Report for timing paths 
 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++

 ++++Path 1  ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++

Path Begin       : CNT03/Couti_reg[15].ff_inst/Q  (SLICE_R61C11A)
Path End         : LED3_0io.PIC_inst/D  (SIOLOGIC_CORE_IOL_R31A)
Source Clock     : clk150 (R)
Destination Clock: clk150 (R)
Logic Level      : 2
Delay Ratio      : 90.9% (route), 9.1% (logic)
Clock Skew       : -0.084 ns 
Setup Constraint : 8.888 ns 
Common Path Skew : 0.027 ns 
Path Slack       : 2.926 ns  (Passed)


Source Clock Path
Name                                      Cell/Site Name            Delay Name        Incr      Arrival/Required Time  Fanout  
----------------------------------------  ------------------------  ----------------  --------  ---------------------  ------  
OSCA001.OSCA_inst/HFCLKOUT                OSC_CORE_OSC_CORE_R1C137  CLOCK LATENCY        0.000                  0.000  322     
top_reveal_coretop_instance/core0/tm_u/secured_instance_1_105/secured_signal_0_141
                                                                    NET DELAY            2.342                  2.342  322     
CNT03/Couti_reg[15].ff_inst/CLK                                     CLOCK PIN            0.000                  2.342  1       


Data Path
Name                                      Cell/Site Name            Delay Name        Incr      Arrival/Required Time  Fanout  
----------------------------------------  ------------------------  ----------------  --------  ---------------------  ------  
CNT03/Couti_reg[15].ff_inst/CLK->CNT03/Couti_reg[15].ff_inst/Q
                                          SLICE_R61C11A             REG_DEL              0.306                  2.648  4       
top_reveal_coretop_instance/core0/tm_u/secured_signal_1_57
                                                                    NET DELAY            3.360                  6.008  4       
LED3_1_cZ/B->LED3_1_cZ/Z                  SLICE_R38C112D            CTOF_DEL             0.206                  6.214  1       
LED3_1                                                              NET DELAY            1.743                  7.957  1       
LED3_0io.PIC_inst/D                                                 ENDPOINT             0.000                  7.957  1       


Destination Clock Path
Name                                      Cell/Site Name            Delay Name        Incr      Arrival/Required Time  Fanout  
----------------------------------------  ------------------------  ----------------  --------  ---------------------  ------  
                                                                    CONSTRAINT           0.000                  8.888  1       
OSCA001.OSCA_inst/HFCLKOUT                OSC_CORE_OSC_CORE_R1C137  CLOCK LATENCY        0.000                  8.888  322     
top_reveal_coretop_instance/core0/tm_u/secured_instance_1_105/secured_signal_0_141
                                                                    NET DELAY            2.258                 11.146  322     
LED3_0io.PIC_inst/CLK                                               CLOCK PIN            0.000                 11.146  1       
                                                                    Uncertainty       -(0.000)                 11.146  
                                                                    Common Path Skew     0.027                 11.173  
                                                                    Setup time        -(0.290)                 10.883  
----------------------------------------  ------------------------  ----------------  --------  ---------------------  ------  
Required Time                                                                                                  10.883  
Arrival Time                                                                                                 -(7.956)  
----------------------------------------  ------------------------  ----------------  --------  ---------------------  ------  
Path Slack  (Passed)                                                                                            2.926  




++++ Path 2 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 

Path Begin       : CNT01/Couti_reg[0].ff_inst/Q  (SLICE_R14C12A)
Path End         : LED1_0io.PIC_inst/D  (SIOLOGIC_CORE_IOL_R28B)
Source Clock     : clk150 (R)
Destination Clock: clk150 (R)
Logic Level      : 2
Delay Ratio      : 91.0% (route), 9.0% (logic)
Clock Skew       : -0.084 ns 
Setup Constraint : 8.888 ns 
Common Path Skew : 0.027 ns 
Path Slack       : 2.995 ns  (Passed)


Source Clock Path
Name                                      Cell/Site Name            Delay Name        Incr      Arrival/Required Time  Fanout  
----------------------------------------  ------------------------  ----------------  --------  ---------------------  ------  
OSCA001.OSCA_inst/HFCLKOUT                OSC_CORE_OSC_CORE_R1C137  CLOCK LATENCY        0.000                  0.000  322     
top_reveal_coretop_instance/core0/tm_u/secured_instance_1_105/secured_signal_0_141
                                                                    NET DELAY            2.342                  2.342  322     
CNT01/Couti_reg[0].ff_inst/CLK                                      CLOCK PIN            0.000                  2.342  1       


Data Path
Name                                      Cell/Site Name            Delay Name        Incr      Arrival/Required Time  Fanout  
----------------------------------------  ------------------------  ----------------  --------  ---------------------  ------  
CNT01/Couti_reg[0].ff_inst/CLK->CNT01/Couti_reg[0].ff_inst/Q
                                          SLICE_R14C12A             REG_DEL              0.295                  2.637  4       
top_reveal_coretop_instance/core0/tm_u/secured_signal_1_40
                                                                    NET DELAY            3.373                  6.010  4       
LED1_1_cZ/A->LED1_1_cZ/Z                  SLICE_R38C117D            CTOF_DEL             0.206                  6.216  1       
LED1_1                                                              NET DELAY            1.672                  7.888  1       
LED1_0io.PIC_inst/D                                                 ENDPOINT             0.000                  7.888  1       


Destination Clock Path
Name                                      Cell/Site Name            Delay Name        Incr      Arrival/Required Time  Fanout  
----------------------------------------  ------------------------  ----------------  --------  ---------------------  ------  
                                                                    CONSTRAINT           0.000                  8.888  1       
OSCA001.OSCA_inst/HFCLKOUT                OSC_CORE_OSC_CORE_R1C137  CLOCK LATENCY        0.000                  8.888  322     
top_reveal_coretop_instance/core0/tm_u/secured_instance_1_105/secured_signal_0_141
                                                                    NET DELAY            2.258                 11.146  322     
LED1_0io.PIC_inst/CLK                                               CLOCK PIN            0.000                 11.146  1       
                                                                    Uncertainty       -(0.000)                 11.146  
                                                                    Common Path Skew     0.027                 11.173  
                                                                    Setup time        -(0.290)                 10.883  
----------------------------------------  ------------------------  ----------------  --------  ---------------------  ------  
Required Time                                                                                                  10.883  
Arrival Time                                                                                                 -(7.887)  
----------------------------------------  ------------------------  ----------------  --------  ---------------------  ------  
Path Slack  (Passed)                                                                                            2.995  




++++ Path 3 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 

Path Begin       : top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_469/Q  (SLICE_R44C108C)
Path End         : {top_reveal_coretop_instance/core0/trig_u/tu_1/secured_instance_13_154/CE   top_reveal_coretop_instance/core0/trig_u/tu_1/secured_instance_13_153/CE}  (SLICE_R39C104C)
Source Clock     : clk150 (R)
Destination Clock: clk150 (R)
Logic Level      : 7
Delay Ratio      : 67.9% (route), 32.1% (logic)
Clock Skew       : -0.130 ns 
Setup Constraint : 8.888 ns 
Common Path Skew : 0.103 ns 
Path Slack       : 3.709 ns  (Passed)


Source Clock Path
Name                                      Cell/Site Name            Delay Name        Incr      Arrival/Required Time  Fanout  
----------------------------------------  ------------------------  ----------------  --------  ---------------------  ------  
OSCA001.OSCA_inst/HFCLKOUT                OSC_CORE_OSC_CORE_R1C137  CLOCK LATENCY        0.000                  0.000  322     
top_reveal_coretop_instance/core0/tm_u/secured_instance_1_105/secured_signal_0_141
                                                                    NET DELAY            2.342                  2.342  322     
{top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_469/CLK   top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_470/CLK}
                                                                    CLOCK PIN            0.000                  2.342  1       


Data Path
Name                                      Cell/Site Name            Delay Name        Incr      Arrival/Required Time  Fanout  
----------------------------------------  ------------------------  ----------------  --------  ---------------------  ------  
top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_469/CLK->top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_469/Q
                                          SLICE_R44C108C            REG_DEL              0.306                  2.648  5       
top_reveal_coretop_instance/core0/jtag_int_u/secured_signal_2_156
                                                                    NET DELAY            0.480                  3.128  5       
top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_280/A->top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_280/Z
                                          SLICE_R45C107D            CTOF_DEL             0.214                  3.342  1       
top_reveal_coretop_instance/core0/jtag_int_u/secured_signal_2_594
                                                                    NET DELAY            0.232                  3.574  1       
top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_256/C->top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_256/Z
                                          SLICE_R45C109C            CTOF_DEL             0.214                  3.788  5       
top_reveal_coretop_instance/core0/tm_u/secured_signal_1_157
                                                                    NET DELAY            0.544                  4.332  5       
top_reveal_coretop_instance/core0/trig_u/decode_u/secured_instance_15_17/B->top_reveal_coretop_instance/core0/trig_u/decode_u/secured_instance_15_17/Z
                                          SLICE_R43C113A            CTOF_DEL             0.214                  4.546  3       
top_reveal_coretop_instance/core0/trig_u/decode_u/secured_signal_15_26
                                                                    NET DELAY            0.284                  4.830  3       
top_reveal_coretop_instance/core0/trig_u/decode_u/secured_instance_15_5/A->top_reveal_coretop_instance/core0/trig_u/decode_u/secured_instance_15_5/Z
                                          SLICE_R43C112A            CTOF_DEL             0.214                  5.044  4       
top_reveal_coretop_instance/core0/trig_u/decode_u/secured_signal_15_27
                                                                    NET DELAY            0.685                  5.729  4       
top_reveal_coretop_instance/core0/trig_u/decode_u/secured_instance_15_4/A->top_reveal_coretop_instance/core0/trig_u/decode_u/secured_instance_15_4/Z
                                          SLICE_R40C109A            CTOF_DEL             0.214                  5.943  3       
top_reveal_coretop_instance/core0/trig_u/tu_1/secured_signal_13_56
                                                                    NET DELAY            0.403                  6.346  3       
top_reveal_coretop_instance/core0/trig_u/tu_1/secured_instance_13_6/C->top_reveal_coretop_instance/core0/trig_u/tu_1/secured_instance_13_6/Z
                                          SLICE_R40C109A            CTOF_DEL             0.214                  6.560  8       
top_reveal_coretop_instance/core0/trig_u/tu_1/secured_signal_13_148
                                                                    NET DELAY            0.740                  7.300  8       
{top_reveal_coretop_instance/core0/trig_u/tu_1/secured_instance_13_154/CE   top_reveal_coretop_instance/core0/trig_u/tu_1/secured_instance_13_153/CE}
                                                                    ENDPOINT             0.000                  7.300  1       


Destination Clock Path
Name                                      Cell/Site Name            Delay Name        Incr      Arrival/Required Time  Fanout  
----------------------------------------  ------------------------  ----------------  --------  ---------------------  ------  
                                                                    CONSTRAINT           0.000                  8.888  1       
OSCA001.OSCA_inst/HFCLKOUT                OSC_CORE_OSC_CORE_R1C137  CLOCK LATENCY        0.000                  8.888  322     
top_reveal_coretop_instance/core0/tm_u/secured_instance_1_105/secured_signal_0_141
                                                                    NET DELAY            2.212                 11.100  322     
{top_reveal_coretop_instance/core0/trig_u/tu_1/secured_instance_13_154/CLK   top_reveal_coretop_instance/core0/trig_u/tu_1/secured_instance_13_153/CLK}
                                                                    CLOCK PIN            0.000                 11.100  1       
                                                                    Uncertainty       -(0.000)                 11.100  
                                                                    Common Path Skew     0.103                 11.203  
                                                                    Setup time        -(0.194)                 11.009  
----------------------------------------  ------------------------  ----------------  --------  ---------------------  ------  
Required Time                                                                                                  11.009  
Arrival Time                                                                                                 -(7.299)  
----------------------------------------  ------------------------  ----------------  --------  ---------------------  ------  
Path Slack  (Passed)                                                                                            3.709  




++++ Path 4 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 

Path Begin       : top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_469/Q  (SLICE_R44C108C)
Path End         : {top_reveal_coretop_instance/core0/trig_u/tu_1/secured_instance_13_148/CE   top_reveal_coretop_instance/core0/trig_u/tu_1/secured_instance_13_147/CE}  (SLICE_R39C104D)
Source Clock     : clk150 (R)
Destination Clock: clk150 (R)
Logic Level      : 7
Delay Ratio      : 67.9% (route), 32.1% (logic)
Clock Skew       : -0.130 ns 
Setup Constraint : 8.888 ns 
Common Path Skew : 0.103 ns 
Path Slack       : 3.709 ns  (Passed)


Source Clock Path
Name                                      Cell/Site Name            Delay Name        Incr      Arrival/Required Time  Fanout  
----------------------------------------  ------------------------  ----------------  --------  ---------------------  ------  
OSCA001.OSCA_inst/HFCLKOUT                OSC_CORE_OSC_CORE_R1C137  CLOCK LATENCY        0.000                  0.000  322     
top_reveal_coretop_instance/core0/tm_u/secured_instance_1_105/secured_signal_0_141
                                                                    NET DELAY            2.342                  2.342  322     
{top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_469/CLK   top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_470/CLK}
                                                                    CLOCK PIN            0.000                  2.342  1       


Data Path
Name                                      Cell/Site Name            Delay Name        Incr      Arrival/Required Time  Fanout  
----------------------------------------  ------------------------  ----------------  --------  ---------------------  ------  
top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_469/CLK->top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_469/Q
                                          SLICE_R44C108C            REG_DEL              0.306                  2.648  5       
top_reveal_coretop_instance/core0/jtag_int_u/secured_signal_2_156
                                                                    NET DELAY            0.480                  3.128  5       
top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_280/A->top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_280/Z
                                          SLICE_R45C107D            CTOF_DEL             0.214                  3.342  1       
top_reveal_coretop_instance/core0/jtag_int_u/secured_signal_2_594
                                                                    NET DELAY            0.232                  3.574  1       
top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_256/C->top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_256/Z
                                          SLICE_R45C109C            CTOF_DEL             0.214                  3.788  5       
top_reveal_coretop_instance/core0/tm_u/secured_signal_1_157
                                                                    NET DELAY            0.544                  4.332  5       
top_reveal_coretop_instance/core0/trig_u/decode_u/secured_instance_15_17/B->top_reveal_coretop_instance/core0/trig_u/decode_u/secured_instance_15_17/Z
                                          SLICE_R43C113A            CTOF_DEL             0.214                  4.546  3       
top_reveal_coretop_instance/core0/trig_u/decode_u/secured_signal_15_26
                                                                    NET DELAY            0.284                  4.830  3       
top_reveal_coretop_instance/core0/trig_u/decode_u/secured_instance_15_5/A->top_reveal_coretop_instance/core0/trig_u/decode_u/secured_instance_15_5/Z
                                          SLICE_R43C112A            CTOF_DEL             0.214                  5.044  4       
top_reveal_coretop_instance/core0/trig_u/decode_u/secured_signal_15_27
                                                                    NET DELAY            0.685                  5.729  4       
top_reveal_coretop_instance/core0/trig_u/decode_u/secured_instance_15_4/A->top_reveal_coretop_instance/core0/trig_u/decode_u/secured_instance_15_4/Z
                                          SLICE_R40C109A            CTOF_DEL             0.214                  5.943  3       
top_reveal_coretop_instance/core0/trig_u/tu_1/secured_signal_13_56
                                                                    NET DELAY            0.403                  6.346  3       
top_reveal_coretop_instance/core0/trig_u/tu_1/secured_instance_13_6/C->top_reveal_coretop_instance/core0/trig_u/tu_1/secured_instance_13_6/Z
                                          SLICE_R40C109A            CTOF_DEL             0.214                  6.560  8       
top_reveal_coretop_instance/core0/trig_u/tu_1/secured_signal_13_148
                                                                    NET DELAY            0.740                  7.300  8       
{top_reveal_coretop_instance/core0/trig_u/tu_1/secured_instance_13_148/CE   top_reveal_coretop_instance/core0/trig_u/tu_1/secured_instance_13_147/CE}
                                                                    ENDPOINT             0.000                  7.300  1       


Destination Clock Path
Name                                      Cell/Site Name            Delay Name        Incr      Arrival/Required Time  Fanout  
----------------------------------------  ------------------------  ----------------  --------  ---------------------  ------  
                                                                    CONSTRAINT           0.000                  8.888  1       
OSCA001.OSCA_inst/HFCLKOUT                OSC_CORE_OSC_CORE_R1C137  CLOCK LATENCY        0.000                  8.888  322     
top_reveal_coretop_instance/core0/tm_u/secured_instance_1_105/secured_signal_0_141
                                                                    NET DELAY            2.212                 11.100  322     
{top_reveal_coretop_instance/core0/trig_u/tu_1/secured_instance_13_148/CLK   top_reveal_coretop_instance/core0/trig_u/tu_1/secured_instance_13_147/CLK}
                                                                    CLOCK PIN            0.000                 11.100  1       
                                                                    Uncertainty       -(0.000)                 11.100  
                                                                    Common Path Skew     0.103                 11.203  
                                                                    Setup time        -(0.194)                 11.009  
----------------------------------------  ------------------------  ----------------  --------  ---------------------  ------  
Required Time                                                                                                  11.009  
Arrival Time                                                                                                 -(7.299)  
----------------------------------------  ------------------------  ----------------  --------  ---------------------  ------  
Path Slack  (Passed)                                                                                            3.709  




++++ Path 5 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 

Path Begin       : top_reveal_coretop_instance/core0/trig_u/tu_3/secured_instance_11_100/Q  (SLICE_R38C106A)
Path End         : top_reveal_coretop_instance/core0/trig_u/tu_3/secured_instance_11_95/DF  (SLICE_R43C109D)
Source Clock     : clk150 (R)
Destination Clock: clk150 (R)
Logic Level      : 11
Delay Ratio      : 57.5% (route), 42.5% (logic)
Clock Skew       : -0.130 ns 
Setup Constraint : 8.888 ns 
Common Path Skew : 0.103 ns 
Path Slack       : 3.739 ns  (Passed)


Source Clock Path
Name                                      Cell/Site Name            Delay Name        Incr       Arrival/Required Time  Fanout  
----------------------------------------  ------------------------  ----------------  ---------  ---------------------  ------  
OSCA001.OSCA_inst/HFCLKOUT                OSC_CORE_OSC_CORE_R1C137  CLOCK LATENCY         0.000                  0.000  322     
top_reveal_coretop_instance/core0/tm_u/secured_instance_1_105/secured_signal_0_141
                                                                    NET DELAY             2.342                  2.342  322     
{top_reveal_coretop_instance/core0/trig_u/tu_3/secured_instance_11_99/CLK   top_reveal_coretop_instance/core0/trig_u/tu_3/secured_instance_11_100/CLK}
                                                                    CLOCK PIN             0.000                  2.342  1       


Data Path
Name                                      Cell/Site Name            Delay Name        Incr       Arrival/Required Time  Fanout  
----------------------------------------  ------------------------  ----------------  ---------  ---------------------  ------  
top_reveal_coretop_instance/core0/trig_u/tu_3/secured_instance_11_100/CLK->top_reveal_coretop_instance/core0/trig_u/tu_3/secured_instance_11_100/Q
                                          SLICE_R38C106A            REG_DEL               0.309                  2.651  3       
top_reveal_coretop_instance/core0/trig_u/tu_3/secured_signal_11_88
                                                                    NET DELAY             0.680                  3.331  3       
top_reveal_coretop_instance/core0/trig_u/tu_3/secured_instance_11_59/B->top_reveal_coretop_instance/core0/trig_u/tu_3/secured_instance_11_59/Z
                                          SLICE_R35C113B            CTOF_DEL              0.214                  3.545  1       
top_reveal_coretop_instance/core0/trig_u/tu_3/secured_signal_11_191
                                                                    NET DELAY             0.419                  3.964  1       
top_reveal_coretop_instance/core0/trig_u/tu_3/secured_instance_11_60/D->top_reveal_coretop_instance/core0/trig_u/tu_3/secured_instance_11_60/Z
                                          SLICE_R35C113B            CTOF_DEL              0.214                  4.178  1       
top_reveal_coretop_instance/core0/trig_u/tu_3/secured_signal_11_162
                                                                    NET DELAY             0.528                  4.706  1       
top_reveal_coretop_instance/core0/trig_u/tu_3/secured_instance_11_79/A1->top_reveal_coretop_instance/core0/trig_u/tu_3/secured_instance_11_79/COUT
                                          SLICE_R30C114A            C1TOFCO_DEL           0.318                  5.024  1       
top_reveal_coretop_instance/core0/trig_u/tu_3/secured_signal_11_112
                                                                    NET DELAY             0.000                  5.024  1       
top_reveal_coretop_instance/core0/trig_u/tu_3/secured_instance_11_78/CIN->top_reveal_coretop_instance/core0/trig_u/tu_3/secured_instance_11_78/COUT
                                          SLICE_R30C114B            FCITOFCO_DEL          0.054                  5.078  1       
top_reveal_coretop_instance/core0/trig_u/tu_3/secured_signal_11_111
                                                                    NET DELAY             0.000                  5.078  1       
top_reveal_coretop_instance/core0/trig_u/tu_3/secured_instance_11_77/CIN->top_reveal_coretop_instance/core0/trig_u/tu_3/secured_instance_11_77/COUT
                                          SLICE_R30C114C            FCITOFCO_DEL          0.054                  5.132  1       
top_reveal_coretop_instance/core0/trig_u/tu_3/secured_signal_11_110
                                                                    NET DELAY             0.000                  5.132  1       
top_reveal_coretop_instance/core0/trig_u/tu_3/secured_instance_11_76/CIN->top_reveal_coretop_instance/core0/trig_u/tu_3/secured_instance_11_76/COUT
                                          SLICE_R30C114D            FCITOFCO_DEL          0.054                  5.186  1       
top_reveal_coretop_instance/core0/trig_u/tu_3/secured_signal_11_109
                                                                    NET DELAY             0.000                  5.186  1       
top_reveal_coretop_instance/core0/trig_u/tu_3/secured_instance_11_75/CIN->top_reveal_coretop_instance/core0/trig_u/tu_3/secured_instance_11_75/S1
                                          SLICE_R30C115A            FCITOF1_DEL           0.282                  5.468  3       
top_reveal_coretop_instance/core0/trig_u/tu_3/secured_signal_11_130
                                                                    NET DELAY             0.541                  6.009  3       
top_reveal_coretop_instance/core0/trig_u/tu_3/secured_instance_11_52/B->top_reveal_coretop_instance/core0/trig_u/tu_3/secured_instance_11_52/Z
                                          SLICE_R36C110B            CTOF_DEL              0.214                  6.223  1       
top_reveal_coretop_instance/core0/trig_u/tu_3/secured_signal_11_163
                                                                    NET DELAY             0.273                  6.496  1       
top_reveal_coretop_instance/core0/trig_u/tu_3/secured_instance_11_90/D->top_reveal_coretop_instance/core0/trig_u/tu_3/secured_instance_11_90/Z
                                          SLICE_R36C109C            CTOOF_DEL             0.275                  6.771  1       
top_reveal_coretop_instance/core0/trig_u/tu_3/secured_signal_11_165
                                                                    NET DELAY             0.537                  7.308  1       
top_reveal_coretop_instance/core0/trig_u/tu_3/secured_instance_11_58/B->top_reveal_coretop_instance/core0/trig_u/tu_3/secured_instance_11_58/Z
                                          SLICE_R43C109D            CTOF_DEL              0.214                  7.522  1       
top_reveal_coretop_instance/core0/trig_u/tu_3/secured_signal_11_150
                                                                    NET DELAY             0.000                  7.522  1       
top_reveal_coretop_instance/core0/trig_u/tu_3/secured_instance_11_95/DF
                                                                    ENDPOINT              0.000                  7.522  1       


Destination Clock Path
Name                                      Cell/Site Name            Delay Name        Incr       Arrival/Required Time  Fanout  
----------------------------------------  ------------------------  ----------------  ---------  ---------------------  ------  
                                                                    CONSTRAINT            0.000                  8.888  1       
OSCA001.OSCA_inst/HFCLKOUT                OSC_CORE_OSC_CORE_R1C137  CLOCK LATENCY         0.000                  8.888  322     
top_reveal_coretop_instance/core0/tm_u/secured_instance_1_105/secured_signal_0_141
                                                                    NET DELAY             2.212                 11.100  322     
{top_reveal_coretop_instance/core0/trig_u/tu_3/secured_instance_11_95/CLK   top_reveal_coretop_instance/core0/trig_u/tu_2/secured_instance_12_95/CLK}
                                                                    CLOCK PIN             0.000                 11.100  1       
                                                                    Uncertainty        -(0.000)                 11.100  
                                                                    Common Path Skew      0.103                 11.203  
                                                                    Setup time        -(-0.058)                 11.261  
----------------------------------------  ------------------------  ----------------  ---------  ---------------------  ------  
Required Time                                                                                                   11.261  
Arrival Time                                                                                                  -(7.521)  
----------------------------------------  ------------------------  ----------------  ---------  ---------------------  ------  
Path Slack  (Passed)                                                                                             3.739  




++++ Path 6 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 

Path Begin       : top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_469/Q  (SLICE_R44C108C)
Path End         : {top_reveal_coretop_instance/core0/trig_u/tu_1/secured_instance_13_162/CE   top_reveal_coretop_instance/core0/trig_u/tu_1/secured_instance_13_161/CE}  (SLICE_R38C106C)
Source Clock     : clk150 (R)
Destination Clock: clk150 (R)
Logic Level      : 7
Delay Ratio      : 67.2% (route), 32.8% (logic)
Clock Skew       : -0.130 ns 
Setup Constraint : 8.888 ns 
Common Path Skew : 0.103 ns 
Path Slack       : 3.822 ns  (Passed)


Source Clock Path
Name                                      Cell/Site Name            Delay Name        Incr      Arrival/Required Time  Fanout  
----------------------------------------  ------------------------  ----------------  --------  ---------------------  ------  
OSCA001.OSCA_inst/HFCLKOUT                OSC_CORE_OSC_CORE_R1C137  CLOCK LATENCY        0.000                  0.000  322     
top_reveal_coretop_instance/core0/tm_u/secured_instance_1_105/secured_signal_0_141
                                                                    NET DELAY            2.342                  2.342  322     
{top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_469/CLK   top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_470/CLK}
                                                                    CLOCK PIN            0.000                  2.342  1       


Data Path
Name                                      Cell/Site Name            Delay Name        Incr      Arrival/Required Time  Fanout  
----------------------------------------  ------------------------  ----------------  --------  ---------------------  ------  
top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_469/CLK->top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_469/Q
                                          SLICE_R44C108C            REG_DEL              0.306                  2.648  5       
top_reveal_coretop_instance/core0/jtag_int_u/secured_signal_2_156
                                                                    NET DELAY            0.480                  3.128  5       
top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_280/A->top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_280/Z
                                          SLICE_R45C107D            CTOF_DEL             0.214                  3.342  1       
top_reveal_coretop_instance/core0/jtag_int_u/secured_signal_2_594
                                                                    NET DELAY            0.232                  3.574  1       
top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_256/C->top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_256/Z
                                          SLICE_R45C109C            CTOF_DEL             0.214                  3.788  5       
top_reveal_coretop_instance/core0/tm_u/secured_signal_1_157
                                                                    NET DELAY            0.544                  4.332  5       
top_reveal_coretop_instance/core0/trig_u/decode_u/secured_instance_15_17/B->top_reveal_coretop_instance/core0/trig_u/decode_u/secured_instance_15_17/Z
                                          SLICE_R43C113A            CTOF_DEL             0.214                  4.546  3       
top_reveal_coretop_instance/core0/trig_u/decode_u/secured_signal_15_26
                                                                    NET DELAY            0.284                  4.830  3       
top_reveal_coretop_instance/core0/trig_u/decode_u/secured_instance_15_5/A->top_reveal_coretop_instance/core0/trig_u/decode_u/secured_instance_15_5/Z
                                          SLICE_R43C112A            CTOF_DEL             0.214                  5.044  4       
top_reveal_coretop_instance/core0/trig_u/decode_u/secured_signal_15_27
                                                                    NET DELAY            0.685                  5.729  4       
top_reveal_coretop_instance/core0/trig_u/decode_u/secured_instance_15_4/A->top_reveal_coretop_instance/core0/trig_u/decode_u/secured_instance_15_4/Z
                                          SLICE_R40C109A            CTOF_DEL             0.214                  5.943  3       
top_reveal_coretop_instance/core0/trig_u/tu_1/secured_signal_13_56
                                                                    NET DELAY            0.403                  6.346  3       
top_reveal_coretop_instance/core0/trig_u/tu_1/secured_instance_13_6/C->top_reveal_coretop_instance/core0/trig_u/tu_1/secured_instance_13_6/Z
                                          SLICE_R40C109A            CTOF_DEL             0.214                  6.560  8       
top_reveal_coretop_instance/core0/trig_u/tu_1/secured_signal_13_148
                                                                    NET DELAY            0.627                  7.187  8       
{top_reveal_coretop_instance/core0/trig_u/tu_1/secured_instance_13_162/CE   top_reveal_coretop_instance/core0/trig_u/tu_1/secured_instance_13_161/CE}
                                                                    ENDPOINT             0.000                  7.187  1       


Destination Clock Path
Name                                      Cell/Site Name            Delay Name        Incr      Arrival/Required Time  Fanout  
----------------------------------------  ------------------------  ----------------  --------  ---------------------  ------  
                                                                    CONSTRAINT           0.000                  8.888  1       
OSCA001.OSCA_inst/HFCLKOUT                OSC_CORE_OSC_CORE_R1C137  CLOCK LATENCY        0.000                  8.888  322     
top_reveal_coretop_instance/core0/tm_u/secured_instance_1_105/secured_signal_0_141
                                                                    NET DELAY            2.212                 11.100  322     
{top_reveal_coretop_instance/core0/trig_u/tu_1/secured_instance_13_162/CLK   top_reveal_coretop_instance/core0/trig_u/tu_1/secured_instance_13_161/CLK}
                                                                    CLOCK PIN            0.000                 11.100  1       
                                                                    Uncertainty       -(0.000)                 11.100  
                                                                    Common Path Skew     0.103                 11.203  
                                                                    Setup time        -(0.194)                 11.009  
----------------------------------------  ------------------------  ----------------  --------  ---------------------  ------  
Required Time                                                                                                  11.009  
Arrival Time                                                                                                 -(7.186)  
----------------------------------------  ------------------------  ----------------  --------  ---------------------  ------  
Path Slack  (Passed)                                                                                            3.822  




++++ Path 7 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 

Path Begin       : top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_469/Q  (SLICE_R44C108C)
Path End         : {top_reveal_coretop_instance/core0/trig_u/tu_1/secured_instance_13_150/CE   top_reveal_coretop_instance/core0/trig_u/tu_1/secured_instance_13_149/CE}  (SLICE_R39C106C)
Source Clock     : clk150 (R)
Destination Clock: clk150 (R)
Logic Level      : 7
Delay Ratio      : 67.2% (route), 32.8% (logic)
Clock Skew       : -0.130 ns 
Setup Constraint : 8.888 ns 
Common Path Skew : 0.103 ns 
Path Slack       : 3.822 ns  (Passed)


Source Clock Path
Name                                      Cell/Site Name            Delay Name        Incr      Arrival/Required Time  Fanout  
----------------------------------------  ------------------------  ----------------  --------  ---------------------  ------  
OSCA001.OSCA_inst/HFCLKOUT                OSC_CORE_OSC_CORE_R1C137  CLOCK LATENCY        0.000                  0.000  322     
top_reveal_coretop_instance/core0/tm_u/secured_instance_1_105/secured_signal_0_141
                                                                    NET DELAY            2.342                  2.342  322     
{top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_469/CLK   top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_470/CLK}
                                                                    CLOCK PIN            0.000                  2.342  1       


Data Path
Name                                      Cell/Site Name            Delay Name        Incr      Arrival/Required Time  Fanout  
----------------------------------------  ------------------------  ----------------  --------  ---------------------  ------  
top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_469/CLK->top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_469/Q
                                          SLICE_R44C108C            REG_DEL              0.306                  2.648  5       
top_reveal_coretop_instance/core0/jtag_int_u/secured_signal_2_156
                                                                    NET DELAY            0.480                  3.128  5       
top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_280/A->top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_280/Z
                                          SLICE_R45C107D            CTOF_DEL             0.214                  3.342  1       
top_reveal_coretop_instance/core0/jtag_int_u/secured_signal_2_594
                                                                    NET DELAY            0.232                  3.574  1       
top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_256/C->top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_256/Z
                                          SLICE_R45C109C            CTOF_DEL             0.214                  3.788  5       
top_reveal_coretop_instance/core0/tm_u/secured_signal_1_157
                                                                    NET DELAY            0.544                  4.332  5       
top_reveal_coretop_instance/core0/trig_u/decode_u/secured_instance_15_17/B->top_reveal_coretop_instance/core0/trig_u/decode_u/secured_instance_15_17/Z
                                          SLICE_R43C113A            CTOF_DEL             0.214                  4.546  3       
top_reveal_coretop_instance/core0/trig_u/decode_u/secured_signal_15_26
                                                                    NET DELAY            0.284                  4.830  3       
top_reveal_coretop_instance/core0/trig_u/decode_u/secured_instance_15_5/A->top_reveal_coretop_instance/core0/trig_u/decode_u/secured_instance_15_5/Z
                                          SLICE_R43C112A            CTOF_DEL             0.214                  5.044  4       
top_reveal_coretop_instance/core0/trig_u/decode_u/secured_signal_15_27
                                                                    NET DELAY            0.685                  5.729  4       
top_reveal_coretop_instance/core0/trig_u/decode_u/secured_instance_15_4/A->top_reveal_coretop_instance/core0/trig_u/decode_u/secured_instance_15_4/Z
                                          SLICE_R40C109A            CTOF_DEL             0.214                  5.943  3       
top_reveal_coretop_instance/core0/trig_u/tu_1/secured_signal_13_56
                                                                    NET DELAY            0.403                  6.346  3       
top_reveal_coretop_instance/core0/trig_u/tu_1/secured_instance_13_6/C->top_reveal_coretop_instance/core0/trig_u/tu_1/secured_instance_13_6/Z
                                          SLICE_R40C109A            CTOF_DEL             0.214                  6.560  8       
top_reveal_coretop_instance/core0/trig_u/tu_1/secured_signal_13_148
                                                                    NET DELAY            0.627                  7.187  8       
{top_reveal_coretop_instance/core0/trig_u/tu_1/secured_instance_13_150/CE   top_reveal_coretop_instance/core0/trig_u/tu_1/secured_instance_13_149/CE}
                                                                    ENDPOINT             0.000                  7.187  1       


Destination Clock Path
Name                                      Cell/Site Name            Delay Name        Incr      Arrival/Required Time  Fanout  
----------------------------------------  ------------------------  ----------------  --------  ---------------------  ------  
                                                                    CONSTRAINT           0.000                  8.888  1       
OSCA001.OSCA_inst/HFCLKOUT                OSC_CORE_OSC_CORE_R1C137  CLOCK LATENCY        0.000                  8.888  322     
top_reveal_coretop_instance/core0/tm_u/secured_instance_1_105/secured_signal_0_141
                                                                    NET DELAY            2.212                 11.100  322     
{top_reveal_coretop_instance/core0/trig_u/tu_1/secured_instance_13_150/CLK   top_reveal_coretop_instance/core0/trig_u/tu_1/secured_instance_13_149/CLK}
                                                                    CLOCK PIN            0.000                 11.100  1       
                                                                    Uncertainty       -(0.000)                 11.100  
                                                                    Common Path Skew     0.103                 11.203  
                                                                    Setup time        -(0.194)                 11.009  
----------------------------------------  ------------------------  ----------------  --------  ---------------------  ------  
Required Time                                                                                                  11.009  
Arrival Time                                                                                                 -(7.186)  
----------------------------------------  ------------------------  ----------------  --------  ---------------------  ------  
Path Slack  (Passed)                                                                                            3.822  




++++ Path 8 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 

Path Begin       : top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_469/Q  (SLICE_R44C108C)
Path End         : {top_reveal_coretop_instance/core0/trig_u/tu_1/secured_instance_13_152/CE   top_reveal_coretop_instance/core0/trig_u/tu_1/secured_instance_13_151/CE}  (SLICE_R39C106D)
Source Clock     : clk150 (R)
Destination Clock: clk150 (R)
Logic Level      : 7
Delay Ratio      : 67.2% (route), 32.8% (logic)
Clock Skew       : -0.130 ns 
Setup Constraint : 8.888 ns 
Common Path Skew : 0.103 ns 
Path Slack       : 3.822 ns  (Passed)


Source Clock Path
Name                                      Cell/Site Name            Delay Name        Incr      Arrival/Required Time  Fanout  
----------------------------------------  ------------------------  ----------------  --------  ---------------------  ------  
OSCA001.OSCA_inst/HFCLKOUT                OSC_CORE_OSC_CORE_R1C137  CLOCK LATENCY        0.000                  0.000  322     
top_reveal_coretop_instance/core0/tm_u/secured_instance_1_105/secured_signal_0_141
                                                                    NET DELAY            2.342                  2.342  322     
{top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_469/CLK   top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_470/CLK}
                                                                    CLOCK PIN            0.000                  2.342  1       


Data Path
Name                                      Cell/Site Name            Delay Name        Incr      Arrival/Required Time  Fanout  
----------------------------------------  ------------------------  ----------------  --------  ---------------------  ------  
top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_469/CLK->top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_469/Q
                                          SLICE_R44C108C            REG_DEL              0.306                  2.648  5       
top_reveal_coretop_instance/core0/jtag_int_u/secured_signal_2_156
                                                                    NET DELAY            0.480                  3.128  5       
top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_280/A->top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_280/Z
                                          SLICE_R45C107D            CTOF_DEL             0.214                  3.342  1       
top_reveal_coretop_instance/core0/jtag_int_u/secured_signal_2_594
                                                                    NET DELAY            0.232                  3.574  1       
top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_256/C->top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_256/Z
                                          SLICE_R45C109C            CTOF_DEL             0.214                  3.788  5       
top_reveal_coretop_instance/core0/tm_u/secured_signal_1_157
                                                                    NET DELAY            0.544                  4.332  5       
top_reveal_coretop_instance/core0/trig_u/decode_u/secured_instance_15_17/B->top_reveal_coretop_instance/core0/trig_u/decode_u/secured_instance_15_17/Z
                                          SLICE_R43C113A            CTOF_DEL             0.214                  4.546  3       
top_reveal_coretop_instance/core0/trig_u/decode_u/secured_signal_15_26
                                                                    NET DELAY            0.284                  4.830  3       
top_reveal_coretop_instance/core0/trig_u/decode_u/secured_instance_15_5/A->top_reveal_coretop_instance/core0/trig_u/decode_u/secured_instance_15_5/Z
                                          SLICE_R43C112A            CTOF_DEL             0.214                  5.044  4       
top_reveal_coretop_instance/core0/trig_u/decode_u/secured_signal_15_27
                                                                    NET DELAY            0.685                  5.729  4       
top_reveal_coretop_instance/core0/trig_u/decode_u/secured_instance_15_4/A->top_reveal_coretop_instance/core0/trig_u/decode_u/secured_instance_15_4/Z
                                          SLICE_R40C109A            CTOF_DEL             0.214                  5.943  3       
top_reveal_coretop_instance/core0/trig_u/tu_1/secured_signal_13_56
                                                                    NET DELAY            0.403                  6.346  3       
top_reveal_coretop_instance/core0/trig_u/tu_1/secured_instance_13_6/C->top_reveal_coretop_instance/core0/trig_u/tu_1/secured_instance_13_6/Z
                                          SLICE_R40C109A            CTOF_DEL             0.214                  6.560  8       
top_reveal_coretop_instance/core0/trig_u/tu_1/secured_signal_13_148
                                                                    NET DELAY            0.627                  7.187  8       
{top_reveal_coretop_instance/core0/trig_u/tu_1/secured_instance_13_152/CE   top_reveal_coretop_instance/core0/trig_u/tu_1/secured_instance_13_151/CE}
                                                                    ENDPOINT             0.000                  7.187  1       


Destination Clock Path
Name                                      Cell/Site Name            Delay Name        Incr      Arrival/Required Time  Fanout  
----------------------------------------  ------------------------  ----------------  --------  ---------------------  ------  
                                                                    CONSTRAINT           0.000                  8.888  1       
OSCA001.OSCA_inst/HFCLKOUT                OSC_CORE_OSC_CORE_R1C137  CLOCK LATENCY        0.000                  8.888  322     
top_reveal_coretop_instance/core0/tm_u/secured_instance_1_105/secured_signal_0_141
                                                                    NET DELAY            2.212                 11.100  322     
{top_reveal_coretop_instance/core0/trig_u/tu_1/secured_instance_13_152/CLK   top_reveal_coretop_instance/core0/trig_u/tu_1/secured_instance_13_151/CLK}
                                                                    CLOCK PIN            0.000                 11.100  1       
                                                                    Uncertainty       -(0.000)                 11.100  
                                                                    Common Path Skew     0.103                 11.203  
                                                                    Setup time        -(0.194)                 11.009  
----------------------------------------  ------------------------  ----------------  --------  ---------------------  ------  
Required Time                                                                                                  11.009  
Arrival Time                                                                                                 -(7.186)  
----------------------------------------  ------------------------  ----------------  --------  ---------------------  ------  
Path Slack  (Passed)                                                                                            3.822  




++++ Path 9 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 

Path Begin       : top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_469/Q  (SLICE_R44C108C)
Path End         : {top_reveal_coretop_instance/core0/trig_u/tu_1/secured_instance_13_156/CE   top_reveal_coretop_instance/core0/trig_u/tu_1/secured_instance_13_155/CE}  (SLICE_R38C106D)
Source Clock     : clk150 (R)
Destination Clock: clk150 (R)
Logic Level      : 7
Delay Ratio      : 67.2% (route), 32.8% (logic)
Clock Skew       : -0.130 ns 
Setup Constraint : 8.888 ns 
Common Path Skew : 0.103 ns 
Path Slack       : 3.822 ns  (Passed)


Source Clock Path
Name                                      Cell/Site Name            Delay Name        Incr      Arrival/Required Time  Fanout  
----------------------------------------  ------------------------  ----------------  --------  ---------------------  ------  
OSCA001.OSCA_inst/HFCLKOUT                OSC_CORE_OSC_CORE_R1C137  CLOCK LATENCY        0.000                  0.000  322     
top_reveal_coretop_instance/core0/tm_u/secured_instance_1_105/secured_signal_0_141
                                                                    NET DELAY            2.342                  2.342  322     
{top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_469/CLK   top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_470/CLK}
                                                                    CLOCK PIN            0.000                  2.342  1       


Data Path
Name                                      Cell/Site Name            Delay Name        Incr      Arrival/Required Time  Fanout  
----------------------------------------  ------------------------  ----------------  --------  ---------------------  ------  
top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_469/CLK->top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_469/Q
                                          SLICE_R44C108C            REG_DEL              0.306                  2.648  5       
top_reveal_coretop_instance/core0/jtag_int_u/secured_signal_2_156
                                                                    NET DELAY            0.480                  3.128  5       
top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_280/A->top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_280/Z
                                          SLICE_R45C107D            CTOF_DEL             0.214                  3.342  1       
top_reveal_coretop_instance/core0/jtag_int_u/secured_signal_2_594
                                                                    NET DELAY            0.232                  3.574  1       
top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_256/C->top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_256/Z
                                          SLICE_R45C109C            CTOF_DEL             0.214                  3.788  5       
top_reveal_coretop_instance/core0/tm_u/secured_signal_1_157
                                                                    NET DELAY            0.544                  4.332  5       
top_reveal_coretop_instance/core0/trig_u/decode_u/secured_instance_15_17/B->top_reveal_coretop_instance/core0/trig_u/decode_u/secured_instance_15_17/Z
                                          SLICE_R43C113A            CTOF_DEL             0.214                  4.546  3       
top_reveal_coretop_instance/core0/trig_u/decode_u/secured_signal_15_26
                                                                    NET DELAY            0.284                  4.830  3       
top_reveal_coretop_instance/core0/trig_u/decode_u/secured_instance_15_5/A->top_reveal_coretop_instance/core0/trig_u/decode_u/secured_instance_15_5/Z
                                          SLICE_R43C112A            CTOF_DEL             0.214                  5.044  4       
top_reveal_coretop_instance/core0/trig_u/decode_u/secured_signal_15_27
                                                                    NET DELAY            0.685                  5.729  4       
top_reveal_coretop_instance/core0/trig_u/decode_u/secured_instance_15_4/A->top_reveal_coretop_instance/core0/trig_u/decode_u/secured_instance_15_4/Z
                                          SLICE_R40C109A            CTOF_DEL             0.214                  5.943  3       
top_reveal_coretop_instance/core0/trig_u/tu_1/secured_signal_13_56
                                                                    NET DELAY            0.403                  6.346  3       
top_reveal_coretop_instance/core0/trig_u/tu_1/secured_instance_13_6/C->top_reveal_coretop_instance/core0/trig_u/tu_1/secured_instance_13_6/Z
                                          SLICE_R40C109A            CTOF_DEL             0.214                  6.560  8       
top_reveal_coretop_instance/core0/trig_u/tu_1/secured_signal_13_148
                                                                    NET DELAY            0.627                  7.187  8       
{top_reveal_coretop_instance/core0/trig_u/tu_1/secured_instance_13_156/CE   top_reveal_coretop_instance/core0/trig_u/tu_1/secured_instance_13_155/CE}
                                                                    ENDPOINT             0.000                  7.187  1       


Destination Clock Path
Name                                      Cell/Site Name            Delay Name        Incr      Arrival/Required Time  Fanout  
----------------------------------------  ------------------------  ----------------  --------  ---------------------  ------  
                                                                    CONSTRAINT           0.000                  8.888  1       
OSCA001.OSCA_inst/HFCLKOUT                OSC_CORE_OSC_CORE_R1C137  CLOCK LATENCY        0.000                  8.888  322     
top_reveal_coretop_instance/core0/tm_u/secured_instance_1_105/secured_signal_0_141
                                                                    NET DELAY            2.212                 11.100  322     
{top_reveal_coretop_instance/core0/trig_u/tu_1/secured_instance_13_156/CLK   top_reveal_coretop_instance/core0/trig_u/tu_1/secured_instance_13_155/CLK}
                                                                    CLOCK PIN            0.000                 11.100  1       
                                                                    Uncertainty       -(0.000)                 11.100  
                                                                    Common Path Skew     0.103                 11.203  
                                                                    Setup time        -(0.194)                 11.009  
----------------------------------------  ------------------------  ----------------  --------  ---------------------  ------  
Required Time                                                                                                  11.009  
Arrival Time                                                                                                 -(7.186)  
----------------------------------------  ------------------------  ----------------  --------  ---------------------  ------  
Path Slack  (Passed)                                                                                            3.822  




++++ Path 10 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 

Path Begin       : top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_469/Q  (SLICE_R44C108C)
Path End         : {top_reveal_coretop_instance/core0/trig_u/tu_1/secured_instance_13_160/CE   top_reveal_coretop_instance/core0/trig_u/tu_1/secured_instance_13_159/CE}  (SLICE_R38C107D)
Source Clock     : clk150 (R)
Destination Clock: clk150 (R)
Logic Level      : 7
Delay Ratio      : 67.1% (route), 32.9% (logic)
Clock Skew       : -0.130 ns 
Setup Constraint : 8.888 ns 
Common Path Skew : 0.103 ns 
Path Slack       : 3.834 ns  (Passed)


Source Clock Path
Name                                      Cell/Site Name            Delay Name        Incr      Arrival/Required Time  Fanout  
----------------------------------------  ------------------------  ----------------  --------  ---------------------  ------  
OSCA001.OSCA_inst/HFCLKOUT                OSC_CORE_OSC_CORE_R1C137  CLOCK LATENCY        0.000                  0.000  322     
top_reveal_coretop_instance/core0/tm_u/secured_instance_1_105/secured_signal_0_141
                                                                    NET DELAY            2.342                  2.342  322     
{top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_469/CLK   top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_470/CLK}
                                                                    CLOCK PIN            0.000                  2.342  1       


Data Path
Name                                      Cell/Site Name            Delay Name        Incr      Arrival/Required Time  Fanout  
----------------------------------------  ------------------------  ----------------  --------  ---------------------  ------  
top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_469/CLK->top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_469/Q
                                          SLICE_R44C108C            REG_DEL              0.306                  2.648  5       
top_reveal_coretop_instance/core0/jtag_int_u/secured_signal_2_156
                                                                    NET DELAY            0.480                  3.128  5       
top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_280/A->top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_280/Z
                                          SLICE_R45C107D            CTOF_DEL             0.214                  3.342  1       
top_reveal_coretop_instance/core0/jtag_int_u/secured_signal_2_594
                                                                    NET DELAY            0.232                  3.574  1       
top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_256/C->top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_256/Z
                                          SLICE_R45C109C            CTOF_DEL             0.214                  3.788  5       
top_reveal_coretop_instance/core0/tm_u/secured_signal_1_157
                                                                    NET DELAY            0.544                  4.332  5       
top_reveal_coretop_instance/core0/trig_u/decode_u/secured_instance_15_17/B->top_reveal_coretop_instance/core0/trig_u/decode_u/secured_instance_15_17/Z
                                          SLICE_R43C113A            CTOF_DEL             0.214                  4.546  3       
top_reveal_coretop_instance/core0/trig_u/decode_u/secured_signal_15_26
                                                                    NET DELAY            0.284                  4.830  3       
top_reveal_coretop_instance/core0/trig_u/decode_u/secured_instance_15_5/A->top_reveal_coretop_instance/core0/trig_u/decode_u/secured_instance_15_5/Z
                                          SLICE_R43C112A            CTOF_DEL             0.214                  5.044  4       
top_reveal_coretop_instance/core0/trig_u/decode_u/secured_signal_15_27
                                                                    NET DELAY            0.685                  5.729  4       
top_reveal_coretop_instance/core0/trig_u/decode_u/secured_instance_15_4/A->top_reveal_coretop_instance/core0/trig_u/decode_u/secured_instance_15_4/Z
                                          SLICE_R40C109A            CTOF_DEL             0.214                  5.943  3       
top_reveal_coretop_instance/core0/trig_u/tu_1/secured_signal_13_56
                                                                    NET DELAY            0.403                  6.346  3       
top_reveal_coretop_instance/core0/trig_u/tu_1/secured_instance_13_6/C->top_reveal_coretop_instance/core0/trig_u/tu_1/secured_instance_13_6/Z
                                          SLICE_R40C109A            CTOF_DEL             0.214                  6.560  8       
top_reveal_coretop_instance/core0/trig_u/tu_1/secured_signal_13_148
                                                                    NET DELAY            0.615                  7.175  8       
{top_reveal_coretop_instance/core0/trig_u/tu_1/secured_instance_13_160/CE   top_reveal_coretop_instance/core0/trig_u/tu_1/secured_instance_13_159/CE}
                                                                    ENDPOINT             0.000                  7.175  1       


Destination Clock Path
Name                                      Cell/Site Name            Delay Name        Incr      Arrival/Required Time  Fanout  
----------------------------------------  ------------------------  ----------------  --------  ---------------------  ------  
                                                                    CONSTRAINT           0.000                  8.888  1       
OSCA001.OSCA_inst/HFCLKOUT                OSC_CORE_OSC_CORE_R1C137  CLOCK LATENCY        0.000                  8.888  322     
top_reveal_coretop_instance/core0/tm_u/secured_instance_1_105/secured_signal_0_141
                                                                    NET DELAY            2.212                 11.100  322     
{top_reveal_coretop_instance/core0/trig_u/tu_1/secured_instance_13_160/CLK   top_reveal_coretop_instance/core0/trig_u/tu_1/secured_instance_13_159/CLK}
                                                                    CLOCK PIN            0.000                 11.100  1       
                                                                    Uncertainty       -(0.000)                 11.100  
                                                                    Common Path Skew     0.103                 11.203  
                                                                    Setup time        -(0.194)                 11.009  
----------------------------------------  ------------------------  ----------------  --------  ---------------------  ------  
Required Time                                                                                                  11.009  
Arrival Time                                                                                                 -(7.174)  
----------------------------------------  ------------------------  ----------------  --------  ---------------------  ------  
Path Slack  (Passed)                                                                                            3.834  



+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 
                    End of Detailed Report for timing paths 
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 


##########################################################



===============================================================
3  Setup at Speed Grade 9_High-Performance_1.0V Corner at -40 Degrees
===============================================================

3.1  Clock Summary
=======================

3.1.1 Clock "clk150"
=======================
create_clock -name {clk150} -period 8.88889 [get_pins {OSCA001.OSCA_inst/HFCLKOUT }] 

Single Clock Domain
-------------------------------------------------------------------------------------------------------
              Clock clk150              |                    |       Period       |     Frequency      
-------------------------------------------------------------------------------------------------------
 From clk150                            |             Target |           8.889 ns |        112.500 MHz 
                                        | Actual (all paths) |           5.854 ns |        170.823 MHz 
OSCA001.OSCA_inst/HFCLKOUT (MPW)        |   (50% duty cycle) |           4.358 ns |        229.463 MHz 
-------------------------------------------------------------------------------------------------------

Clock Domain Crossing
------------------------------------------------------------------------------------------------------
              Clock clk150              |   Worst Time Between Edges   |           Comment            
------------------------------------------------------------------------------------------------------
 From rvltck                            |                         ---- |                   False path 
 From rvjtck                            |                         ---- |                   False path 
------------------------------------------------------------------------------------------------------

3.1.2 Clock "rvltck"
=======================
create_clock -name {rvltck} -period 33.33 [get_ports TCK]

Single Clock Domain
-------------------------------------------------------------------------------------------------------
              Clock rvltck              |                    |       Period       |     Frequency      
-------------------------------------------------------------------------------------------------------
 From rvltck                            |             Target |          33.330 ns |         30.003 MHz 
                                        | Actual (all paths) |           5.000 ns |        200.000 MHz 
jtaghub_inst/IB_inst2.bb_inst/B (MPW)   |   (50% duty cycle) |           5.000 ns |        200.000 MHz 
-------------------------------------------------------------------------------------------------------

Clock Domain Crossing
------------------------------------------------------------------------------------------------------
              Clock rvltck              |   Worst Time Between Edges   |           Comment            
------------------------------------------------------------------------------------------------------
 From clk150                            |                         ---- |                   False path 
 From rvjtck                            |                         ---- |                   False path 
------------------------------------------------------------------------------------------------------

3.1.3 Clock "rvjtck"
=======================
create_generated_clock -name {rvjtck} -source [get_ports TCK] [get_nets jtck]

Single Clock Domain
-------------------------------------------------------------------------------------------------------
              Clock rvjtck              |                    |       Period       |     Frequency      
-------------------------------------------------------------------------------------------------------
 From rvjtck                            |             Target |          33.330 ns |         30.003 MHz 
                                        | Actual (all paths) |           2.920 ns |        342.466 MHz 
top_reveal_coretop_instance/core0/tm_u/secured_instance_1_105/secured_instance_0_65/CLKR (MPW)                                                                
                                        |   (50% duty cycle) |           2.920 ns |        342.466 MHz 
-------------------------------------------------------------------------------------------------------

Clock Domain Crossing
------------------------------------------------------------------------------------------------------
              Clock rvjtck              |   Worst Time Between Edges   |           Comment            
------------------------------------------------------------------------------------------------------
 From clk150                            |                         ---- |                   False path 
 From rvltck                            |                         ---- |                   False path 
------------------------------------------------------------------------------------------------------

3.2  Endpoint slacks
=======================
-------------------------------------------------------
          Listing 10 End Points          |    Slack    
-------------------------------------------------------
LED3_0io.PIC_inst/D                      |    3.035 ns 
LED1_0io.PIC_inst/D                      |    3.094 ns 
top_reveal_coretop_instance/core0/trig_u/tu_3/secured_instance_11_95/DF              
                                         |    3.875 ns 
{top_reveal_coretop_instance/core0/trig_u/tu_1/secured_instance_13_154/CE   top_reveal_coretop_instance/core0/trig_u/tu_1/secured_instance_13_153/CE}              
                                         |    3.881 ns 
{top_reveal_coretop_instance/core0/trig_u/tu_1/secured_instance_13_148/CE   top_reveal_coretop_instance/core0/trig_u/tu_1/secured_instance_13_147/CE}              
                                         |    3.881 ns 
{top_reveal_coretop_instance/core0/trig_u/tu_1/secured_instance_13_162/CE   top_reveal_coretop_instance/core0/trig_u/tu_1/secured_instance_13_161/CE}              
                                         |    3.990 ns 
{top_reveal_coretop_instance/core0/trig_u/tu_1/secured_instance_13_150/CE   top_reveal_coretop_instance/core0/trig_u/tu_1/secured_instance_13_149/CE}              
                                         |    3.990 ns 
{top_reveal_coretop_instance/core0/trig_u/tu_1/secured_instance_13_152/CE   top_reveal_coretop_instance/core0/trig_u/tu_1/secured_instance_13_151/CE}              
                                         |    3.990 ns 
{top_reveal_coretop_instance/core0/trig_u/tu_1/secured_instance_13_156/CE   top_reveal_coretop_instance/core0/trig_u/tu_1/secured_instance_13_155/CE}              
                                         |    3.990 ns 
{top_reveal_coretop_instance/core0/trig_u/tu_1/secured_instance_13_160/CE   top_reveal_coretop_instance/core0/trig_u/tu_1/secured_instance_13_159/CE}              
                                         |    3.997 ns 
-------------------------------------------------------
                                         |             
Setup # of endpoints with negative slack:|           0 
                                         |             
-------------------------------------------------------

3.3  Detailed Report
=======================


XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

Detail report of critical paths

XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
                    Detailed Report for timing paths 
 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++

 ++++Path 1  ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++

Path Begin       : CNT03/Couti_reg[15].ff_inst/Q  (SLICE_R61C11A)
Path End         : LED3_0io.PIC_inst/D  (SIOLOGIC_CORE_IOL_R31A)
Source Clock     : clk150 (R)
Destination Clock: clk150 (R)
Logic Level      : 2
Delay Ratio      : 90.6% (route), 9.4% (logic)
Clock Skew       : -0.101 ns 
Setup Constraint : 8.888 ns 
Common Path Skew : 0.031 ns 
Path Slack       : 3.034 ns  (Passed)


Source Clock Path
Name                                      Cell/Site Name            Delay Name        Incr      Arrival/Required Time  Fanout  
----------------------------------------  ------------------------  ----------------  --------  ---------------------  ------  
OSCA001.OSCA_inst/HFCLKOUT                OSC_CORE_OSC_CORE_R1C137  CLOCK LATENCY        0.000                  0.000  323     
top_reveal_coretop_instance/core0/tm_u/secured_instance_1_105/secured_signal_0_141
                                                                    NET DELAY            2.654                  2.654  323     
CNT03/Couti_reg[15].ff_inst/CLK                                     CLOCK PIN            0.000                  2.654  1       


Data Path
Name                                      Cell/Site Name            Delay Name        Incr      Arrival/Required Time  Fanout  
----------------------------------------  ------------------------  ----------------  --------  ---------------------  ------  
CNT03/Couti_reg[15].ff_inst/CLK->CNT03/Couti_reg[15].ff_inst/Q
                                          SLICE_R61C11A             REG_DEL              0.301                  2.955  4       
top_reveal_coretop_instance/core0/tm_u/secured_signal_1_57
                                                                    NET DELAY            3.245                  6.200  4       
LED3_1_cZ/B->LED3_1_cZ/Z                  SLICE_R38C112D            CTOF_DEL             0.211                  6.411  1       
LED3_1                                                              NET DELAY            1.690                  8.101  1       
LED3_0io.PIC_inst/D                                                 ENDPOINT             0.000                  8.101  1       


Destination Clock Path
Name                                      Cell/Site Name            Delay Name        Incr      Arrival/Required Time  Fanout  
----------------------------------------  ------------------------  ----------------  --------  ---------------------  ------  
                                                                    CONSTRAINT           0.000                  8.888  1       
OSCA001.OSCA_inst/HFCLKOUT                OSC_CORE_OSC_CORE_R1C137  CLOCK LATENCY        0.000                  8.888  323     
top_reveal_coretop_instance/core0/tm_u/secured_instance_1_105/secured_signal_0_141
                                                                    NET DELAY            2.553                 11.441  323     
LED3_0io.PIC_inst/CLK                                               CLOCK PIN            0.000                 11.441  1       
                                                                    Uncertainty       -(0.000)                 11.441  
                                                                    Common Path Skew     0.031                 11.472  
                                                                    Setup time        -(0.337)                 11.135  
----------------------------------------  ------------------------  ----------------  --------  ---------------------  ------  
Required Time                                                                                                  11.135  
Arrival Time                                                                                                 -(8.100)  
----------------------------------------  ------------------------  ----------------  --------  ---------------------  ------  
Path Slack  (Passed)                                                                                            3.034  




++++ Path 2 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 

Path Begin       : CNT01/Couti_reg[0].ff_inst/Q  (SLICE_R14C12A)
Path End         : LED1_0io.PIC_inst/D  (SIOLOGIC_CORE_IOL_R28B)
Source Clock     : clk150 (R)
Destination Clock: clk150 (R)
Logic Level      : 2
Delay Ratio      : 90.5% (route), 9.5% (logic)
Clock Skew       : -0.101 ns 
Setup Constraint : 8.888 ns 
Common Path Skew : 0.031 ns 
Path Slack       : 3.093 ns  (Passed)


Source Clock Path
Name                                      Cell/Site Name            Delay Name        Incr      Arrival/Required Time  Fanout  
----------------------------------------  ------------------------  ----------------  --------  ---------------------  ------  
OSCA001.OSCA_inst/HFCLKOUT                OSC_CORE_OSC_CORE_R1C137  CLOCK LATENCY        0.000                  0.000  323     
top_reveal_coretop_instance/core0/tm_u/secured_instance_1_105/secured_signal_0_141
                                                                    NET DELAY            2.654                  2.654  323     
CNT01/Couti_reg[0].ff_inst/CLK                                      CLOCK PIN            0.000                  2.654  1       


Data Path
Name                                      Cell/Site Name            Delay Name        Incr      Arrival/Required Time  Fanout  
----------------------------------------  ------------------------  ----------------  --------  ---------------------  ------  
CNT01/Couti_reg[0].ff_inst/CLK->CNT01/Couti_reg[0].ff_inst/Q
                                          SLICE_R14C12A             REG_DEL              0.302                  2.956  4       
top_reveal_coretop_instance/core0/tm_u/secured_signal_1_40
                                                                    NET DELAY            3.254                  6.210  4       
LED1_1_cZ/A->LED1_1_cZ/Z                  SLICE_R38C117D            CTOF_DEL             0.211                  6.421  1       
LED1_1                                                              NET DELAY            1.621                  8.042  1       
LED1_0io.PIC_inst/D                                                 ENDPOINT             0.000                  8.042  1       


Destination Clock Path
Name                                      Cell/Site Name            Delay Name        Incr      Arrival/Required Time  Fanout  
----------------------------------------  ------------------------  ----------------  --------  ---------------------  ------  
                                                                    CONSTRAINT           0.000                  8.888  1       
OSCA001.OSCA_inst/HFCLKOUT                OSC_CORE_OSC_CORE_R1C137  CLOCK LATENCY        0.000                  8.888  323     
top_reveal_coretop_instance/core0/tm_u/secured_instance_1_105/secured_signal_0_141
                                                                    NET DELAY            2.553                 11.441  323     
LED1_0io.PIC_inst/CLK                                               CLOCK PIN            0.000                 11.441  1       
                                                                    Uncertainty       -(0.000)                 11.441  
                                                                    Common Path Skew     0.031                 11.472  
                                                                    Setup time        -(0.337)                 11.135  
----------------------------------------  ------------------------  ----------------  --------  ---------------------  ------  
Required Time                                                                                                  11.135  
Arrival Time                                                                                                 -(8.041)  
----------------------------------------  ------------------------  ----------------  --------  ---------------------  ------  
Path Slack  (Passed)                                                                                            3.093  




++++ Path 3 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 

Path Begin       : top_reveal_coretop_instance/core0/trig_u/tu_3/secured_instance_11_100/Q  (SLICE_R38C106A)
Path End         : top_reveal_coretop_instance/core0/trig_u/tu_3/secured_instance_11_95/DF  (SLICE_R43C109D)
Source Clock     : clk150 (R)
Destination Clock: clk150 (R)
Logic Level      : 11
Delay Ratio      : 56.1% (route), 43.9% (logic)
Clock Skew       : -0.148 ns 
Setup Constraint : 8.888 ns 
Common Path Skew : 0.118 ns 
Path Slack       : 3.874 ns  (Passed)


Source Clock Path
Name                                      Cell/Site Name            Delay Name        Incr       Arrival/Required Time  Fanout  
----------------------------------------  ------------------------  ----------------  ---------  ---------------------  ------  
OSCA001.OSCA_inst/HFCLKOUT                OSC_CORE_OSC_CORE_R1C137  CLOCK LATENCY         0.000                  0.000  323     
top_reveal_coretop_instance/core0/tm_u/secured_instance_1_105/secured_signal_0_141
                                                                    NET DELAY             2.654                  2.654  323     
{top_reveal_coretop_instance/core0/trig_u/tu_3/secured_instance_11_99/CLK   top_reveal_coretop_instance/core0/trig_u/tu_3/secured_instance_11_100/CLK}
                                                                    CLOCK PIN             0.000                  2.654  1       


Data Path
Name                                      Cell/Site Name            Delay Name        Incr       Arrival/Required Time  Fanout  
----------------------------------------  ------------------------  ----------------  ---------  ---------------------  ------  
top_reveal_coretop_instance/core0/trig_u/tu_3/secured_instance_11_100/CLK->top_reveal_coretop_instance/core0/trig_u/tu_3/secured_instance_11_100/Q
                                          SLICE_R38C106A            REG_DEL               0.302                  2.956  3       
top_reveal_coretop_instance/core0/trig_u/tu_3/secured_signal_11_88
                                                                    NET DELAY             0.664                  3.620  3       
top_reveal_coretop_instance/core0/trig_u/tu_3/secured_instance_11_59/B->top_reveal_coretop_instance/core0/trig_u/tu_3/secured_instance_11_59/Z
                                          SLICE_R35C113B            CTOF_DEL              0.211                  3.831  1       
top_reveal_coretop_instance/core0/trig_u/tu_3/secured_signal_11_191
                                                                    NET DELAY             0.393                  4.224  1       
top_reveal_coretop_instance/core0/trig_u/tu_3/secured_instance_11_60/D->top_reveal_coretop_instance/core0/trig_u/tu_3/secured_instance_11_60/Z
                                          SLICE_R35C113B            CTOF_DEL              0.211                  4.435  1       
top_reveal_coretop_instance/core0/trig_u/tu_3/secured_signal_11_162
                                                                    NET DELAY             0.502                  4.937  1       
top_reveal_coretop_instance/core0/trig_u/tu_3/secured_instance_11_79/A1->top_reveal_coretop_instance/core0/trig_u/tu_3/secured_instance_11_79/COUT
                                          SLICE_R30C114A            C1TOFCO_DEL           0.325                  5.262  1       
top_reveal_coretop_instance/core0/trig_u/tu_3/secured_signal_11_112
                                                                    NET DELAY             0.000                  5.262  1       
top_reveal_coretop_instance/core0/trig_u/tu_3/secured_instance_11_78/CIN->top_reveal_coretop_instance/core0/trig_u/tu_3/secured_instance_11_78/COUT
                                          SLICE_R30C114B            FCITOFCO_DEL          0.055                  5.317  1       
top_reveal_coretop_instance/core0/trig_u/tu_3/secured_signal_11_111
                                                                    NET DELAY             0.000                  5.317  1       
top_reveal_coretop_instance/core0/trig_u/tu_3/secured_instance_11_77/CIN->top_reveal_coretop_instance/core0/trig_u/tu_3/secured_instance_11_77/COUT
                                          SLICE_R30C114C            FCITOFCO_DEL          0.055                  5.372  1       
top_reveal_coretop_instance/core0/trig_u/tu_3/secured_signal_11_110
                                                                    NET DELAY             0.000                  5.372  1       
top_reveal_coretop_instance/core0/trig_u/tu_3/secured_instance_11_76/CIN->top_reveal_coretop_instance/core0/trig_u/tu_3/secured_instance_11_76/COUT
                                          SLICE_R30C114D            FCITOFCO_DEL          0.055                  5.427  1       
top_reveal_coretop_instance/core0/trig_u/tu_3/secured_signal_11_109
                                                                    NET DELAY             0.000                  5.427  1       
top_reveal_coretop_instance/core0/trig_u/tu_3/secured_instance_11_75/CIN->top_reveal_coretop_instance/core0/trig_u/tu_3/secured_instance_11_75/S1
                                          SLICE_R30C115A            FCITOF1_DEL           0.288                  5.715  3       
top_reveal_coretop_instance/core0/trig_u/tu_3/secured_signal_11_130
                                                                    NET DELAY             0.488                  6.203  3       
top_reveal_coretop_instance/core0/trig_u/tu_3/secured_instance_11_52/B->top_reveal_coretop_instance/core0/trig_u/tu_3/secured_instance_11_52/Z
                                          SLICE_R36C110B            CTOF_DEL              0.211                  6.414  1       
top_reveal_coretop_instance/core0/trig_u/tu_3/secured_signal_11_163
                                                                    NET DELAY             0.263                  6.677  1       
top_reveal_coretop_instance/core0/trig_u/tu_3/secured_instance_11_90/D->top_reveal_coretop_instance/core0/trig_u/tu_3/secured_instance_11_90/Z
                                          SLICE_R36C109C            CTOOF_DEL             0.281                  6.958  1       
top_reveal_coretop_instance/core0/trig_u/tu_3/secured_signal_11_165
                                                                    NET DELAY             0.520                  7.478  1       
top_reveal_coretop_instance/core0/trig_u/tu_3/secured_instance_11_58/B->top_reveal_coretop_instance/core0/trig_u/tu_3/secured_instance_11_58/Z
                                          SLICE_R43C109D            CTOF_DEL              0.219                  7.697  1       
top_reveal_coretop_instance/core0/trig_u/tu_3/secured_signal_11_150
                                                                    NET DELAY             0.000                  7.697  1       
top_reveal_coretop_instance/core0/trig_u/tu_3/secured_instance_11_95/DF
                                                                    ENDPOINT              0.000                  7.697  1       


Destination Clock Path
Name                                      Cell/Site Name            Delay Name        Incr       Arrival/Required Time  Fanout  
----------------------------------------  ------------------------  ----------------  ---------  ---------------------  ------  
                                                                    CONSTRAINT            0.000                  8.888  1       
OSCA001.OSCA_inst/HFCLKOUT                OSC_CORE_OSC_CORE_R1C137  CLOCK LATENCY         0.000                  8.888  323     
top_reveal_coretop_instance/core0/tm_u/secured_instance_1_105/secured_signal_0_141
                                                                    NET DELAY             2.506                 11.394  323     
{top_reveal_coretop_instance/core0/trig_u/tu_3/secured_instance_11_95/CLK   top_reveal_coretop_instance/core0/trig_u/tu_2/secured_instance_12_95/CLK}
                                                                    CLOCK PIN             0.000                 11.394  1       
                                                                    Uncertainty        -(0.000)                 11.394  
                                                                    Common Path Skew      0.118                 11.512  
                                                                    Setup time        -(-0.059)                 11.571  
----------------------------------------  ------------------------  ----------------  ---------  ---------------------  ------  
Required Time                                                                                                   11.571  
Arrival Time                                                                                                  -(7.696)  
----------------------------------------  ------------------------  ----------------  ---------  ---------------------  ------  
Path Slack  (Passed)                                                                                             3.874  




++++ Path 4 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 

Path Begin       : top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_469/Q  (SLICE_R44C108C)
Path End         : {top_reveal_coretop_instance/core0/trig_u/tu_1/secured_instance_13_154/CE   top_reveal_coretop_instance/core0/trig_u/tu_1/secured_instance_13_153/CE}  (SLICE_R39C104C)
Source Clock     : clk150 (R)
Destination Clock: clk150 (R)
Logic Level      : 7
Delay Ratio      : 67.3% (route), 32.7% (logic)
Clock Skew       : -0.148 ns 
Setup Constraint : 8.888 ns 
Common Path Skew : 0.118 ns 
Path Slack       : 3.880 ns  (Passed)


Source Clock Path
Name                                      Cell/Site Name            Delay Name        Incr      Arrival/Required Time  Fanout  
----------------------------------------  ------------------------  ----------------  --------  ---------------------  ------  
OSCA001.OSCA_inst/HFCLKOUT                OSC_CORE_OSC_CORE_R1C137  CLOCK LATENCY        0.000                  0.000  323     
top_reveal_coretop_instance/core0/tm_u/secured_instance_1_105/secured_signal_0_141
                                                                    NET DELAY            2.654                  2.654  323     
{top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_469/CLK   top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_470/CLK}
                                                                    CLOCK PIN            0.000                  2.654  1       


Data Path
Name                                      Cell/Site Name            Delay Name        Incr      Arrival/Required Time  Fanout  
----------------------------------------  ------------------------  ----------------  --------  ---------------------  ------  
top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_469/CLK->top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_469/Q
                                          SLICE_R44C108C            REG_DEL              0.301                  2.955  5       
top_reveal_coretop_instance/core0/jtag_int_u/secured_signal_2_156
                                                                    NET DELAY            0.474                  3.429  5       
top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_280/A->top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_280/Z
                                          SLICE_R45C107D            CTOF_DEL             0.211                  3.640  1       
top_reveal_coretop_instance/core0/jtag_int_u/secured_signal_2_594
                                                                    NET DELAY            0.218                  3.858  1       
top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_256/C->top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_256/Z
                                          SLICE_R45C109C            CTOF_DEL             0.211                  4.069  5       
top_reveal_coretop_instance/core0/tm_u/secured_signal_1_157
                                                                    NET DELAY            0.511                  4.580  5       
top_reveal_coretop_instance/core0/trig_u/decode_u/secured_instance_15_17/B->top_reveal_coretop_instance/core0/trig_u/decode_u/secured_instance_15_17/Z
                                          SLICE_R43C113A            CTOF_DEL             0.211                  4.791  3       
top_reveal_coretop_instance/core0/trig_u/decode_u/secured_signal_15_26
                                                                    NET DELAY            0.270                  5.061  3       
top_reveal_coretop_instance/core0/trig_u/decode_u/secured_instance_15_5/A->top_reveal_coretop_instance/core0/trig_u/decode_u/secured_instance_15_5/Z
                                          SLICE_R43C112A            CTOF_DEL             0.211                  5.272  4       
top_reveal_coretop_instance/core0/trig_u/decode_u/secured_signal_15_27
                                                                    NET DELAY            0.671                  5.943  4       
top_reveal_coretop_instance/core0/trig_u/decode_u/secured_instance_15_4/A->top_reveal_coretop_instance/core0/trig_u/decode_u/secured_instance_15_4/Z
                                          SLICE_R40C109A            CTOF_DEL             0.211                  6.154  3       
top_reveal_coretop_instance/core0/trig_u/tu_1/secured_signal_13_56
                                                                    NET DELAY            0.376                  6.530  3       
top_reveal_coretop_instance/core0/trig_u/tu_1/secured_instance_13_6/C->top_reveal_coretop_instance/core0/trig_u/tu_1/secured_instance_13_6/Z
                                          SLICE_R40C109A            CTOF_DEL             0.211                  6.741  8       
top_reveal_coretop_instance/core0/trig_u/tu_1/secured_signal_13_148
                                                                    NET DELAY            0.702                  7.443  8       
{top_reveal_coretop_instance/core0/trig_u/tu_1/secured_instance_13_154/CE   top_reveal_coretop_instance/core0/trig_u/tu_1/secured_instance_13_153/CE}
                                                                    ENDPOINT             0.000                  7.443  1       


Destination Clock Path
Name                                      Cell/Site Name            Delay Name        Incr      Arrival/Required Time  Fanout  
----------------------------------------  ------------------------  ----------------  --------  ---------------------  ------  
                                                                    CONSTRAINT           0.000                  8.888  1       
OSCA001.OSCA_inst/HFCLKOUT                OSC_CORE_OSC_CORE_R1C137  CLOCK LATENCY        0.000                  8.888  323     
top_reveal_coretop_instance/core0/tm_u/secured_instance_1_105/secured_signal_0_141
                                                                    NET DELAY            2.506                 11.394  323     
{top_reveal_coretop_instance/core0/trig_u/tu_1/secured_instance_13_154/CLK   top_reveal_coretop_instance/core0/trig_u/tu_1/secured_instance_13_153/CLK}
                                                                    CLOCK PIN            0.000                 11.394  1       
                                                                    Uncertainty       -(0.000)                 11.394  
                                                                    Common Path Skew     0.118                 11.512  
                                                                    Setup time        -(0.189)                 11.323  
----------------------------------------  ------------------------  ----------------  --------  ---------------------  ------  
Required Time                                                                                                  11.323  
Arrival Time                                                                                                 -(7.442)  
----------------------------------------  ------------------------  ----------------  --------  ---------------------  ------  
Path Slack  (Passed)                                                                                            3.880  




++++ Path 5 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 

Path Begin       : top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_469/Q  (SLICE_R44C108C)
Path End         : {top_reveal_coretop_instance/core0/trig_u/tu_1/secured_instance_13_148/CE   top_reveal_coretop_instance/core0/trig_u/tu_1/secured_instance_13_147/CE}  (SLICE_R39C104D)
Source Clock     : clk150 (R)
Destination Clock: clk150 (R)
Logic Level      : 7
Delay Ratio      : 67.3% (route), 32.7% (logic)
Clock Skew       : -0.148 ns 
Setup Constraint : 8.888 ns 
Common Path Skew : 0.118 ns 
Path Slack       : 3.880 ns  (Passed)


Source Clock Path
Name                                      Cell/Site Name            Delay Name        Incr      Arrival/Required Time  Fanout  
----------------------------------------  ------------------------  ----------------  --------  ---------------------  ------  
OSCA001.OSCA_inst/HFCLKOUT                OSC_CORE_OSC_CORE_R1C137  CLOCK LATENCY        0.000                  0.000  323     
top_reveal_coretop_instance/core0/tm_u/secured_instance_1_105/secured_signal_0_141
                                                                    NET DELAY            2.654                  2.654  323     
{top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_469/CLK   top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_470/CLK}
                                                                    CLOCK PIN            0.000                  2.654  1       


Data Path
Name                                      Cell/Site Name            Delay Name        Incr      Arrival/Required Time  Fanout  
----------------------------------------  ------------------------  ----------------  --------  ---------------------  ------  
top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_469/CLK->top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_469/Q
                                          SLICE_R44C108C            REG_DEL              0.301                  2.955  5       
top_reveal_coretop_instance/core0/jtag_int_u/secured_signal_2_156
                                                                    NET DELAY            0.474                  3.429  5       
top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_280/A->top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_280/Z
                                          SLICE_R45C107D            CTOF_DEL             0.211                  3.640  1       
top_reveal_coretop_instance/core0/jtag_int_u/secured_signal_2_594
                                                                    NET DELAY            0.218                  3.858  1       
top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_256/C->top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_256/Z
                                          SLICE_R45C109C            CTOF_DEL             0.211                  4.069  5       
top_reveal_coretop_instance/core0/tm_u/secured_signal_1_157
                                                                    NET DELAY            0.511                  4.580  5       
top_reveal_coretop_instance/core0/trig_u/decode_u/secured_instance_15_17/B->top_reveal_coretop_instance/core0/trig_u/decode_u/secured_instance_15_17/Z
                                          SLICE_R43C113A            CTOF_DEL             0.211                  4.791  3       
top_reveal_coretop_instance/core0/trig_u/decode_u/secured_signal_15_26
                                                                    NET DELAY            0.270                  5.061  3       
top_reveal_coretop_instance/core0/trig_u/decode_u/secured_instance_15_5/A->top_reveal_coretop_instance/core0/trig_u/decode_u/secured_instance_15_5/Z
                                          SLICE_R43C112A            CTOF_DEL             0.211                  5.272  4       
top_reveal_coretop_instance/core0/trig_u/decode_u/secured_signal_15_27
                                                                    NET DELAY            0.671                  5.943  4       
top_reveal_coretop_instance/core0/trig_u/decode_u/secured_instance_15_4/A->top_reveal_coretop_instance/core0/trig_u/decode_u/secured_instance_15_4/Z
                                          SLICE_R40C109A            CTOF_DEL             0.211                  6.154  3       
top_reveal_coretop_instance/core0/trig_u/tu_1/secured_signal_13_56
                                                                    NET DELAY            0.376                  6.530  3       
top_reveal_coretop_instance/core0/trig_u/tu_1/secured_instance_13_6/C->top_reveal_coretop_instance/core0/trig_u/tu_1/secured_instance_13_6/Z
                                          SLICE_R40C109A            CTOF_DEL             0.211                  6.741  8       
top_reveal_coretop_instance/core0/trig_u/tu_1/secured_signal_13_148
                                                                    NET DELAY            0.702                  7.443  8       
{top_reveal_coretop_instance/core0/trig_u/tu_1/secured_instance_13_148/CE   top_reveal_coretop_instance/core0/trig_u/tu_1/secured_instance_13_147/CE}
                                                                    ENDPOINT             0.000                  7.443  1       


Destination Clock Path
Name                                      Cell/Site Name            Delay Name        Incr      Arrival/Required Time  Fanout  
----------------------------------------  ------------------------  ----------------  --------  ---------------------  ------  
                                                                    CONSTRAINT           0.000                  8.888  1       
OSCA001.OSCA_inst/HFCLKOUT                OSC_CORE_OSC_CORE_R1C137  CLOCK LATENCY        0.000                  8.888  323     
top_reveal_coretop_instance/core0/tm_u/secured_instance_1_105/secured_signal_0_141
                                                                    NET DELAY            2.506                 11.394  323     
{top_reveal_coretop_instance/core0/trig_u/tu_1/secured_instance_13_148/CLK   top_reveal_coretop_instance/core0/trig_u/tu_1/secured_instance_13_147/CLK}
                                                                    CLOCK PIN            0.000                 11.394  1       
                                                                    Uncertainty       -(0.000)                 11.394  
                                                                    Common Path Skew     0.118                 11.512  
                                                                    Setup time        -(0.189)                 11.323  
----------------------------------------  ------------------------  ----------------  --------  ---------------------  ------  
Required Time                                                                                                  11.323  
Arrival Time                                                                                                 -(7.442)  
----------------------------------------  ------------------------  ----------------  --------  ---------------------  ------  
Path Slack  (Passed)                                                                                            3.880  




++++ Path 6 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 

Path Begin       : top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_469/Q  (SLICE_R44C108C)
Path End         : {top_reveal_coretop_instance/core0/trig_u/tu_1/secured_instance_13_162/CE   top_reveal_coretop_instance/core0/trig_u/tu_1/secured_instance_13_161/CE}  (SLICE_R38C106C)
Source Clock     : clk150 (R)
Destination Clock: clk150 (R)
Logic Level      : 7
Delay Ratio      : 66.5% (route), 33.5% (logic)
Clock Skew       : -0.148 ns 
Setup Constraint : 8.888 ns 
Common Path Skew : 0.118 ns 
Path Slack       : 3.989 ns  (Passed)


Source Clock Path
Name                                      Cell/Site Name            Delay Name        Incr      Arrival/Required Time  Fanout  
----------------------------------------  ------------------------  ----------------  --------  ---------------------  ------  
OSCA001.OSCA_inst/HFCLKOUT                OSC_CORE_OSC_CORE_R1C137  CLOCK LATENCY        0.000                  0.000  323     
top_reveal_coretop_instance/core0/tm_u/secured_instance_1_105/secured_signal_0_141
                                                                    NET DELAY            2.654                  2.654  323     
{top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_469/CLK   top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_470/CLK}
                                                                    CLOCK PIN            0.000                  2.654  1       


Data Path
Name                                      Cell/Site Name            Delay Name        Incr      Arrival/Required Time  Fanout  
----------------------------------------  ------------------------  ----------------  --------  ---------------------  ------  
top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_469/CLK->top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_469/Q
                                          SLICE_R44C108C            REG_DEL              0.301                  2.955  5       
top_reveal_coretop_instance/core0/jtag_int_u/secured_signal_2_156
                                                                    NET DELAY            0.474                  3.429  5       
top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_280/A->top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_280/Z
                                          SLICE_R45C107D            CTOF_DEL             0.211                  3.640  1       
top_reveal_coretop_instance/core0/jtag_int_u/secured_signal_2_594
                                                                    NET DELAY            0.218                  3.858  1       
top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_256/C->top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_256/Z
                                          SLICE_R45C109C            CTOF_DEL             0.211                  4.069  5       
top_reveal_coretop_instance/core0/tm_u/secured_signal_1_157
                                                                    NET DELAY            0.511                  4.580  5       
top_reveal_coretop_instance/core0/trig_u/decode_u/secured_instance_15_17/B->top_reveal_coretop_instance/core0/trig_u/decode_u/secured_instance_15_17/Z
                                          SLICE_R43C113A            CTOF_DEL             0.211                  4.791  3       
top_reveal_coretop_instance/core0/trig_u/decode_u/secured_signal_15_26
                                                                    NET DELAY            0.270                  5.061  3       
top_reveal_coretop_instance/core0/trig_u/decode_u/secured_instance_15_5/A->top_reveal_coretop_instance/core0/trig_u/decode_u/secured_instance_15_5/Z
                                          SLICE_R43C112A            CTOF_DEL             0.211                  5.272  4       
top_reveal_coretop_instance/core0/trig_u/decode_u/secured_signal_15_27
                                                                    NET DELAY            0.671                  5.943  4       
top_reveal_coretop_instance/core0/trig_u/decode_u/secured_instance_15_4/A->top_reveal_coretop_instance/core0/trig_u/decode_u/secured_instance_15_4/Z
                                          SLICE_R40C109A            CTOF_DEL             0.211                  6.154  3       
top_reveal_coretop_instance/core0/trig_u/tu_1/secured_signal_13_56
                                                                    NET DELAY            0.376                  6.530  3       
top_reveal_coretop_instance/core0/trig_u/tu_1/secured_instance_13_6/C->top_reveal_coretop_instance/core0/trig_u/tu_1/secured_instance_13_6/Z
                                          SLICE_R40C109A            CTOF_DEL             0.211                  6.741  8       
top_reveal_coretop_instance/core0/trig_u/tu_1/secured_signal_13_148
                                                                    NET DELAY            0.593                  7.334  8       
{top_reveal_coretop_instance/core0/trig_u/tu_1/secured_instance_13_162/CE   top_reveal_coretop_instance/core0/trig_u/tu_1/secured_instance_13_161/CE}
                                                                    ENDPOINT             0.000                  7.334  1       


Destination Clock Path
Name                                      Cell/Site Name            Delay Name        Incr      Arrival/Required Time  Fanout  
----------------------------------------  ------------------------  ----------------  --------  ---------------------  ------  
                                                                    CONSTRAINT           0.000                  8.888  1       
OSCA001.OSCA_inst/HFCLKOUT                OSC_CORE_OSC_CORE_R1C137  CLOCK LATENCY        0.000                  8.888  323     
top_reveal_coretop_instance/core0/tm_u/secured_instance_1_105/secured_signal_0_141
                                                                    NET DELAY            2.506                 11.394  323     
{top_reveal_coretop_instance/core0/trig_u/tu_1/secured_instance_13_162/CLK   top_reveal_coretop_instance/core0/trig_u/tu_1/secured_instance_13_161/CLK}
                                                                    CLOCK PIN            0.000                 11.394  1       
                                                                    Uncertainty       -(0.000)                 11.394  
                                                                    Common Path Skew     0.118                 11.512  
                                                                    Setup time        -(0.189)                 11.323  
----------------------------------------  ------------------------  ----------------  --------  ---------------------  ------  
Required Time                                                                                                  11.323  
Arrival Time                                                                                                 -(7.333)  
----------------------------------------  ------------------------  ----------------  --------  ---------------------  ------  
Path Slack  (Passed)                                                                                            3.989  




++++ Path 7 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 

Path Begin       : top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_469/Q  (SLICE_R44C108C)
Path End         : {top_reveal_coretop_instance/core0/trig_u/tu_1/secured_instance_13_150/CE   top_reveal_coretop_instance/core0/trig_u/tu_1/secured_instance_13_149/CE}  (SLICE_R39C106C)
Source Clock     : clk150 (R)
Destination Clock: clk150 (R)
Logic Level      : 7
Delay Ratio      : 66.5% (route), 33.5% (logic)
Clock Skew       : -0.148 ns 
Setup Constraint : 8.888 ns 
Common Path Skew : 0.118 ns 
Path Slack       : 3.989 ns  (Passed)


Source Clock Path
Name                                      Cell/Site Name            Delay Name        Incr      Arrival/Required Time  Fanout  
----------------------------------------  ------------------------  ----------------  --------  ---------------------  ------  
OSCA001.OSCA_inst/HFCLKOUT                OSC_CORE_OSC_CORE_R1C137  CLOCK LATENCY        0.000                  0.000  323     
top_reveal_coretop_instance/core0/tm_u/secured_instance_1_105/secured_signal_0_141
                                                                    NET DELAY            2.654                  2.654  323     
{top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_469/CLK   top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_470/CLK}
                                                                    CLOCK PIN            0.000                  2.654  1       


Data Path
Name                                      Cell/Site Name            Delay Name        Incr      Arrival/Required Time  Fanout  
----------------------------------------  ------------------------  ----------------  --------  ---------------------  ------  
top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_469/CLK->top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_469/Q
                                          SLICE_R44C108C            REG_DEL              0.301                  2.955  5       
top_reveal_coretop_instance/core0/jtag_int_u/secured_signal_2_156
                                                                    NET DELAY            0.474                  3.429  5       
top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_280/A->top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_280/Z
                                          SLICE_R45C107D            CTOF_DEL             0.211                  3.640  1       
top_reveal_coretop_instance/core0/jtag_int_u/secured_signal_2_594
                                                                    NET DELAY            0.218                  3.858  1       
top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_256/C->top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_256/Z
                                          SLICE_R45C109C            CTOF_DEL             0.211                  4.069  5       
top_reveal_coretop_instance/core0/tm_u/secured_signal_1_157
                                                                    NET DELAY            0.511                  4.580  5       
top_reveal_coretop_instance/core0/trig_u/decode_u/secured_instance_15_17/B->top_reveal_coretop_instance/core0/trig_u/decode_u/secured_instance_15_17/Z
                                          SLICE_R43C113A            CTOF_DEL             0.211                  4.791  3       
top_reveal_coretop_instance/core0/trig_u/decode_u/secured_signal_15_26
                                                                    NET DELAY            0.270                  5.061  3       
top_reveal_coretop_instance/core0/trig_u/decode_u/secured_instance_15_5/A->top_reveal_coretop_instance/core0/trig_u/decode_u/secured_instance_15_5/Z
                                          SLICE_R43C112A            CTOF_DEL             0.211                  5.272  4       
top_reveal_coretop_instance/core0/trig_u/decode_u/secured_signal_15_27
                                                                    NET DELAY            0.671                  5.943  4       
top_reveal_coretop_instance/core0/trig_u/decode_u/secured_instance_15_4/A->top_reveal_coretop_instance/core0/trig_u/decode_u/secured_instance_15_4/Z
                                          SLICE_R40C109A            CTOF_DEL             0.211                  6.154  3       
top_reveal_coretop_instance/core0/trig_u/tu_1/secured_signal_13_56
                                                                    NET DELAY            0.376                  6.530  3       
top_reveal_coretop_instance/core0/trig_u/tu_1/secured_instance_13_6/C->top_reveal_coretop_instance/core0/trig_u/tu_1/secured_instance_13_6/Z
                                          SLICE_R40C109A            CTOF_DEL             0.211                  6.741  8       
top_reveal_coretop_instance/core0/trig_u/tu_1/secured_signal_13_148
                                                                    NET DELAY            0.593                  7.334  8       
{top_reveal_coretop_instance/core0/trig_u/tu_1/secured_instance_13_150/CE   top_reveal_coretop_instance/core0/trig_u/tu_1/secured_instance_13_149/CE}
                                                                    ENDPOINT             0.000                  7.334  1       


Destination Clock Path
Name                                      Cell/Site Name            Delay Name        Incr      Arrival/Required Time  Fanout  
----------------------------------------  ------------------------  ----------------  --------  ---------------------  ------  
                                                                    CONSTRAINT           0.000                  8.888  1       
OSCA001.OSCA_inst/HFCLKOUT                OSC_CORE_OSC_CORE_R1C137  CLOCK LATENCY        0.000                  8.888  323     
top_reveal_coretop_instance/core0/tm_u/secured_instance_1_105/secured_signal_0_141
                                                                    NET DELAY            2.506                 11.394  323     
{top_reveal_coretop_instance/core0/trig_u/tu_1/secured_instance_13_150/CLK   top_reveal_coretop_instance/core0/trig_u/tu_1/secured_instance_13_149/CLK}
                                                                    CLOCK PIN            0.000                 11.394  1       
                                                                    Uncertainty       -(0.000)                 11.394  
                                                                    Common Path Skew     0.118                 11.512  
                                                                    Setup time        -(0.189)                 11.323  
----------------------------------------  ------------------------  ----------------  --------  ---------------------  ------  
Required Time                                                                                                  11.323  
Arrival Time                                                                                                 -(7.333)  
----------------------------------------  ------------------------  ----------------  --------  ---------------------  ------  
Path Slack  (Passed)                                                                                            3.989  




++++ Path 8 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 

Path Begin       : top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_469/Q  (SLICE_R44C108C)
Path End         : {top_reveal_coretop_instance/core0/trig_u/tu_1/secured_instance_13_152/CE   top_reveal_coretop_instance/core0/trig_u/tu_1/secured_instance_13_151/CE}  (SLICE_R39C106D)
Source Clock     : clk150 (R)
Destination Clock: clk150 (R)
Logic Level      : 7
Delay Ratio      : 66.5% (route), 33.5% (logic)
Clock Skew       : -0.148 ns 
Setup Constraint : 8.888 ns 
Common Path Skew : 0.118 ns 
Path Slack       : 3.989 ns  (Passed)


Source Clock Path
Name                                      Cell/Site Name            Delay Name        Incr      Arrival/Required Time  Fanout  
----------------------------------------  ------------------------  ----------------  --------  ---------------------  ------  
OSCA001.OSCA_inst/HFCLKOUT                OSC_CORE_OSC_CORE_R1C137  CLOCK LATENCY        0.000                  0.000  323     
top_reveal_coretop_instance/core0/tm_u/secured_instance_1_105/secured_signal_0_141
                                                                    NET DELAY            2.654                  2.654  323     
{top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_469/CLK   top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_470/CLK}
                                                                    CLOCK PIN            0.000                  2.654  1       


Data Path
Name                                      Cell/Site Name            Delay Name        Incr      Arrival/Required Time  Fanout  
----------------------------------------  ------------------------  ----------------  --------  ---------------------  ------  
top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_469/CLK->top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_469/Q
                                          SLICE_R44C108C            REG_DEL              0.301                  2.955  5       
top_reveal_coretop_instance/core0/jtag_int_u/secured_signal_2_156
                                                                    NET DELAY            0.474                  3.429  5       
top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_280/A->top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_280/Z
                                          SLICE_R45C107D            CTOF_DEL             0.211                  3.640  1       
top_reveal_coretop_instance/core0/jtag_int_u/secured_signal_2_594
                                                                    NET DELAY            0.218                  3.858  1       
top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_256/C->top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_256/Z
                                          SLICE_R45C109C            CTOF_DEL             0.211                  4.069  5       
top_reveal_coretop_instance/core0/tm_u/secured_signal_1_157
                                                                    NET DELAY            0.511                  4.580  5       
top_reveal_coretop_instance/core0/trig_u/decode_u/secured_instance_15_17/B->top_reveal_coretop_instance/core0/trig_u/decode_u/secured_instance_15_17/Z
                                          SLICE_R43C113A            CTOF_DEL             0.211                  4.791  3       
top_reveal_coretop_instance/core0/trig_u/decode_u/secured_signal_15_26
                                                                    NET DELAY            0.270                  5.061  3       
top_reveal_coretop_instance/core0/trig_u/decode_u/secured_instance_15_5/A->top_reveal_coretop_instance/core0/trig_u/decode_u/secured_instance_15_5/Z
                                          SLICE_R43C112A            CTOF_DEL             0.211                  5.272  4       
top_reveal_coretop_instance/core0/trig_u/decode_u/secured_signal_15_27
                                                                    NET DELAY            0.671                  5.943  4       
top_reveal_coretop_instance/core0/trig_u/decode_u/secured_instance_15_4/A->top_reveal_coretop_instance/core0/trig_u/decode_u/secured_instance_15_4/Z
                                          SLICE_R40C109A            CTOF_DEL             0.211                  6.154  3       
top_reveal_coretop_instance/core0/trig_u/tu_1/secured_signal_13_56
                                                                    NET DELAY            0.376                  6.530  3       
top_reveal_coretop_instance/core0/trig_u/tu_1/secured_instance_13_6/C->top_reveal_coretop_instance/core0/trig_u/tu_1/secured_instance_13_6/Z
                                          SLICE_R40C109A            CTOF_DEL             0.211                  6.741  8       
top_reveal_coretop_instance/core0/trig_u/tu_1/secured_signal_13_148
                                                                    NET DELAY            0.593                  7.334  8       
{top_reveal_coretop_instance/core0/trig_u/tu_1/secured_instance_13_152/CE   top_reveal_coretop_instance/core0/trig_u/tu_1/secured_instance_13_151/CE}
                                                                    ENDPOINT             0.000                  7.334  1       


Destination Clock Path
Name                                      Cell/Site Name            Delay Name        Incr      Arrival/Required Time  Fanout  
----------------------------------------  ------------------------  ----------------  --------  ---------------------  ------  
                                                                    CONSTRAINT           0.000                  8.888  1       
OSCA001.OSCA_inst/HFCLKOUT                OSC_CORE_OSC_CORE_R1C137  CLOCK LATENCY        0.000                  8.888  323     
top_reveal_coretop_instance/core0/tm_u/secured_instance_1_105/secured_signal_0_141
                                                                    NET DELAY            2.506                 11.394  323     
{top_reveal_coretop_instance/core0/trig_u/tu_1/secured_instance_13_152/CLK   top_reveal_coretop_instance/core0/trig_u/tu_1/secured_instance_13_151/CLK}
                                                                    CLOCK PIN            0.000                 11.394  1       
                                                                    Uncertainty       -(0.000)                 11.394  
                                                                    Common Path Skew     0.118                 11.512  
                                                                    Setup time        -(0.189)                 11.323  
----------------------------------------  ------------------------  ----------------  --------  ---------------------  ------  
Required Time                                                                                                  11.323  
Arrival Time                                                                                                 -(7.333)  
----------------------------------------  ------------------------  ----------------  --------  ---------------------  ------  
Path Slack  (Passed)                                                                                            3.989  




++++ Path 9 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 

Path Begin       : top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_469/Q  (SLICE_R44C108C)
Path End         : {top_reveal_coretop_instance/core0/trig_u/tu_1/secured_instance_13_156/CE   top_reveal_coretop_instance/core0/trig_u/tu_1/secured_instance_13_155/CE}  (SLICE_R38C106D)
Source Clock     : clk150 (R)
Destination Clock: clk150 (R)
Logic Level      : 7
Delay Ratio      : 66.5% (route), 33.5% (logic)
Clock Skew       : -0.148 ns 
Setup Constraint : 8.888 ns 
Common Path Skew : 0.118 ns 
Path Slack       : 3.989 ns  (Passed)


Source Clock Path
Name                                      Cell/Site Name            Delay Name        Incr      Arrival/Required Time  Fanout  
----------------------------------------  ------------------------  ----------------  --------  ---------------------  ------  
OSCA001.OSCA_inst/HFCLKOUT                OSC_CORE_OSC_CORE_R1C137  CLOCK LATENCY        0.000                  0.000  323     
top_reveal_coretop_instance/core0/tm_u/secured_instance_1_105/secured_signal_0_141
                                                                    NET DELAY            2.654                  2.654  323     
{top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_469/CLK   top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_470/CLK}
                                                                    CLOCK PIN            0.000                  2.654  1       


Data Path
Name                                      Cell/Site Name            Delay Name        Incr      Arrival/Required Time  Fanout  
----------------------------------------  ------------------------  ----------------  --------  ---------------------  ------  
top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_469/CLK->top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_469/Q
                                          SLICE_R44C108C            REG_DEL              0.301                  2.955  5       
top_reveal_coretop_instance/core0/jtag_int_u/secured_signal_2_156
                                                                    NET DELAY            0.474                  3.429  5       
top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_280/A->top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_280/Z
                                          SLICE_R45C107D            CTOF_DEL             0.211                  3.640  1       
top_reveal_coretop_instance/core0/jtag_int_u/secured_signal_2_594
                                                                    NET DELAY            0.218                  3.858  1       
top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_256/C->top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_256/Z
                                          SLICE_R45C109C            CTOF_DEL             0.211                  4.069  5       
top_reveal_coretop_instance/core0/tm_u/secured_signal_1_157
                                                                    NET DELAY            0.511                  4.580  5       
top_reveal_coretop_instance/core0/trig_u/decode_u/secured_instance_15_17/B->top_reveal_coretop_instance/core0/trig_u/decode_u/secured_instance_15_17/Z
                                          SLICE_R43C113A            CTOF_DEL             0.211                  4.791  3       
top_reveal_coretop_instance/core0/trig_u/decode_u/secured_signal_15_26
                                                                    NET DELAY            0.270                  5.061  3       
top_reveal_coretop_instance/core0/trig_u/decode_u/secured_instance_15_5/A->top_reveal_coretop_instance/core0/trig_u/decode_u/secured_instance_15_5/Z
                                          SLICE_R43C112A            CTOF_DEL             0.211                  5.272  4       
top_reveal_coretop_instance/core0/trig_u/decode_u/secured_signal_15_27
                                                                    NET DELAY            0.671                  5.943  4       
top_reveal_coretop_instance/core0/trig_u/decode_u/secured_instance_15_4/A->top_reveal_coretop_instance/core0/trig_u/decode_u/secured_instance_15_4/Z
                                          SLICE_R40C109A            CTOF_DEL             0.211                  6.154  3       
top_reveal_coretop_instance/core0/trig_u/tu_1/secured_signal_13_56
                                                                    NET DELAY            0.376                  6.530  3       
top_reveal_coretop_instance/core0/trig_u/tu_1/secured_instance_13_6/C->top_reveal_coretop_instance/core0/trig_u/tu_1/secured_instance_13_6/Z
                                          SLICE_R40C109A            CTOF_DEL             0.211                  6.741  8       
top_reveal_coretop_instance/core0/trig_u/tu_1/secured_signal_13_148
                                                                    NET DELAY            0.593                  7.334  8       
{top_reveal_coretop_instance/core0/trig_u/tu_1/secured_instance_13_156/CE   top_reveal_coretop_instance/core0/trig_u/tu_1/secured_instance_13_155/CE}
                                                                    ENDPOINT             0.000                  7.334  1       


Destination Clock Path
Name                                      Cell/Site Name            Delay Name        Incr      Arrival/Required Time  Fanout  
----------------------------------------  ------------------------  ----------------  --------  ---------------------  ------  
                                                                    CONSTRAINT           0.000                  8.888  1       
OSCA001.OSCA_inst/HFCLKOUT                OSC_CORE_OSC_CORE_R1C137  CLOCK LATENCY        0.000                  8.888  323     
top_reveal_coretop_instance/core0/tm_u/secured_instance_1_105/secured_signal_0_141
                                                                    NET DELAY            2.506                 11.394  323     
{top_reveal_coretop_instance/core0/trig_u/tu_1/secured_instance_13_156/CLK   top_reveal_coretop_instance/core0/trig_u/tu_1/secured_instance_13_155/CLK}
                                                                    CLOCK PIN            0.000                 11.394  1       
                                                                    Uncertainty       -(0.000)                 11.394  
                                                                    Common Path Skew     0.118                 11.512  
                                                                    Setup time        -(0.189)                 11.323  
----------------------------------------  ------------------------  ----------------  --------  ---------------------  ------  
Required Time                                                                                                  11.323  
Arrival Time                                                                                                 -(7.333)  
----------------------------------------  ------------------------  ----------------  --------  ---------------------  ------  
Path Slack  (Passed)                                                                                            3.989  




++++ Path 10 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 

Path Begin       : top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_469/Q  (SLICE_R44C108C)
Path End         : {top_reveal_coretop_instance/core0/trig_u/tu_1/secured_instance_13_160/CE   top_reveal_coretop_instance/core0/trig_u/tu_1/secured_instance_13_159/CE}  (SLICE_R38C107D)
Source Clock     : clk150 (R)
Destination Clock: clk150 (R)
Logic Level      : 7
Delay Ratio      : 66.5% (route), 33.5% (logic)
Clock Skew       : -0.148 ns 
Setup Constraint : 8.888 ns 
Common Path Skew : 0.118 ns 
Path Slack       : 3.996 ns  (Passed)


Source Clock Path
Name                                      Cell/Site Name            Delay Name        Incr      Arrival/Required Time  Fanout  
----------------------------------------  ------------------------  ----------------  --------  ---------------------  ------  
OSCA001.OSCA_inst/HFCLKOUT                OSC_CORE_OSC_CORE_R1C137  CLOCK LATENCY        0.000                  0.000  323     
top_reveal_coretop_instance/core0/tm_u/secured_instance_1_105/secured_signal_0_141
                                                                    NET DELAY            2.654                  2.654  323     
{top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_469/CLK   top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_470/CLK}
                                                                    CLOCK PIN            0.000                  2.654  1       


Data Path
Name                                      Cell/Site Name            Delay Name        Incr      Arrival/Required Time  Fanout  
----------------------------------------  ------------------------  ----------------  --------  ---------------------  ------  
top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_469/CLK->top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_469/Q
                                          SLICE_R44C108C            REG_DEL              0.301                  2.955  5       
top_reveal_coretop_instance/core0/jtag_int_u/secured_signal_2_156
                                                                    NET DELAY            0.474                  3.429  5       
top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_280/A->top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_280/Z
                                          SLICE_R45C107D            CTOF_DEL             0.211                  3.640  1       
top_reveal_coretop_instance/core0/jtag_int_u/secured_signal_2_594
                                                                    NET DELAY            0.218                  3.858  1       
top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_256/C->top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_256/Z
                                          SLICE_R45C109C            CTOF_DEL             0.211                  4.069  5       
top_reveal_coretop_instance/core0/tm_u/secured_signal_1_157
                                                                    NET DELAY            0.511                  4.580  5       
top_reveal_coretop_instance/core0/trig_u/decode_u/secured_instance_15_17/B->top_reveal_coretop_instance/core0/trig_u/decode_u/secured_instance_15_17/Z
                                          SLICE_R43C113A            CTOF_DEL             0.211                  4.791  3       
top_reveal_coretop_instance/core0/trig_u/decode_u/secured_signal_15_26
                                                                    NET DELAY            0.270                  5.061  3       
top_reveal_coretop_instance/core0/trig_u/decode_u/secured_instance_15_5/A->top_reveal_coretop_instance/core0/trig_u/decode_u/secured_instance_15_5/Z
                                          SLICE_R43C112A            CTOF_DEL             0.211                  5.272  4       
top_reveal_coretop_instance/core0/trig_u/decode_u/secured_signal_15_27
                                                                    NET DELAY            0.671                  5.943  4       
top_reveal_coretop_instance/core0/trig_u/decode_u/secured_instance_15_4/A->top_reveal_coretop_instance/core0/trig_u/decode_u/secured_instance_15_4/Z
                                          SLICE_R40C109A            CTOF_DEL             0.211                  6.154  3       
top_reveal_coretop_instance/core0/trig_u/tu_1/secured_signal_13_56
                                                                    NET DELAY            0.376                  6.530  3       
top_reveal_coretop_instance/core0/trig_u/tu_1/secured_instance_13_6/C->top_reveal_coretop_instance/core0/trig_u/tu_1/secured_instance_13_6/Z
                                          SLICE_R40C109A            CTOF_DEL             0.211                  6.741  8       
top_reveal_coretop_instance/core0/trig_u/tu_1/secured_signal_13_148
                                                                    NET DELAY            0.586                  7.327  8       
{top_reveal_coretop_instance/core0/trig_u/tu_1/secured_instance_13_160/CE   top_reveal_coretop_instance/core0/trig_u/tu_1/secured_instance_13_159/CE}
                                                                    ENDPOINT             0.000                  7.327  1       


Destination Clock Path
Name                                      Cell/Site Name            Delay Name        Incr      Arrival/Required Time  Fanout  
----------------------------------------  ------------------------  ----------------  --------  ---------------------  ------  
                                                                    CONSTRAINT           0.000                  8.888  1       
OSCA001.OSCA_inst/HFCLKOUT                OSC_CORE_OSC_CORE_R1C137  CLOCK LATENCY        0.000                  8.888  323     
top_reveal_coretop_instance/core0/tm_u/secured_instance_1_105/secured_signal_0_141
                                                                    NET DELAY            2.506                 11.394  323     
{top_reveal_coretop_instance/core0/trig_u/tu_1/secured_instance_13_160/CLK   top_reveal_coretop_instance/core0/trig_u/tu_1/secured_instance_13_159/CLK}
                                                                    CLOCK PIN            0.000                 11.394  1       
                                                                    Uncertainty       -(0.000)                 11.394  
                                                                    Common Path Skew     0.118                 11.512  
                                                                    Setup time        -(0.189)                 11.323  
----------------------------------------  ------------------------  ----------------  --------  ---------------------  ------  
Required Time                                                                                                  11.323  
Arrival Time                                                                                                 -(7.326)  
----------------------------------------  ------------------------  ----------------  --------  ---------------------  ------  
Path Slack  (Passed)                                                                                            3.996  



+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 
                    End of Detailed Report for timing paths 
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 


##########################################################



===============================================================
4  Hold at Speed Grade m Corner at -40 Degrees
===============================================================

4.1  Endpoint slacks
=======================
-------------------------------------------------------
          Listing 10 End Points          |    Slack    
-------------------------------------------------------
top_reveal_coretop_instance/core0/trig_u/tu_1/secured_instance_13_123/DF              
                                         |    0.164 ns 
top_reveal_coretop_instance/core0/trig_u/tu_1/secured_instance_13_130/DF              
                                         |    0.165 ns 
top_reveal_coretop_instance/core0/trig_u/tu_4/secured_instance_10_122/DF              
                                         |    0.166 ns 
top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_470/DF              
                                         |    0.166 ns 
top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_468/DF              
                                         |    0.166 ns 
top_reveal_coretop_instance/core0/trig_u/tu_0/secured_instance_14_23/DF              
                                         |    0.167 ns 
top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_486/DF              
                                         |    0.167 ns 
top_reveal_coretop_instance/core0/trig_u/tu_1/secured_instance_13_122/DF              
                                         |    0.168 ns 
top_reveal_coretop_instance/core0/trig_u/tu_4/secured_instance_10_124/DF              
                                         |    0.168 ns 
top_reveal_coretop_instance/core0/trig_u/tu_3/secured_instance_11_120/DF              
                                         |    0.170 ns 
-------------------------------------------------------
                                         |             
Hold # of endpoints with negative slack: |           0 
                                         |             
-------------------------------------------------------

4.2  Detailed Report
=======================


XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

Detail report of critical paths

XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
                    Detailed Report for timing paths 
 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++

 ++++Path 1  ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++

Path Begin       : top_reveal_coretop_instance/core0/trig_u/tu_1/secured_instance_13_139/Q  (SLICE_R39C105A)
Path End         : top_reveal_coretop_instance/core0/trig_u/tu_1/secured_instance_13_123/DF  (SLICE_R39C105D)
Source Clock     : clk150 (R)
Destination Clock: clk150 (R)
Logic Level      : 1
Delay Ratio      : 31.5% (route), 68.5% (logic)
Clock Skew       : 0.113 ns 
Hold Constraint  : 0.000 ns 
Common Path Skew : -0.111 ns 
Path Slack       : 0.164 ns  (Passed)


Source Clock Path
Name                                      Cell/Site Name            Delay Name        Incr    Arrival/Required Time  Fanout  
----------------------------------------  ------------------------  ----------------  ------  ---------------------  ------  
OSCA001.OSCA_inst/HFCLKOUT                OSC_CORE_OSC_CORE_R1C137  CLOCK LATENCY      0.000                  0.000  324     
top_reveal_coretop_instance/core0/tm_u/secured_instance_1_105/secured_signal_0_141
                                                                    NET DELAY          1.808                  1.808  324     
top_reveal_coretop_instance/core0/trig_u/tu_1/secured_instance_13_139/CLK
                                                                    CLOCK PIN          0.000                  1.808  1       


Data Path
Name                                      Cell/Site Name            Delay Name        Incr    Arrival/Required Time  Fanout  
----------------------------------------  ------------------------  ----------------  ------  ---------------------  ------  
top_reveal_coretop_instance/core0/trig_u/tu_1/secured_instance_13_139/CLK->top_reveal_coretop_instance/core0/trig_u/tu_1/secured_instance_13_139/Q
                                          SLICE_R39C105A            REG_DEL            0.178                  1.986  5       
top_reveal_coretop_instance/core0/trig_u/tu_1/secured_signal_13_139
                                                                    NET DELAY          0.082                  2.068  5       
top_reveal_coretop_instance/core0/trig_u/tu_1/secured_instance_13_123/DF
                                                                    ENDPOINT           0.000                  2.068  1       


Destination Clock Path
Name                                      Cell/Site Name            Delay Name        Incr    Arrival/Required Time  Fanout  
----------------------------------------  ------------------------  ----------------  ------  ---------------------  ------  
                                                                    CONSTRAINT         0.000                  0.000  1       
OSCA001.OSCA_inst/HFCLKOUT                OSC_CORE_OSC_CORE_R1C137  CLOCK LATENCY      0.000                  0.000  324     
top_reveal_coretop_instance/core0/tm_u/secured_instance_1_105/secured_signal_0_141
                                                                    NET DELAY          1.921                  1.921  324     
{top_reveal_coretop_instance/core0/trig_u/tu_1/secured_instance_13_123/CLK   top_reveal_coretop_instance/core0/trig_u/tu_1/secured_instance_13_124/CLK}
                                                                    CLOCK PIN          0.000                  1.921  1       
                                                                    Uncertainty        0.000                  1.921  
                                                                    Common Path Skew  -0.111                  1.810  
                                                                    Hold time          0.094                  1.904  
----------------------------------------  ------------------------  ----------------  ------  ---------------------  ------  
Required Time                                                                                                -1.904  
Arrival Time                                                                                                  2.068  
----------------------------------------  ------------------------  ----------------  ------  ---------------------  ------  
Path Slack  (Passed)                                                                                          0.164  




++++ Path 2 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 

Path Begin       : top_reveal_coretop_instance/core0/trig_u/tu_1/secured_instance_13_146/Q  (SLICE_R39C105C)
Path End         : top_reveal_coretop_instance/core0/trig_u/tu_1/secured_instance_13_130/DF  (SLICE_R39C105B)
Source Clock     : clk150 (R)
Destination Clock: clk150 (R)
Logic Level      : 1
Delay Ratio      : 31.4% (route), 68.6% (logic)
Clock Skew       : 0.113 ns 
Hold Constraint  : 0.000 ns 
Common Path Skew : -0.111 ns 
Path Slack       : 0.165 ns  (Passed)


Source Clock Path
Name                                      Cell/Site Name            Delay Name        Incr    Arrival/Required Time  Fanout  
----------------------------------------  ------------------------  ----------------  ------  ---------------------  ------  
OSCA001.OSCA_inst/HFCLKOUT                OSC_CORE_OSC_CORE_R1C137  CLOCK LATENCY      0.000                  0.000  324     
top_reveal_coretop_instance/core0/tm_u/secured_instance_1_105/secured_signal_0_141
                                                                    NET DELAY          1.808                  1.808  324     
{top_reveal_coretop_instance/core0/trig_u/tu_1/secured_instance_13_140/CLK   top_reveal_coretop_instance/core0/trig_u/tu_1/secured_instance_13_146/CLK}
                                                                    CLOCK PIN          0.000                  1.808  1       


Data Path
Name                                      Cell/Site Name            Delay Name        Incr    Arrival/Required Time  Fanout  
----------------------------------------  ------------------------  ----------------  ------  ---------------------  ------  
top_reveal_coretop_instance/core0/trig_u/tu_1/secured_instance_13_146/CLK->top_reveal_coretop_instance/core0/trig_u/tu_1/secured_instance_13_146/Q
                                          SLICE_R39C105C            REG_DEL            0.179                  1.987  5       
top_reveal_coretop_instance/core0/trig_u/tu_1/secured_signal_13_146
                                                                    NET DELAY          0.082                  2.069  5       
top_reveal_coretop_instance/core0/trig_u/tu_1/secured_instance_13_130/DF
                                                                    ENDPOINT           0.000                  2.069  1       


Destination Clock Path
Name                                      Cell/Site Name            Delay Name        Incr    Arrival/Required Time  Fanout  
----------------------------------------  ------------------------  ----------------  ------  ---------------------  ------  
                                                                    CONSTRAINT         0.000                  0.000  1       
OSCA001.OSCA_inst/HFCLKOUT                OSC_CORE_OSC_CORE_R1C137  CLOCK LATENCY      0.000                  0.000  324     
top_reveal_coretop_instance/core0/tm_u/secured_instance_1_105/secured_signal_0_141
                                                                    NET DELAY          1.921                  1.921  324     
{top_reveal_coretop_instance/core0/trig_u/tu_1/secured_instance_13_129/CLK   top_reveal_coretop_instance/core0/trig_u/tu_1/secured_instance_13_130/CLK}
                                                                    CLOCK PIN          0.000                  1.921  1       
                                                                    Uncertainty        0.000                  1.921  
                                                                    Common Path Skew  -0.111                  1.810  
                                                                    Hold time          0.094                  1.904  
----------------------------------------  ------------------------  ----------------  ------  ---------------------  ------  
Required Time                                                                                                -1.904  
Arrival Time                                                                                                  2.069  
----------------------------------------  ------------------------  ----------------  ------  ---------------------  ------  
Path Slack  (Passed)                                                                                          0.165  




++++ Path 3 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 

Path Begin       : top_reveal_coretop_instance/core0/trig_u/tu_4/secured_instance_10_138/Q  (SLICE_R33C109C)
Path End         : top_reveal_coretop_instance/core0/trig_u/tu_4/secured_instance_10_122/DF  (SLICE_R33C109D)
Source Clock     : clk150 (R)
Destination Clock: clk150 (R)
Logic Level      : 1
Delay Ratio      : 31.5% (route), 68.5% (logic)
Clock Skew       : 0.113 ns 
Hold Constraint  : 0.000 ns 
Common Path Skew : -0.113 ns 
Path Slack       : 0.166 ns  (Passed)


Source Clock Path
Name                                      Cell/Site Name            Delay Name        Incr    Arrival/Required Time  Fanout  
----------------------------------------  ------------------------  ----------------  ------  ---------------------  ------  
OSCA001.OSCA_inst/HFCLKOUT                OSC_CORE_OSC_CORE_R1C137  CLOCK LATENCY      0.000                  0.000  324     
top_reveal_coretop_instance/core0/tm_u/secured_instance_1_105/secured_signal_0_141
                                                                    NET DELAY          1.808                  1.808  324     
{top_reveal_coretop_instance/core0/trig_u/tu_4/secured_instance_10_138/CLK   top_reveal_coretop_instance/core0/trig_u/tu_4/secured_instance_10_142/CLK}
                                                                    CLOCK PIN          0.000                  1.808  1       


Data Path
Name                                      Cell/Site Name            Delay Name        Incr    Arrival/Required Time  Fanout  
----------------------------------------  ------------------------  ----------------  ------  ---------------------  ------  
top_reveal_coretop_instance/core0/trig_u/tu_4/secured_instance_10_138/CLK->top_reveal_coretop_instance/core0/trig_u/tu_4/secured_instance_10_138/Q
                                          SLICE_R33C109C            REG_DEL            0.178                  1.986  5       
top_reveal_coretop_instance/core0/trig_u/tu_4/secured_signal_10_138
                                                                    NET DELAY          0.082                  2.068  5       
top_reveal_coretop_instance/core0/trig_u/tu_4/secured_instance_10_122/DF
                                                                    ENDPOINT           0.000                  2.068  1       


Destination Clock Path
Name                                      Cell/Site Name            Delay Name        Incr    Arrival/Required Time  Fanout  
----------------------------------------  ------------------------  ----------------  ------  ---------------------  ------  
                                                                    CONSTRAINT         0.000                  0.000  1       
OSCA001.OSCA_inst/HFCLKOUT                OSC_CORE_OSC_CORE_R1C137  CLOCK LATENCY      0.000                  0.000  324     
top_reveal_coretop_instance/core0/tm_u/secured_instance_1_105/secured_signal_0_141
                                                                    NET DELAY          1.921                  1.921  324     
{top_reveal_coretop_instance/core0/trig_u/tu_4/secured_instance_10_121/CLK   top_reveal_coretop_instance/core0/trig_u/tu_4/secured_instance_10_122/CLK}
                                                                    CLOCK PIN          0.000                  1.921  1       
                                                                    Uncertainty        0.000                  1.921  
                                                                    Common Path Skew  -0.113                  1.808  
                                                                    Hold time          0.094                  1.902  
----------------------------------------  ------------------------  ----------------  ------  ---------------------  ------  
Required Time                                                                                                -1.902  
Arrival Time                                                                                                  2.068  
----------------------------------------  ------------------------  ----------------  ------  ---------------------  ------  
Path Slack  (Passed)                                                                                          0.166  




++++ Path 4 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 

Path Begin       : top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_469/Q  (SLICE_R44C108C)
Path End         : top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_470/DF  (SLICE_R44C108C)
Source Clock     : clk150 (R)
Destination Clock: clk150 (R)
Logic Level      : 1
Delay Ratio      : 31.5% (route), 68.5% (logic)
Clock Skew       : 0.113 ns 
Hold Constraint  : 0.000 ns 
Common Path Skew : -0.113 ns 
Path Slack       : 0.166 ns  (Passed)


Source Clock Path
Name                                      Cell/Site Name            Delay Name        Incr    Arrival/Required Time  Fanout  
----------------------------------------  ------------------------  ----------------  ------  ---------------------  ------  
OSCA001.OSCA_inst/HFCLKOUT                OSC_CORE_OSC_CORE_R1C137  CLOCK LATENCY      0.000                  0.000  324     
top_reveal_coretop_instance/core0/tm_u/secured_instance_1_105/secured_signal_0_141
                                                                    NET DELAY          1.808                  1.808  324     
{top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_469/CLK   top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_470/CLK}
                                                                    CLOCK PIN          0.000                  1.808  1       


Data Path
Name                                      Cell/Site Name            Delay Name        Incr    Arrival/Required Time  Fanout  
----------------------------------------  ------------------------  ----------------  ------  ---------------------  ------  
top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_469/CLK->top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_469/Q
                                          SLICE_R44C108C            REG_DEL            0.178                  1.986  5       
top_reveal_coretop_instance/core0/jtag_int_u/secured_signal_2_156
                                                                    NET DELAY          0.082                  2.068  5       
top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_470/DF
                                                                    ENDPOINT           0.000                  2.068  1       


Destination Clock Path
Name                                      Cell/Site Name            Delay Name        Incr    Arrival/Required Time  Fanout  
----------------------------------------  ------------------------  ----------------  ------  ---------------------  ------  
                                                                    CONSTRAINT         0.000                  0.000  1       
OSCA001.OSCA_inst/HFCLKOUT                OSC_CORE_OSC_CORE_R1C137  CLOCK LATENCY      0.000                  0.000  324     
top_reveal_coretop_instance/core0/tm_u/secured_instance_1_105/secured_signal_0_141
                                                                    NET DELAY          1.921                  1.921  324     
{top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_469/CLK   top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_470/CLK}
                                                                    CLOCK PIN          0.000                  1.921  1       
                                                                    Uncertainty        0.000                  1.921  
                                                                    Common Path Skew  -0.113                  1.808  
                                                                    Hold time          0.094                  1.902  
----------------------------------------  ------------------------  ----------------  ------  ---------------------  ------  
Required Time                                                                                                -1.902  
Arrival Time                                                                                                  2.068  
----------------------------------------  ------------------------  ----------------  ------  ---------------------  ------  
Path Slack  (Passed)                                                                                          0.166  




++++ Path 5 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 

Path Begin       : top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_467/Q  (SLICE_R44C110D)
Path End         : top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_468/DF  (SLICE_R44C110D)
Source Clock     : clk150 (R)
Destination Clock: clk150 (R)
Logic Level      : 1
Delay Ratio      : 31.5% (route), 68.5% (logic)
Clock Skew       : 0.113 ns 
Hold Constraint  : 0.000 ns 
Common Path Skew : -0.113 ns 
Path Slack       : 0.166 ns  (Passed)


Source Clock Path
Name                                      Cell/Site Name            Delay Name        Incr    Arrival/Required Time  Fanout  
----------------------------------------  ------------------------  ----------------  ------  ---------------------  ------  
OSCA001.OSCA_inst/HFCLKOUT                OSC_CORE_OSC_CORE_R1C137  CLOCK LATENCY      0.000                  0.000  324     
top_reveal_coretop_instance/core0/tm_u/secured_instance_1_105/secured_signal_0_141
                                                                    NET DELAY          1.808                  1.808  324     
{top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_467/CLK   top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_468/CLK}
                                                                    CLOCK PIN          0.000                  1.808  1       


Data Path
Name                                      Cell/Site Name            Delay Name        Incr    Arrival/Required Time  Fanout  
----------------------------------------  ------------------------  ----------------  ------  ---------------------  ------  
top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_467/CLK->top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_467/Q
                                          SLICE_R44C110D            REG_DEL            0.178                  1.986  1       
top_reveal_coretop_instance/core0/jtag_int_u/secured_signal_2_158
                                                                    NET DELAY          0.082                  2.068  1       
top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_468/DF
                                                                    ENDPOINT           0.000                  2.068  1       


Destination Clock Path
Name                                      Cell/Site Name            Delay Name        Incr    Arrival/Required Time  Fanout  
----------------------------------------  ------------------------  ----------------  ------  ---------------------  ------  
                                                                    CONSTRAINT         0.000                  0.000  1       
OSCA001.OSCA_inst/HFCLKOUT                OSC_CORE_OSC_CORE_R1C137  CLOCK LATENCY      0.000                  0.000  324     
top_reveal_coretop_instance/core0/tm_u/secured_instance_1_105/secured_signal_0_141
                                                                    NET DELAY          1.921                  1.921  324     
{top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_467/CLK   top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_468/CLK}
                                                                    CLOCK PIN          0.000                  1.921  1       
                                                                    Uncertainty        0.000                  1.921  
                                                                    Common Path Skew  -0.113                  1.808  
                                                                    Hold time          0.094                  1.902  
----------------------------------------  ------------------------  ----------------  ------  ---------------------  ------  
Required Time                                                                                                -1.902  
Arrival Time                                                                                                  2.068  
----------------------------------------  ------------------------  ----------------  ------  ---------------------  ------  
Path Slack  (Passed)                                                                                          0.166  




++++ Path 6 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 

Path Begin       : top_reveal_coretop_instance/core0/trig_u/tu_0/secured_instance_14_24/Q  (SLICE_R45C109D)
Path End         : top_reveal_coretop_instance/core0/trig_u/tu_0/secured_instance_14_23/DF  (SLICE_R45C109D)
Source Clock     : clk150 (R)
Destination Clock: clk150 (R)
Logic Level      : 1
Delay Ratio      : 31.4% (route), 68.6% (logic)
Clock Skew       : 0.113 ns 
Hold Constraint  : 0.000 ns 
Common Path Skew : -0.113 ns 
Path Slack       : 0.167 ns  (Passed)


Source Clock Path
Name                                      Cell/Site Name            Delay Name        Incr    Arrival/Required Time  Fanout  
----------------------------------------  ------------------------  ----------------  ------  ---------------------  ------  
OSCA001.OSCA_inst/HFCLKOUT                OSC_CORE_OSC_CORE_R1C137  CLOCK LATENCY      0.000                  0.000  324     
top_reveal_coretop_instance/core0/tm_u/secured_instance_1_105/secured_signal_0_141
                                                                    NET DELAY          1.808                  1.808  324     
{top_reveal_coretop_instance/core0/trig_u/tu_0/secured_instance_14_23/CLK   top_reveal_coretop_instance/core0/trig_u/tu_0/secured_instance_14_24/CLK}
                                                                    CLOCK PIN          0.000                  1.808  1       


Data Path
Name                                      Cell/Site Name            Delay Name        Incr    Arrival/Required Time  Fanout  
----------------------------------------  ------------------------  ----------------  ------  ---------------------  ------  
top_reveal_coretop_instance/core0/trig_u/tu_0/secured_instance_14_24/CLK->top_reveal_coretop_instance/core0/trig_u/tu_0/secured_instance_14_24/Q
                                          SLICE_R45C109D            REG_DEL            0.179                  1.987  6       
top_reveal_coretop_instance/core0/trig_u/tu_0/secured_signal_14_18
                                                                    NET DELAY          0.082                  2.069  6       
top_reveal_coretop_instance/core0/trig_u/tu_0/secured_instance_14_23/DF
                                                                    ENDPOINT           0.000                  2.069  1       


Destination Clock Path
Name                                      Cell/Site Name            Delay Name        Incr    Arrival/Required Time  Fanout  
----------------------------------------  ------------------------  ----------------  ------  ---------------------  ------  
                                                                    CONSTRAINT         0.000                  0.000  1       
OSCA001.OSCA_inst/HFCLKOUT                OSC_CORE_OSC_CORE_R1C137  CLOCK LATENCY      0.000                  0.000  324     
top_reveal_coretop_instance/core0/tm_u/secured_instance_1_105/secured_signal_0_141
                                                                    NET DELAY          1.921                  1.921  324     
{top_reveal_coretop_instance/core0/trig_u/tu_0/secured_instance_14_23/CLK   top_reveal_coretop_instance/core0/trig_u/tu_0/secured_instance_14_24/CLK}
                                                                    CLOCK PIN          0.000                  1.921  1       
                                                                    Uncertainty        0.000                  1.921  
                                                                    Common Path Skew  -0.113                  1.808  
                                                                    Hold time          0.094                  1.902  
----------------------------------------  ------------------------  ----------------  ------  ---------------------  ------  
Required Time                                                                                                -1.902  
Arrival Time                                                                                                  2.069  
----------------------------------------  ------------------------  ----------------  ------  ---------------------  ------  
Path Slack  (Passed)                                                                                          0.167  




++++ Path 7 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 

Path Begin       : top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_485/Q  (SLICE_R45C112C)
Path End         : top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_486/DF  (SLICE_R45C112C)
Source Clock     : clk150 (R)
Destination Clock: clk150 (R)
Logic Level      : 1
Delay Ratio      : 31.4% (route), 68.6% (logic)
Clock Skew       : 0.113 ns 
Hold Constraint  : 0.000 ns 
Common Path Skew : -0.113 ns 
Path Slack       : 0.167 ns  (Passed)


Source Clock Path
Name                                      Cell/Site Name            Delay Name        Incr    Arrival/Required Time  Fanout  
----------------------------------------  ------------------------  ----------------  ------  ---------------------  ------  
OSCA001.OSCA_inst/HFCLKOUT                OSC_CORE_OSC_CORE_R1C137  CLOCK LATENCY      0.000                  0.000  324     
top_reveal_coretop_instance/core0/tm_u/secured_instance_1_105/secured_signal_0_141
                                                                    NET DELAY          1.808                  1.808  324     
{top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_486/CLK   top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_485/CLK}
                                                                    CLOCK PIN          0.000                  1.808  1       


Data Path
Name                                      Cell/Site Name            Delay Name        Incr    Arrival/Required Time  Fanout  
----------------------------------------  ------------------------  ----------------  ------  ---------------------  ------  
top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_485/CLK->top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_485/Q
                                          SLICE_R45C112C            REG_DEL            0.179                  1.987  2       
top_reveal_coretop_instance/core0/jtag_int_u/secured_signal_2_160
                                                                    NET DELAY          0.082                  2.069  2       
top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_486/DF
                                                                    ENDPOINT           0.000                  2.069  1       


Destination Clock Path
Name                                      Cell/Site Name            Delay Name        Incr    Arrival/Required Time  Fanout  
----------------------------------------  ------------------------  ----------------  ------  ---------------------  ------  
                                                                    CONSTRAINT         0.000                  0.000  1       
OSCA001.OSCA_inst/HFCLKOUT                OSC_CORE_OSC_CORE_R1C137  CLOCK LATENCY      0.000                  0.000  324     
top_reveal_coretop_instance/core0/tm_u/secured_instance_1_105/secured_signal_0_141
                                                                    NET DELAY          1.921                  1.921  324     
{top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_486/CLK   top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_485/CLK}
                                                                    CLOCK PIN          0.000                  1.921  1       
                                                                    Uncertainty        0.000                  1.921  
                                                                    Common Path Skew  -0.113                  1.808  
                                                                    Hold time          0.094                  1.902  
----------------------------------------  ------------------------  ----------------  ------  ---------------------  ------  
Required Time                                                                                                -1.902  
Arrival Time                                                                                                  2.069  
----------------------------------------  ------------------------  ----------------  ------  ---------------------  ------  
Path Slack  (Passed)                                                                                          0.167  




++++ Path 8 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 

Path Begin       : top_reveal_coretop_instance/core0/trig_u/tu_1/secured_instance_13_138/Q  (SLICE_R40C105B)
Path End         : top_reveal_coretop_instance/core0/trig_u/tu_1/secured_instance_13_122/DF  (SLICE_R40C105C)
Source Clock     : clk150 (R)
Destination Clock: clk150 (R)
Logic Level      : 1
Delay Ratio      : 32.6% (route), 67.4% (logic)
Clock Skew       : 0.113 ns 
Hold Constraint  : 0.000 ns 
Common Path Skew : -0.111 ns 
Path Slack       : 0.168 ns  (Passed)


Source Clock Path
Name                                      Cell/Site Name            Delay Name        Incr    Arrival/Required Time  Fanout  
----------------------------------------  ------------------------  ----------------  ------  ---------------------  ------  
OSCA001.OSCA_inst/HFCLKOUT                OSC_CORE_OSC_CORE_R1C137  CLOCK LATENCY      0.000                  0.000  324     
top_reveal_coretop_instance/core0/tm_u/secured_instance_1_105/secured_signal_0_141
                                                                    NET DELAY          1.808                  1.808  324     
top_reveal_coretop_instance/core0/trig_u/tu_1/secured_instance_13_138/CLK
                                                                    CLOCK PIN          0.000                  1.808  1       


Data Path
Name                                      Cell/Site Name            Delay Name        Incr    Arrival/Required Time  Fanout  
----------------------------------------  ------------------------  ----------------  ------  ---------------------  ------  
top_reveal_coretop_instance/core0/trig_u/tu_1/secured_instance_13_138/CLK->top_reveal_coretop_instance/core0/trig_u/tu_1/secured_instance_13_138/Q
                                          SLICE_R40C105B            REG_DEL            0.178                  1.986  5       
top_reveal_coretop_instance/core0/trig_u/tu_1/secured_signal_13_138
                                                                    NET DELAY          0.086                  2.072  5       
top_reveal_coretop_instance/core0/trig_u/tu_1/secured_instance_13_122/DF
                                                                    ENDPOINT           0.000                  2.072  1       


Destination Clock Path
Name                                      Cell/Site Name            Delay Name        Incr    Arrival/Required Time  Fanout  
----------------------------------------  ------------------------  ----------------  ------  ---------------------  ------  
                                                                    CONSTRAINT         0.000                  0.000  1       
OSCA001.OSCA_inst/HFCLKOUT                OSC_CORE_OSC_CORE_R1C137  CLOCK LATENCY      0.000                  0.000  324     
top_reveal_coretop_instance/core0/tm_u/secured_instance_1_105/secured_signal_0_141
                                                                    NET DELAY          1.921                  1.921  324     
{top_reveal_coretop_instance/core0/trig_u/tu_1/secured_instance_13_121/CLK   top_reveal_coretop_instance/core0/trig_u/tu_1/secured_instance_13_122/CLK}
                                                                    CLOCK PIN          0.000                  1.921  1       
                                                                    Uncertainty        0.000                  1.921  
                                                                    Common Path Skew  -0.111                  1.810  
                                                                    Hold time          0.094                  1.904  
----------------------------------------  ------------------------  ----------------  ------  ---------------------  ------  
Required Time                                                                                                -1.904  
Arrival Time                                                                                                  2.072  
----------------------------------------  ------------------------  ----------------  ------  ---------------------  ------  
Path Slack  (Passed)                                                                                          0.168  




++++ Path 9 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 

Path Begin       : top_reveal_coretop_instance/core0/trig_u/tu_4/secured_instance_10_140/Q  (SLICE_R36C111C)
Path End         : top_reveal_coretop_instance/core0/trig_u/tu_4/secured_instance_10_124/DF  (SLICE_R36C111A)
Source Clock     : clk150 (R)
Destination Clock: clk150 (R)
Logic Level      : 1
Delay Ratio      : 32.6% (route), 67.4% (logic)
Clock Skew       : 0.113 ns 
Hold Constraint  : 0.000 ns 
Common Path Skew : -0.111 ns 
Path Slack       : 0.168 ns  (Passed)


Source Clock Path
Name                                      Cell/Site Name            Delay Name        Incr    Arrival/Required Time  Fanout  
----------------------------------------  ------------------------  ----------------  ------  ---------------------  ------  
OSCA001.OSCA_inst/HFCLKOUT                OSC_CORE_OSC_CORE_R1C137  CLOCK LATENCY      0.000                  0.000  324     
top_reveal_coretop_instance/core0/tm_u/secured_instance_1_105/secured_signal_0_141
                                                                    NET DELAY          1.808                  1.808  324     
top_reveal_coretop_instance/core0/trig_u/tu_4/secured_instance_10_140/CLK
                                                                    CLOCK PIN          0.000                  1.808  1       


Data Path
Name                                      Cell/Site Name            Delay Name        Incr    Arrival/Required Time  Fanout  
----------------------------------------  ------------------------  ----------------  ------  ---------------------  ------  
top_reveal_coretop_instance/core0/trig_u/tu_4/secured_instance_10_140/CLK->top_reveal_coretop_instance/core0/trig_u/tu_4/secured_instance_10_140/Q
                                          SLICE_R36C111C            REG_DEL            0.178                  1.986  5       
top_reveal_coretop_instance/core0/trig_u/tu_4/secured_signal_10_140
                                                                    NET DELAY          0.086                  2.072  5       
top_reveal_coretop_instance/core0/trig_u/tu_4/secured_instance_10_124/DF
                                                                    ENDPOINT           0.000                  2.072  1       


Destination Clock Path
Name                                      Cell/Site Name            Delay Name        Incr    Arrival/Required Time  Fanout  
----------------------------------------  ------------------------  ----------------  ------  ---------------------  ------  
                                                                    CONSTRAINT         0.000                  0.000  1       
OSCA001.OSCA_inst/HFCLKOUT                OSC_CORE_OSC_CORE_R1C137  CLOCK LATENCY      0.000                  0.000  324     
top_reveal_coretop_instance/core0/tm_u/secured_instance_1_105/secured_signal_0_141
                                                                    NET DELAY          1.921                  1.921  324     
{top_reveal_coretop_instance/core0/trig_u/tu_4/secured_instance_10_123/CLK   top_reveal_coretop_instance/core0/trig_u/tu_4/secured_instance_10_124/CLK}
                                                                    CLOCK PIN          0.000                  1.921  1       
                                                                    Uncertainty        0.000                  1.921  
                                                                    Common Path Skew  -0.111                  1.810  
                                                                    Hold time          0.094                  1.904  
----------------------------------------  ------------------------  ----------------  ------  ---------------------  ------  
Required Time                                                                                                -1.904  
Arrival Time                                                                                                  2.072  
----------------------------------------  ------------------------  ----------------  ------  ---------------------  ------  
Path Slack  (Passed)                                                                                          0.168  




++++ Path 10 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 

Path Begin       : top_reveal_coretop_instance/core0/trig_u/tu_3/secured_instance_11_136/Q  (SLICE_R34C109A)
Path End         : top_reveal_coretop_instance/core0/trig_u/tu_3/secured_instance_11_120/DF  (SLICE_R34C109D)
Source Clock     : clk150 (R)
Destination Clock: clk150 (R)
Logic Level      : 1
Delay Ratio      : 33.1% (route), 66.9% (logic)
Clock Skew       : 0.113 ns 
Hold Constraint  : 0.000 ns 
Common Path Skew : -0.111 ns 
Path Slack       : 0.170 ns  (Passed)


Source Clock Path
Name                                      Cell/Site Name            Delay Name        Incr    Arrival/Required Time  Fanout  
----------------------------------------  ------------------------  ----------------  ------  ---------------------  ------  
OSCA001.OSCA_inst/HFCLKOUT                OSC_CORE_OSC_CORE_R1C137  CLOCK LATENCY      0.000                  0.000  324     
top_reveal_coretop_instance/core0/tm_u/secured_instance_1_105/secured_signal_0_141
                                                                    NET DELAY          1.808                  1.808  324     
top_reveal_coretop_instance/core0/trig_u/tu_3/secured_instance_11_136/CLK
                                                                    CLOCK PIN          0.000                  1.808  1       


Data Path
Name                                      Cell/Site Name            Delay Name        Incr    Arrival/Required Time  Fanout  
----------------------------------------  ------------------------  ----------------  ------  ---------------------  ------  
top_reveal_coretop_instance/core0/trig_u/tu_3/secured_instance_11_136/CLK->top_reveal_coretop_instance/core0/trig_u/tu_3/secured_instance_11_136/Q
                                          SLICE_R34C109A            REG_DEL            0.178                  1.986  5       
top_reveal_coretop_instance/core0/trig_u/tu_3/secured_signal_11_136
                                                                    NET DELAY          0.088                  2.074  5       
top_reveal_coretop_instance/core0/trig_u/tu_3/secured_instance_11_120/DF
                                                                    ENDPOINT           0.000                  2.074  1       


Destination Clock Path
Name                                      Cell/Site Name            Delay Name        Incr    Arrival/Required Time  Fanout  
----------------------------------------  ------------------------  ----------------  ------  ---------------------  ------  
                                                                    CONSTRAINT         0.000                  0.000  1       
OSCA001.OSCA_inst/HFCLKOUT                OSC_CORE_OSC_CORE_R1C137  CLOCK LATENCY      0.000                  0.000  324     
top_reveal_coretop_instance/core0/tm_u/secured_instance_1_105/secured_signal_0_141
                                                                    NET DELAY          1.921                  1.921  324     
{top_reveal_coretop_instance/core0/trig_u/tu_3/secured_instance_11_119/CLK   top_reveal_coretop_instance/core0/trig_u/tu_3/secured_instance_11_120/CLK}
                                                                    CLOCK PIN          0.000                  1.921  1       
                                                                    Uncertainty        0.000                  1.921  
                                                                    Common Path Skew  -0.111                  1.810  
                                                                    Hold time          0.094                  1.904  
----------------------------------------  ------------------------  ----------------  ------  ---------------------  ------  
Required Time                                                                                                -1.904  
Arrival Time                                                                                                  2.074  
----------------------------------------  ------------------------  ----------------  ------  ---------------------  ------  
Path Slack  (Passed)                                                                                          0.170  



+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 
                    End of Detailed Report for timing paths 
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 


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