Running in Lattice mode Synplify Pro (R) Version V-2023.09LR-1 for win64 - May 14, 2024 Copyright (c) 1988 - 2024 Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, or distribution of this software is strictly prohibited. Licensed Products communicate with Synopsys servers for the purpose of providing software updates, detecting software piracy and verifying that customers are using Licensed Products in conformity with the applicable License Key for such Licensed Products. Synopsys will use information gathered in connection with this process to deliver software updates and pursue software pirates and infringers. Inclusivity & Diversity - Visit SolvNetPlus to read the "Synopsys Statement on Inclusivity and Diversity" (Refer to article 000036315 at https://solvnetplus.synopsys.com) Starting: C:\lscc\radiant\2024.1\synpbase\bin64\mbin\synbatch.exe Install: C:\lscc\radiant\2024.1\synpbase Hostname: LPGL109135 Date: Thu Sep 5 14:20:31 2024 Version: V-2023.09LR-1 Arguments: -product synplify_base -batch LAB04_imp1_synplify.tcl ProductType: synplify_pro log file: "C:\Users\qnoor\Downloads\LAB02_Prop_Circuit_ARST\LAB02_Prop_Circuit_ARST\imp1\LAB04_imp1.srr" Running: hdl_info_gen in foreground Generating HDL info... Copied C:\Users\qnoor\Downloads\LAB02_Prop_Circuit_ARST\LAB02_Prop_Circuit_ARST\imp1\LAB04_imp1.srr to C:\Users\qnoor\Downloads\LAB02_Prop_Circuit_ARST\LAB02_Prop_Circuit_ARST\imp1\LAB04_imp1.srf hdl_info_gen completed # Thu Sep 5 14:20:32 2024 Return Code: 0 Run Time:00h:00m:00s log file: "C:\Users\qnoor\Downloads\LAB02_Prop_Circuit_ARST\LAB02_Prop_Circuit_ARST\imp1\LAB04_imp1.srr" Running: imp1 in foreground Running proj_1|imp1 Running Flow: compile (Compile) on proj_1|imp1 # Thu Sep 5 14:20:33 2024 Running Flow: compile_flow (Compile Process) on proj_1|imp1 # Thu Sep 5 14:20:33 2024 Running: compiler (Compile Input) on proj_1|imp1 # Thu Sep 5 14:20:33 2024 Copied C:\Users\qnoor\Downloads\LAB02_Prop_Circuit_ARST\LAB02_Prop_Circuit_ARST\imp1\synwork\LAB04_imp1_comp.srs to C:\Users\qnoor\Downloads\LAB02_Prop_Circuit_ARST\LAB02_Prop_Circuit_ARST\imp1\LAB04_imp1.srs compiler completed # Thu Sep 5 14:20:45 2024 Return Code: 0 Run Time:00h:00m:11s Running: multi_srs_gen (Multi-srs Generator) on proj_1|imp1 # Thu Sep 5 14:20:45 2024 multi_srs_gen completed # Thu Sep 5 14:20:46 2024 Return Code: 0 Run Time:00h:00m:01s Copied C:\Users\qnoor\Downloads\LAB02_Prop_Circuit_ARST\LAB02_Prop_Circuit_ARST\imp1\synwork\LAB04_imp1_mult.srs to C:\Users\qnoor\Downloads\LAB02_Prop_Circuit_ARST\LAB02_Prop_Circuit_ARST\imp1\LAB04_imp1.srs Copied C:\Users\qnoor\Downloads\LAB02_Prop_Circuit_ARST\LAB02_Prop_Circuit_ARST\imp1\LAB04_imp1.srr to C:\Users\qnoor\Downloads\LAB02_Prop_Circuit_ARST\LAB02_Prop_Circuit_ARST\imp1\LAB04_imp1.srf Complete: Compile Process on proj_1|imp1 Running: premap (Premap) on proj_1|imp1 # Thu Sep 5 14:20:46 2024 premap completed with warnings # Thu Sep 5 14:20:49 2024 Return Code: 1 Run Time:00h:00m:03s Complete: Compile on proj_1|imp1 Running Flow: map (Map) on proj_1|imp1 # Thu Sep 5 14:20:49 2024 License granted for 4 parallel jobs Running: fpga_mapper (Map & Optimize) on proj_1|imp1 # Thu Sep 5 14:20:49 2024