Copyright (C) 1994-2023 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: V-2023.09LR-1 Install: C:\lscc\radiant\2024.1\synpbase OS: Windows 10 or later Hostname: LPGL109135 Implementation : Async_rst # Written on Mon Sep 9 14:38:29 2024 ##### DESIGN INFO ####################################################### Top View: "Top" Constraint File(s): "C:\lscc\radiant\2024.1\scripts\tcl\flow\radiant_synplify_vars.tcl" "C:\Users\qnoor\Downloads\LAB04_Hybrid_2024\LAB04_Hybrid\timingsdc.sdc" ##### SUMMARY ############################################################ Found 0 issues in 0 out of 0 constraints ##### DETAILS ############################################################ Clock Relationships ******************* Starting Ending | rise to rise | fall to fall | rise to fall | fall to rise ------------------------------------------------------------------------------------------------------------------------------------------------------------------- System System | 1000.000 | No paths | No paths | No paths System Top|clk150 | 1000.000 | No paths | No paths | No paths System Top|jtck_inferred_clock | No paths | No paths | 1000.000 | No paths Top|clk150 System | 1000.000 | No paths | No paths | No paths Top|clk150 Top|clk150 | 1000.000 | No paths | No paths | No paths Top|clk150 Top|jtck_inferred_clock | No paths | No paths | Diff grp | No paths Top|jtck_inferred_clock System | No paths | No paths | No paths | 1000.000 Top|jtck_inferred_clock Top|clk150 | No paths | No paths | No paths | Diff grp Top|jtck_inferred_clock Top|jtck_inferred_clock | No paths | 1000.000 | No paths | No paths =================================================================================================================================================================== Note: 'No paths' indicates there are no paths in the design for that pair of clock edges. 'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups. Unconstrained Start/End Points ****************************** p:LED1 p:LED2 p:LED3 p:LED4 p:TCK p:TDI p:TDO p:TMS p:en p:reset Inapplicable constraints ************************ (none) Applicable constraints with issues ********************************** (none) Constraints with matching wildcard expressions ********************************************** (none) Library Report ************** # End of Constraint Checker Report