#Build: Synplify Pro (R) U-2023.03LR-SP1-2, Build 296R, Mar  7 2024
#install: C:\lscc\radiant\2023.2\synpbase
#OS: Windows 10 or later
#Hostname: DESKTOP-CQ0R02Q

# Mon Aug 26 15:06:03 2024

#Implementation: impl_1


Copyright (C) 1994-2023 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: U-2023.03LR-SP1-2
Install: C:\lscc\radiant\2023.2\synpbase
OS: Windows 10 or later
Hostname: DESKTOP-CQ0R02Q

Implementation : impl_1
Synopsys HDL Compiler, Version comp202303synp1, Build 300R, Built Mar  7 2024 08:13:58, @

@N: :  | Running in 64-bit mode 
###########################################################[

Copyright (C) 1994-2023 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: U-2023.03LR-SP1-2
Install: C:\lscc\radiant\2023.2\synpbase
OS: Windows 10 or later
Hostname: DESKTOP-CQ0R02Q

Implementation : impl_1
Synopsys VHDL Compiler, Version comp202303synp1, Build 300R, Built Mar  7 2024 08:13:58, @

@N: :  | Running in 64-bit mode 
@N: : top.vhd(7) | Top entity is set to top_level.
@N:CD140 :  | Using the VHDL 1993 Standard for file 'C:\lscc\radiant\2023.2\ip\pmi\pmi_lfcpnx.vhd'. 
@N:CD140 :  | Using the VHDL 1993 Standard for file 'D:\02_LSCC\13_VHDL\LAB05\LAB05\source\impl_1\FSM.vhd'. 
@N:CD140 :  | Using the VHDL 1993 Standard for file 'D:\02_LSCC\13_VHDL\LAB05\LAB05\source\impl_1\MyPackage.vhd'. 
@N:CD140 :  | Using the VHDL 1993 Standard for file 'D:\02_LSCC\13_VHDL\LAB05\LAB05\source\impl_1\Decoder_7Seg.vhd'. 
@N:CD140 :  | Using the VHDL 1993 Standard for file 'C:\lscc\radiant\2023.2\cae_library\synthesis\vhdl\lfcpnx.vhd'. 
@N:CD140 :  | Using the VHDL 1993 Standard for file 'D:\02_LSCC\13_VHDL\LAB05\LAB05\source\impl_1\CNT24.vhd'. 
@N:CD140 :  | Using the VHDL 1993 Standard for file 'D:\02_LSCC\13_VHDL\LAB05\LAB05\source\impl_1\top.vhd'. 
VHDL syntax check successful!

At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 102MB peak: 102MB)


Process completed successfully.
# Mon Aug 26 15:06:03 2024

###########################################################]
###########################################################[

Copyright (C) 1994-2023 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: U-2023.03LR-SP1-2
Install: C:\lscc\radiant\2023.2\synpbase
OS: Windows 10 or later
Hostname: DESKTOP-CQ0R02Q

Implementation : impl_1
Synopsys Verilog Compiler, Version comp202303synp1, Build 300R, Built Mar  7 2024 08:13:58, @

@N: :  | Running in 64-bit mode 
@I::"C:\lscc\radiant\2023.2\synpbase\lib\lucent\lfcpnx.v" (library work)
@I::"C:\lscc\radiant\2023.2\synpbase\lib\lucent\pmi_def.v" (library work)
@I::"C:\lscc\radiant\2023.2\synpbase\lib\vlog\hypermods.v" (library __hyper__lib__)
@I::"C:\lscc\radiant\2023.2\synpbase\lib\vlog\scemi_objects.v" (library snps_haps)
@I::"C:\lscc\radiant\2023.2\synpbase\lib\vlog\scemi_pipes.svh" (library snps_haps)
@I::"C:\lscc\radiant\2023.2\ip\pmi\pmi_lfcpnx.v" (library work)
@I:"C:\lscc\radiant\2023.2\ip\pmi\pmi_lfcpnx.v":"C:\lscc\radiant\2023.2\ip\pmi\pmi_addsub.v" (library work)
@I:"C:\lscc\radiant\2023.2\ip\pmi\pmi_addsub.v":"C:\lscc\radiant\2023.2\ip\pmi\../common/adder_subtractor/rtl\lscc_add_sub.v" (library work)
@N:CG334 : lscc_add_sub.v(313) | Read directive translate_off.
@N:CG333 : lscc_add_sub.v(333) | Read directive translate_on.
@I:"C:\lscc\radiant\2023.2\ip\pmi\pmi_lfcpnx.v":"C:\lscc\radiant\2023.2\ip\pmi\pmi_add.v" (library work)
@I:"C:\lscc\radiant\2023.2\ip\pmi\pmi_add.v":"C:\lscc\radiant\2023.2\ip\pmi\../common/adder/rtl\lscc_adder.v" (library work)
@I:"C:\lscc\radiant\2023.2\ip\pmi\pmi_lfcpnx.v":"C:\lscc\radiant\2023.2\ip\pmi\pmi_complex_mult.v" (library work)
@I:"C:\lscc\radiant\2023.2\ip\pmi\pmi_complex_mult.v":"C:\lscc\radiant\2023.2\ip\pmi\../common/complex_mult/rtl\lscc_complex_mult.v" (library work)
@N:CG334 : pmi_complex_mult.v(92) | Read directive translate_off.
@N:CG333 : pmi_complex_mult.v(101) | Read directive translate_on.
@I:"C:\lscc\radiant\2023.2\ip\pmi\pmi_lfcpnx.v":"C:\lscc\radiant\2023.2\ip\pmi\pmi_counter.v" (library work)
@I:"C:\lscc\radiant\2023.2\ip\pmi\pmi_counter.v":"C:\lscc\radiant\2023.2\ip\pmi\../common/counter/rtl\lscc_cntr.v" (library work)
@N:CG334 : lscc_cntr.v(129) | Read directive translate_off.
@N:CG333 : lscc_cntr.v(143) | Read directive translate_on.
@I:"C:\lscc\radiant\2023.2\ip\pmi\pmi_lfcpnx.v":"C:\lscc\radiant\2023.2\ip\pmi\pmi_distributed_dpram.v" (library work)
@I:"C:\lscc\radiant\2023.2\ip\pmi\pmi_distributed_dpram.v":"C:\lscc\radiant\2023.2\ip\pmi\../common/distributed_dpram/rtl\lscc_distributed_dpram.v" (library work)
@I:"C:\lscc\radiant\2023.2\ip\pmi\pmi_lfcpnx.v":"C:\lscc\radiant\2023.2\ip\pmi\pmi_distributed_spram.v" (library work)
@I:"C:\lscc\radiant\2023.2\ip\pmi\pmi_distributed_spram.v":"C:\lscc\radiant\2023.2\ip\pmi\../common/distributed_spram/rtl\lscc_distributed_spram.v" (library work)
@I:"C:\lscc\radiant\2023.2\ip\pmi\pmi_lfcpnx.v":"C:\lscc\radiant\2023.2\ip\pmi\pmi_distributed_rom.v" (library work)
@I:"C:\lscc\radiant\2023.2\ip\pmi\pmi_distributed_rom.v":"C:\lscc\radiant\2023.2\ip\pmi\../common/distributed_rom/rtl\lscc_distributed_rom.v" (library work)
@I:"C:\lscc\radiant\2023.2\ip\pmi\pmi_lfcpnx.v":"C:\lscc\radiant\2023.2\ip\pmi\pmi_distributed_shift_reg.v" (library work)
@I:"C:\lscc\radiant\2023.2\ip\pmi\pmi_distributed_shift_reg.v":"C:\lscc\radiant\2023.2\ip\pmi\../common/ram_shift_reg/rtl\lscc_shift_register.v" (library work)
@N:CG334 : pmi_distributed_shift_reg.v(126) | Read directive translate_off.
@N:CG333 : pmi_distributed_shift_reg.v(135) | Read directive translate_on.
@I:"C:\lscc\radiant\2023.2\ip\pmi\pmi_lfcpnx.v":"C:\lscc\radiant\2023.2\ip\pmi\pmi_fifo.v" (library work)
@I:"C:\lscc\radiant\2023.2\ip\pmi\pmi_fifo.v":"C:\lscc\radiant\2023.2\ip\pmi\../avant/fifo/rtl\lscc_fifo.v" (library work)
@N:CG334 : lscc_fifo.v(3260) | Read directive translate_off.
@N:CG333 : lscc_fifo.v(3267) | Read directive translate_on.
@I:"C:\lscc\radiant\2023.2\ip\pmi\pmi_lfcpnx.v":"C:\lscc\radiant\2023.2\ip\pmi\pmi_fifo_dc.v" (library work)
@I:"C:\lscc\radiant\2023.2\ip\pmi\pmi_fifo_dc.v":"C:\lscc\radiant\2023.2\ip\pmi\../avant/fifo_dc/rtl\lscc_fifo_dc.v" (library work)
@N:CG334 : lscc_fifo_dc.v(4898) | Read directive translate_off.
@N:CG333 : lscc_fifo_dc.v(4902) | Read directive translate_on.
@N:CG334 : lscc_fifo_dc.v(4933) | Read directive translate_off.
@N:CG333 : lscc_fifo_dc.v(4937) | Read directive translate_on.
@I:"C:\lscc\radiant\2023.2\ip\pmi\pmi_lfcpnx.v":"C:\lscc\radiant\2023.2\ip\pmi\pmi_mac.v" (library work)
@I:"C:\lscc\radiant\2023.2\ip\pmi\pmi_mac.v":"C:\lscc\radiant\2023.2\ip\pmi\../common/mult_accumulate/rtl\lscc_mult_accumulate.v" (library work)
@N:CG334 : pmi_mac.v(94) | Read directive translate_off.
@N:CG333 : pmi_mac.v(109) | Read directive translate_on.
@I:"C:\lscc\radiant\2023.2\ip\pmi\pmi_lfcpnx.v":"C:\lscc\radiant\2023.2\ip\pmi\pmi_multaddsubsum.v" (library work)
@I:"C:\lscc\radiant\2023.2\ip\pmi\pmi_multaddsubsum.v":"C:\lscc\radiant\2023.2\ip\pmi\../common/mult_add_sub_sum/rtl\lscc_mult_add_sub_sum.v" (library work)
@N:CG334 : lscc_mult_add_sub_sum.v(210) | Read directive translate_off.
@N:CG333 : lscc_mult_add_sub_sum.v(227) | Read directive translate_on.
@N:CG334 : pmi_multaddsubsum.v(84) | Read directive translate_off.
@N:CG333 : pmi_multaddsubsum.v(93) | Read directive translate_on.
@I:"C:\lscc\radiant\2023.2\ip\pmi\pmi_lfcpnx.v":"C:\lscc\radiant\2023.2\ip\pmi\pmi_multaddsub.v" (library work)
@I:"C:\lscc\radiant\2023.2\ip\pmi\pmi_multaddsub.v":"C:\lscc\radiant\2023.2\ip\pmi\../common/mult_add_sub/rtl\lscc_mult_add_sub.v" (library work)
@N:CG334 : pmi_multaddsub.v(91) | Read directive translate_off.
@N:CG333 : pmi_multaddsub.v(100) | Read directive translate_on.
@I:"C:\lscc\radiant\2023.2\ip\pmi\pmi_lfcpnx.v":"C:\lscc\radiant\2023.2\ip\pmi\pmi_mult.v" (library work)
@I:"C:\lscc\radiant\2023.2\ip\pmi\pmi_mult.v":"C:\lscc\radiant\2023.2\ip\pmi\../common/multiplier/rtl\lscc_multiplier.v" (library work)
@N:CG334 : pmi_mult.v(87) | Read directive translate_off.
@N:CG333 : pmi_mult.v(96) | Read directive translate_on.
@I:"C:\lscc\radiant\2023.2\ip\pmi\pmi_lfcpnx.v":"C:\lscc\radiant\2023.2\ip\pmi\pmi_ram_dp.v" (library work)
@I:"C:\lscc\radiant\2023.2\ip\pmi\pmi_ram_dp.v":"C:\lscc\radiant\2023.2\ip\pmi\../avant/ram_dp/rtl\lscc_ram_dp.v" (library work)
@N:CG334 : lscc_ram_dp.v(1060) | Read directive translate_off.
@N:CG333 : lscc_ram_dp.v(1064) | Read directive translate_on.
@N:CG334 : lscc_ram_dp.v(1095) | Read directive translate_off.
@N:CG333 : lscc_ram_dp.v(1099) | Read directive translate_on.
@I:"C:\lscc\radiant\2023.2\ip\pmi\pmi_lfcpnx.v":"C:\lscc\radiant\2023.2\ip\pmi\pmi_ram_dp_be.v" (library work)
@N:CG334 : pmi_ram_dp_be.v(146) | Read directive translate_off.
@N:CG333 : pmi_ram_dp_be.v(155) | Read directive translate_on.
@I:"C:\lscc\radiant\2023.2\ip\pmi\pmi_lfcpnx.v":"C:\lscc\radiant\2023.2\ip\pmi\pmi_ram_dp_true.v" (library work)
@I:"C:\lscc\radiant\2023.2\ip\pmi\pmi_ram_dp_true.v":"C:\lscc\radiant\2023.2\ip\pmi\../avant/ram_dp_true/rtl\lscc_ram_dp_true.v" (library work)
@N:CG334 : lscc_ram_dp_true.v(1880) | Read directive translate_off.
@N:CG333 : lscc_ram_dp_true.v(1885) | Read directive translate_on.
@N:CG334 : lscc_ram_dp_true.v(1916) | Read directive translate_off.
@N:CG333 : lscc_ram_dp_true.v(1920) | Read directive translate_on.
@N:CG334 : lscc_ram_dp_true.v(1953) | Read directive translate_off.
@N:CG333 : lscc_ram_dp_true.v(1958) | Read directive translate_on.
@N:CG334 : lscc_ram_dp_true.v(1988) | Read directive translate_off.
@N:CG333 : lscc_ram_dp_true.v(1992) | Read directive translate_on.
@N:CG334 : lscc_ram_dp_true.v(2508) | Read directive translate_off.
@N:CG333 : lscc_ram_dp_true.v(2513) | Read directive translate_on.
@N:CG334 : lscc_ram_dp_true.v(2544) | Read directive translate_off.
@N:CG333 : lscc_ram_dp_true.v(2548) | Read directive translate_on.
@N:CG334 : lscc_ram_dp_true.v(2581) | Read directive translate_off.
@N:CG333 : lscc_ram_dp_true.v(2586) | Read directive translate_on.
@N:CG334 : lscc_ram_dp_true.v(2617) | Read directive translate_off.
@N:CG333 : lscc_ram_dp_true.v(2621) | Read directive translate_on.
@N:CG334 : lscc_ram_dp_true.v(3108) | Read directive translate_off.
@N:CG333 : lscc_ram_dp_true.v(3113) | Read directive translate_on.
@N:CG334 : lscc_ram_dp_true.v(3144) | Read directive translate_off.
@N:CG333 : lscc_ram_dp_true.v(3148) | Read directive translate_on.
@N:CG334 : lscc_ram_dp_true.v(3181) | Read directive translate_off.
@N:CG333 : lscc_ram_dp_true.v(3186) | Read directive translate_on.
@N:CG334 : lscc_ram_dp_true.v(3217) | Read directive translate_off.
@N:CG333 : lscc_ram_dp_true.v(3221) | Read directive translate_on.
@I:"C:\lscc\radiant\2023.2\ip\pmi\pmi_lfcpnx.v":"C:\lscc\radiant\2023.2\ip\pmi\pmi_ram_dq.v" (library work)
@I:"C:\lscc\radiant\2023.2\ip\pmi\pmi_ram_dq.v":"C:\lscc\radiant\2023.2\ip\pmi\../avant/ram_dq/rtl\lscc_ram_dq.v" (library work)
@N:CG334 : lscc_ram_dq.v(1485) | Read directive translate_off.
@N:CG333 : lscc_ram_dq.v(1491) | Read directive translate_on.
@I:"C:\lscc\radiant\2023.2\ip\pmi\pmi_lfcpnx.v":"C:\lscc\radiant\2023.2\ip\pmi\pmi_ram_dq_be.v" (library work)
@N:CG334 : pmi_ram_dq_be.v(87) | Read directive translate_off.
@N:CG333 : pmi_ram_dq_be.v(95) | Read directive translate_on.
@I:"C:\lscc\radiant\2023.2\ip\pmi\pmi_lfcpnx.v":"C:\lscc\radiant\2023.2\ip\pmi\pmi_rom.v" (library work)
@I:"C:\lscc\radiant\2023.2\ip\pmi\pmi_rom.v":"C:\lscc\radiant\2023.2\ip\pmi\../avant/rom/rtl\lscc_rom.v" (library work)
@N:CG334 : lscc_rom.v(970) | Read directive translate_off.
@N:CG333 : lscc_rom.v(976) | Read directive translate_on.
@I:"C:\lscc\radiant\2023.2\ip\pmi\pmi_lfcpnx.v":"C:\lscc\radiant\2023.2\ip\pmi\pmi_sub.v" (library work)
@I:"C:\lscc\radiant\2023.2\ip\pmi\pmi_sub.v":"C:\lscc\radiant\2023.2\ip\pmi\../common/subtractor/rtl\lscc_subtractor.v" (library work)
Verilog syntax check successful!

At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 131MB peak: 131MB)


Process completed successfully.
# Mon Aug 26 15:06:04 2024

###########################################################]
###########################################################[
@N: : top.vhd(7) | Top entity is set to top_level.
File D:\02_LSCC\13_VHDL\LAB05\LAB05\source\impl_1\CNT24.vhd changed - recompiling
File D:\02_LSCC\13_VHDL\LAB05\LAB05\source\impl_1\FSM.vhd changed - recompiling
File D:\02_LSCC\13_VHDL\LAB05\LAB05\source\impl_1\MyPackage.vhd changed - recompiling
File D:\02_LSCC\13_VHDL\LAB05\LAB05\source\impl_1\Decoder_7Seg.vhd changed - recompiling
File C:\lscc\radiant\2023.2\cae_library\synthesis\vhdl\lfcpnx.vhd changed - recompiling
@N:CD140 :  | Using the VHDL 1993 Standard for file 'C:\lscc\radiant\2023.2\ip\pmi\pmi_lfcpnx.vhd'. 
@N:CD140 :  | Using the VHDL 1993 Standard for file 'D:\02_LSCC\13_VHDL\LAB05\LAB05\source\impl_1\FSM.vhd'. 
@N:CD140 :  | Using the VHDL 1993 Standard for file 'D:\02_LSCC\13_VHDL\LAB05\LAB05\source\impl_1\MyPackage.vhd'. 
@N:CD140 :  | Using the VHDL 1993 Standard for file 'D:\02_LSCC\13_VHDL\LAB05\LAB05\source\impl_1\Decoder_7Seg.vhd'. 
@N:CD140 :  | Using the VHDL 1993 Standard for file 'C:\lscc\radiant\2023.2\cae_library\synthesis\vhdl\lfcpnx.vhd'. 
@N:CD140 :  | Using the VHDL 1993 Standard for file 'D:\02_LSCC\13_VHDL\LAB05\LAB05\source\impl_1\CNT24.vhd'. 
@N:CD140 :  | Using the VHDL 1993 Standard for file 'D:\02_LSCC\13_VHDL\LAB05\LAB05\source\impl_1\top.vhd'. 
VHDL syntax check successful!
File D:\02_LSCC\13_VHDL\LAB05\LAB05\source\impl_1\CNT24.vhd changed - recompiling
File D:\02_LSCC\13_VHDL\LAB05\LAB05\source\impl_1\FSM.vhd changed - recompiling
File D:\02_LSCC\13_VHDL\LAB05\LAB05\source\impl_1\MyPackage.vhd changed - recompiling
File D:\02_LSCC\13_VHDL\LAB05\LAB05\source\impl_1\Decoder_7Seg.vhd changed - recompiling
File C:\lscc\radiant\2023.2\cae_library\synthesis\vhdl\lfcpnx.vhd changed - recompiling
@N:CD630 : top.vhd(7) | Synthesizing work.top_level.behavioral.
@W:CD638 : top.vhd(36) | Signal seq_sig is undriven. Either assign the signal a value or remove the signal declaration.
@N:CD630 : Decoder_7Seg.vhd(5) | Synthesizing work.seven_segment_decoder.behavioral.
Post processing for work.seven_segment_decoder.behavioral
Running optimization stage 1 on seven_segment_decoder .......
Finished optimization stage 1 on seven_segment_decoder (CPU Time 0h:00m:00s, Memory Used current: 104MB peak: 105MB)
@N:CD630 : CNT24.vhd(8) | Synthesizing work.gen_cnt.behavioral.
Post processing for work.gen_cnt.behavioral
Running optimization stage 1 on Gen_CNT .......
Finished optimization stage 1 on Gen_CNT (CPU Time 0h:00m:00s, Memory Used current: 104MB peak: 105MB)
@N:CD630 : FSM.vhd(7) | Synthesizing work.counter_fsm.behavioral.
@N:CD233 : FSM.vhd(20) | Using sequential encoding for type state_type.
@N:CD604 : FSM.vhd(50) | OTHERS clause is not synthesized.
Post processing for work.counter_fsm.behavioral
Running optimization stage 1 on counter_fsm .......
Finished optimization stage 1 on counter_fsm (CPU Time 0h:00m:00s, Memory Used current: 104MB peak: 105MB)
Post processing for work.top_level.behavioral
Running optimization stage 1 on top_level .......
Finished optimization stage 1 on top_level (CPU Time 0h:00m:00s, Memory Used current: 104MB peak: 105MB)
Running optimization stage 2 on counter_fsm .......
@N:CL201 : FSM.vhd(27) | Trying to extract state machine for register state.
Extracted state machine for register state
State machine has 4 reachable states with original encodings of:
   00
   01
   10
   11
Finished optimization stage 2 on counter_fsm (CPU Time 0h:00m:00s, Memory Used current: 105MB peak: 105MB)
Running optimization stage 2 on Gen_CNT .......
Finished optimization stage 2 on Gen_CNT (CPU Time 0h:00m:00s, Memory Used current: 105MB peak: 105MB)
Running optimization stage 2 on seven_segment_decoder .......
Finished optimization stage 2 on seven_segment_decoder (CPU Time 0h:00m:00s, Memory Used current: 105MB peak: 105MB)
Running optimization stage 2 on top_level .......
Finished optimization stage 2 on top_level (CPU Time 0h:00m:00s, Memory Used current: 105MB peak: 105MB)

For a summary of runtime per design unit, please see file:
==========================================================
Linked File:  layer0.duruntime



At c_vhdl Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 105MB peak: 105MB)


Process completed successfully.
# Mon Aug 26 15:06:05 2024

###########################################################]
###########################################################[

Copyright (C) 1994-2023 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: U-2023.03LR-SP1-2
Install: C:\lscc\radiant\2023.2\synpbase
OS: Windows 10 or later
Hostname: DESKTOP-CQ0R02Q

Implementation : impl_1
Synopsys Synopsys Netlist Linker, Version comp202303synp1, Build 300R, Built Mar  7 2024 08:13:58, @

@N: :  | Running in 64-bit mode 

At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 90MB peak: 91MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime

Process completed successfully.
# Mon Aug 26 15:06:05 2024

###########################################################]

For a summary of runtime and memory usage for all design units, please see file:
==========================================================
Linked File:  LAB05_impl_1_comp.rt.csv

@END

At c_hdl Exit (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:00s; Memory used current: 23MB peak: 24MB)

Process took 0h:00m:02s realtime, 0h:00m:01s cputime

Process completed successfully.
# Mon Aug 26 15:06:05 2024

###########################################################]


###########################################################[

Copyright (C) 1994-2023 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: U-2023.03LR-SP1-2
Install: C:\lscc\radiant\2023.2\synpbase
OS: Windows 10 or later
Hostname: DESKTOP-CQ0R02Q

Implementation : impl_1
Synopsys Synopsys Netlist Linker, Version comp202303synp1, Build 300R, Built Mar  7 2024 08:13:58, @

@N: :  | Running in 64-bit mode 
File D:\02_LSCC\13_VHDL\LAB05\LAB05\impl_1\synwork\LAB05_impl_1_comp.srs changed - recompiling

At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 91MB peak: 91MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime

Process completed successfully.
# Mon Aug 26 15:06:06 2024

###########################################################]


# Mon Aug 26 15:06:07 2024


Copyright (C) 1994-2023 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: U-2023.03LR-SP1-2
Install: C:\lscc\radiant\2023.2\synpbase
OS: Windows 10 or later
Hostname: DESKTOP-CQ0R02Q

Implementation : impl_1
Synopsys Lattice Technology Pre-mapping, Version map202303lat, Build 248R, Built Mar  7 2024 08:35:47, @


Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 122MB peak: 122MB)


Done reading skeleton netlist (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 127MB peak: 136MB)

Reading constraint file: D:\02_LSCC\13_VHDL\LAB05\LAB05\MySDC.sdc
Linked File:  LAB05_impl_1_scck.rpt
See clock summary report "D:\02_LSCC\13_VHDL\LAB05\LAB05\impl_1\LAB05_impl_1_scck.rpt"
@N:MF916 :  | Option synthesis_strategy=base is enabled.  
@N:MF248 :  | Running in 64-bit mode. 
@N:MF667 :  | Clock conversion disabled. (Command "set_option -fix_gated_and_generated_clocks 0" in the project file.) 

Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 131MB peak: 136MB)


Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 131MB peak: 136MB)


Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 143MB)


Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 145MB)

NConnInternalConnection caching is on

Starting HSTDM IP insertion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 193MB peak: 194MB)


Finished HSTDM IP insertion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 193MB peak: 194MB)


Started DisTri Cleanup (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 193MB peak: 194MB)


Finished DisTri Cleanup (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 193MB peak: 194MB)

Encoding state machine state[0:3] (in view: work.counter_fsm(behavioral))
original code -> new code
   00 -> 00
   01 -> 01
   10 -> 10
   11 -> 11
@N:MO225 : fsm.vhd(27) | There are no possible illegal states for state machine state[0:3] (in view: work.counter_fsm(behavioral)); safe FSM implementation is not required.

Starting clock optimization report phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 195MB peak: 195MB)


Finished clock optimization report phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 196MB peak: 196MB)

@N:FX1184 :  | Applying syn_allowed_resources blockrams=208 on top level netlist top_level  

Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 196MB peak: 196MB)



Clock Summary
******************

          Start     Requested     Requested     Clock        Clock                Clock
Level     Clock     Frequency     Period        Type         Group                Load 
---------------------------------------------------------------------------------------
0 -       clk2      1.0 MHz       1000.000      declared     default_clkgroup     30   
=======================================================================================



Clock Load Summary
***********************

          Clock     Source                   Clock Pin                        Non-clock Pin     Non-clock Pin
Clock     Load      Pin                      Seq Example                      Seq Example       Comb Example 
-------------------------------------------------------------------------------------------------------------
clk2      30        MyOSC.LFCLKOUT(OSCA)     counter_inst.cnt_reg[17:0].C     -                 -            
=============================================================================================================

ICG Latch Removal Summary:
Number of ICG latches removed: 0
Number of ICG latches not removed:	0


@S |Clock Optimization Summary



#### START OF PREMAP CLOCK OPTIMIZATION REPORT #####[

1 non-gated/non-generated clock tree(s) driving 30 clock pin(s) of sequential element(s)
0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
0 instances converted, 0 sequential instances remain driven by gated/generated clocks

================================= Non-Gated/Non-Generated Clocks =================================
Clock Tree ID     Driving Element     Drive Element Type     Fanout     Sample Instance           
--------------------------------------------------------------------------------------------------
ClockId_0_0       MyOSC.LFCLKOUT      OSCA                   30         counter_inst.cnt_reg[17:0]
==================================================================================================


##### END OF CLOCK OPTIMIZATION REPORT ######


Summary of user generated gated clocks:
0 user generated gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)

@N:FX1143 :  | Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized. 
Finished Pre Mapping Phase.

Starting constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 197MB peak: 197MB)


Finished constraint checker preprocessing (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 197MB peak: 197MB)


Finished constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 197MB peak: 197MB)

Pre-mapping successful!

At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 199MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Mon Aug 26 15:06:08 2024

###########################################################]


Map & Optimize Report



# Mon Aug 26 15:06:08 2024


Copyright (C) 1994-2023 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: U-2023.03LR-SP1-2
Install: C:\lscc\radiant\2023.2\synpbase
OS: Windows 10 or later
Hostname: DESKTOP-CQ0R02Q

Implementation : impl_1
Synopsys Lattice Technology Mapper, Version map202303lat, Build 248R, Built Mar  7 2024 08:35:47, @


Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 122MB peak: 122MB)

@N:MF916 :  | Option synthesis_strategy=base is enabled.  
@N:MF248 :  | Running in 64-bit mode. 
@N:MF667 :  | Clock conversion disabled. (Command "set_option -fix_gated_and_generated_clocks 0" in the project file.) 

Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 124MB peak: 136MB)


Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 124MB peak: 136MB)


Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 138MB)


Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)



Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 192MB peak: 192MB)

@N:BZ173 : decoder_7seg.vhd(16) | ROM decoder_inst1.seg_out_1[6:0] (in view: work.top_level(behavioral)) mapped in logic.
@N:BZ173 : decoder_7seg.vhd(16) | ROM decoder_inst1.seg_out_1[6:0] (in view: work.top_level(behavioral)) mapped in logic.
@N:MO106 : decoder_7seg.vhd(16) | Found ROM decoder_inst1.seg_out_1[6:0] (in view: work.top_level(behavioral)) with 16 words by 7 bits.

Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 197MB peak: 197MB)

@N:MO230 : cnt24.vhd(24) | Found up-down counter in view:work.top_level(behavioral) instance counter_inst.cnt_reg[17:0]  

Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 197MB peak: 197MB)


Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 197MB peak: 198MB)


Available hyper_sources - for debug and ip models
	None Found

NConnInternalConnection caching is on

Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 198MB peak: 198MB)


Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 198MB peak: 199MB)


Finished Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 198MB peak: 199MB)


Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 198MB peak: 199MB)

@W:FX474 :  | User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved.  

Finished preparing to map (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 199MB peak: 199MB)


Finished technology mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 199MB peak: 199MB)

Pass		 CPU time		Worst Slack		Luts / Registers
------------------------------------------------------------
   1		0h:00m:00s		   997.88ns		  21 /        30

Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 199MB peak: 200MB)

@N:FX164 :  | The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.   

Finished restoring hierarchy (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 200MB peak: 200MB)


Starting CDBProcessSetClockGroups... (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 200MB peak: 200MB)


Finished with CDBProcessSetClockGroups (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 200MB peak: 200MB)


Start Writing Netlists (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 146MB peak: 200MB)

Writing Analyst data base D:\02_LSCC\13_VHDL\LAB05\LAB05\impl_1\synwork\LAB05_impl_1_m.srm

Finished Writing Netlist Databases (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 200MB peak: 200MB)

Writing Verilog Simulation files

Writing scf file... (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:00s; Memory used current: 202MB peak: 202MB)

@N:BW103 :  | The default time unit for the Synopsys Constraint File (SDC or FDC) is 1ns. 
@N:BW107 :  | Synopsys Constraint File capacitance units using default value of 1pF  

Finished Writing Verilog Simulation files (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:00s; Memory used current: 202MB peak: 202MB)


Finished Writing Netlists (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:00s; Memory used current: 202MB peak: 202MB)


Start final timing analysis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 201MB peak: 202MB)

@W:MT246 : top.vhd(43) | Blackbox OSCA is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
@N:MT615 :  | Found clock clk2 with period 1000.00ns  


##### START OF TIMING REPORT #####[
# Timing report written on Mon Aug 26 15:06:11 2024
#


Top view:               top_level
Requested Frequency:    1.0 MHz
Wire load mode:         top
Paths requested:        5
Constraint File(s):    D:\02_LSCC\13_VHDL\LAB05\LAB05\MySDC.sdc
                       
@N:MT320 :  | This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report. 

@N:MT322 :  | Clock constraints include only register-to-register paths associated with each individual clock. 



Performance Summary
*******************


Worst slack in design: 997.529

                   Requested     Estimated     Requested     Estimated                 Clock        Clock           
Starting Clock     Frequency     Frequency     Period        Period        Slack       Type         Group           
--------------------------------------------------------------------------------------------------------------------
clk2               1.0 MHz       404.6 MHz     1000.000      2.471         997.529     declared     default_clkgroup
====================================================================================================================





Clock Relationships
*******************

Clocks            |    rise  to  rise     |    fall  to  fall   |    rise  to  fall   |    fall  to  rise 
----------------------------------------------------------------------------------------------------------
Starting  Ending  |  constraint  slack    |  constraint  slack  |  constraint  slack  |  constraint  slack
----------------------------------------------------------------------------------------------------------
clk2      clk2    |  1000.000    997.529  |  No paths    -      |  No paths    -      |  No paths    -    
==========================================================================================================
 Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.



Interface Information 
*********************

No IO constraint found



====================================
Detailed Report for Clock: clk2
====================================



Starting Points with Worst Slack
********************************

                             Starting                                         Arrival            
Instance                     Reference     Type        Pin     Net            Time        Slack  
                             Clock                                                               
-------------------------------------------------------------------------------------------------
counter_inst.cnt_reg[0]      clk2          FD1P3DX     Q       cnt_reg[0]     0.753       997.529
counter_inst.cnt_reg[1]      clk2          FD1P3DX     Q       cnt_reg[1]     0.753       997.587
counter_inst.cnt_reg[2]      clk2          FD1P3DX     Q       cnt_reg[2]     0.753       997.587
counter_inst.cnt_reg[3]      clk2          FD1P3DX     Q       cnt_reg[3]     0.753       997.646
counter_inst.cnt_reg[4]      clk2          FD1P3DX     Q       cnt_reg[4]     0.753       997.646
counter_inst.cnt_reg[5]      clk2          FD1P3DX     Q       cnt_reg[5]     0.753       997.706
counter_inst.cnt_reg[6]      clk2          FD1P3DX     Q       cnt_reg[6]     0.753       997.706
counter_inst.cnt_reg[7]      clk2          FD1P3DX     Q       cnt_reg[7]     0.753       997.764
counter_inst.cnt_reg[8]      clk2          FD1P3DX     Q       cnt_reg[8]     0.753       997.764
counter_inst.cnt_reg[14]     clk2          FD1P3DX     Q       count[14]      0.908       997.787
=================================================================================================


Ending Points with Worst Slack
******************************

                             Starting                                            Required            
Instance                     Reference     Type        Pin     Net               Time         Slack  
                             Clock                                                                   
-----------------------------------------------------------------------------------------------------
counter_inst.cnt_reg[17]     clk2          FD1P3DX     D       cnt_reg_s[17]     1000.144     997.529
counter_inst.cnt_reg[15]     clk2          FD1P3DX     D       cnt_reg_s[15]     1000.144     997.587
counter_inst.cnt_reg[16]     clk2          FD1P3DX     D       cnt_reg_s[16]     1000.144     997.587
counter_inst.cnt_reg[13]     clk2          FD1P3DX     D       cnt_reg_s[13]     1000.144     997.646
counter_inst.cnt_reg[14]     clk2          FD1P3DX     D       cnt_reg_s[14]     1000.144     997.646
counter_inst.cnt_reg[11]     clk2          FD1P3DX     D       cnt_reg_s[11]     1000.144     997.706
counter_inst.cnt_reg[12]     clk2          FD1P3DX     D       cnt_reg_s[12]     1000.144     997.706
counter_inst.cnt_reg[9]      clk2          FD1P3DX     D       cnt_reg_s[9]      1000.144     997.764
counter_inst.cnt_reg[10]     clk2          FD1P3DX     D       cnt_reg_s[10]     1000.144     997.764
counter_inst.cnt_reg[7]      clk2          FD1P3DX     D       cnt_reg_s[7]      1000.144     997.823
=====================================================================================================



Worst Path Information
View Worst Path in Analyst
***********************


Path information for path number 1: 
      Requested Period:                      1000.000
    - Setup time:                            -0.144
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         1000.144

    - Propagation time:                      2.615
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (critical) :                     997.529

    Number of logic level(s):                10
    Starting point:                          counter_inst.cnt_reg[0] / Q
    Ending point:                            counter_inst.cnt_reg[17] / D
    The start point is clocked by            clk2 [rising] (rise=0.000 fall=500.000 period=1000.000) on pin CK
    The end   point is clocked by            clk2 [rising] (rise=0.000 fall=500.000 period=1000.000) on pin CK

Instance / Net                                 Pin      Pin               Arrival     No. of    
Name                               Type        Name     Dir     Delay     Time        Fan Out(s)
------------------------------------------------------------------------------------------------
counter_inst.cnt_reg[0]            FD1P3DX     Q        Out     0.753     0.753 r     -         
cnt_reg[0]                         Net         -        -       -         -           1         
counter_inst.cnt_reg_cry_0[0]      CCU2        B1       In      0.000     0.753 r     -         
counter_inst.cnt_reg_cry_0[0]      CCU2        COUT     Out     0.784     1.537 r     -         
cnt_reg_cry[0]                     Net         -        -       -         -           1         
counter_inst.cnt_reg_cry_0[1]      CCU2        CIN      In      0.000     1.537 r     -         
counter_inst.cnt_reg_cry_0[1]      CCU2        COUT     Out     0.059     1.596 r     -         
cnt_reg_cry[2]                     Net         -        -       -         -           1         
counter_inst.cnt_reg_cry_0[3]      CCU2        CIN      In      0.000     1.596 r     -         
counter_inst.cnt_reg_cry_0[3]      CCU2        COUT     Out     0.059     1.655 r     -         
cnt_reg_cry[4]                     Net         -        -       -         -           1         
counter_inst.cnt_reg_cry_0[5]      CCU2        CIN      In      0.000     1.655 r     -         
counter_inst.cnt_reg_cry_0[5]      CCU2        COUT     Out     0.059     1.714 r     -         
cnt_reg_cry[6]                     Net         -        -       -         -           1         
counter_inst.cnt_reg_cry_0[7]      CCU2        CIN      In      0.000     1.714 r     -         
counter_inst.cnt_reg_cry_0[7]      CCU2        COUT     Out     0.059     1.773 r     -         
cnt_reg_cry[8]                     Net         -        -       -         -           1         
counter_inst.cnt_reg_cry_0[9]      CCU2        CIN      In      0.000     1.773 r     -         
counter_inst.cnt_reg_cry_0[9]      CCU2        COUT     Out     0.059     1.832 r     -         
cnt_reg_cry[10]                    Net         -        -       -         -           1         
counter_inst.cnt_reg_cry_0[11]     CCU2        CIN      In      0.000     1.832 r     -         
counter_inst.cnt_reg_cry_0[11]     CCU2        COUT     Out     0.059     1.891 r     -         
cnt_reg_cry[12]                    Net         -        -       -         -           1         
counter_inst.cnt_reg_cry_0[13]     CCU2        CIN      In      0.000     1.891 r     -         
counter_inst.cnt_reg_cry_0[13]     CCU2        COUT     Out     0.059     1.950 r     -         
cnt_reg_cry[14]                    Net         -        -       -         -           1         
counter_inst.cnt_reg_cry_0[15]     CCU2        CIN      In      0.000     1.950 r     -         
counter_inst.cnt_reg_cry_0[15]     CCU2        COUT     Out     0.059     2.009 r     -         
cnt_reg_cry[16]                    Net         -        -       -         -           1         
counter_inst.cnt_reg_s_0[17]       CCU2        CIN      In      0.000     2.009 r     -         
counter_inst.cnt_reg_s_0[17]       CCU2        S0       Out     0.607     2.615 r     -         
cnt_reg_s[17]                      Net         -        -       -         -           1         
counter_inst.cnt_reg[17]           FD1P3DX     D        In      0.000     2.615 r     -         
================================================================================================



##### END OF TIMING REPORT #####]

Timing exceptions that could not be applied

Finished final timing analysis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 201MB peak: 202MB)


Finished timing report (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 201MB peak: 202MB)

---------------------------------------
Resource Usage Report
Part: lfcpnx_100-9

Register bits: 30 of 79872 (0%)
PIC Latch:       0
I/O cells:       12


Details:
CCU2:           10
FD1P3DX:        20
GSR:            1
IB:             2
INV:            2
LUT4:           19
OB:             10
OFD1P3DX:       10
OSCA:           1
VHI:            4
VLO:            4

Resource Usage inside macros:
Registers: 0
LUTs: 0
EBRs: 0
LRAMs: 0
DSPs: 0
Distributed RAMs: 0
Carry Chains: 0
Blackboxes: 0

Mapping Summary:
Total number of registers: 30 + 0 = 30 of 79872 (0.04%)
Total number of LUTs: 19 + 0 = 19 
Total number of EBRs: 0 + 0 = 0 of 208 (0.00%)
Total number of LRAMs: 0 + 0 = 0 of 7 (0.00%)
Total number of DSPs: 0 + 0 = 0 of 156 (0.00%)
Total number of Distributed RAMs: 0 + 0 = 0 
Total number of Carry Chains: 10 + 0 = 10 
Total number of BlackBoxes: 10 + 0 = 10 
Mapper successful!

At Mapper Exit (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 64MB peak: 202MB)

Process took 0h:00m:02s realtime, 0h:00m:01s cputime
# Mon Aug 26 15:06:11 2024

###########################################################]