Copyright (C) 1994-2023 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: U-2023.03LR-SP1-2 Install: C:\lscc\radiant\2023.2\synpbase OS: Windows 10 or later Hostname: DESKTOP-CQ0R02Q Implementation : impl_1 # Written on Wed Aug 21 08:30:05 2024 ##### DESIGN INFO ####################################################### Top View: "seven_segment_decoder" Constraint File(s): (none) ##### SUMMARY ############################################################ Found 0 issues in 0 out of 0 constraints ##### DETAILS ############################################################ Clock Relationships ******************* Starting Ending | rise to rise | fall to fall | rise to fall | fall to rise ----------------------------------------------------------------------------------------------------------------------------------- =================================================================================================================================== Note: 'No paths' indicates there are no paths in the design for that pair of clock edges. 'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups. Unconstrained Start/End Points ****************************** p:binary_in[0] p:binary_in[1] p:binary_in[2] p:binary_in[3] p:seg_out[0] p:seg_out[1] p:seg_out[2] p:seg_out[3] p:seg_out[4] p:seg_out[5] p:seg_out[6] Inapplicable constraints ************************ (none) Applicable constraints with issues ********************************** (none) Constraints with matching wildcard expressions ********************************************** (none) Library Report ************** # End of Constraint Checker Report