Project Settings
Project Name proj_1 Device Name impl_1: Lattice LFCPNX : LFCPNX_100
Implementation Name impl_1 Top Module counter_fsm
Pipelining 1 Retiming 0
Resource Sharing 1 Fanout Guide 1000
Disable I/O Insertion 0 Disable Sequential Optimizations 0
Clock Conversion 0 FSM Compiler 1

Run Status
Job Name Status CPU Time Real Time Memory Date/Time
(compiler)Complete 76 0 0 - 00m:03s - 2024-08-21
9:33 AM
(premap)Complete 6 1 0 0m:00s 0m:01s 199MB 2024-08-21
9:33 AM
(fpga_mapper)Complete 8 1 0 0m:01s 0m:02s 202MB 2024-08-21
9:33 AM
Multi-srs Generator Complete2024-08-21
9:33 AM

Area Summary
Register bits 12 I/O cells 33
Block RAMs (v_ram) 0 DSPs (dsp_used) 0
LUTs (total_luts) 19

Timing Summary
Clock NameReq FreqEst FreqSlack
counter_fsm|clk200.0 MHz495.0 MHz2.980

Optimizations Summary
Combined Clock Conversion 1 / 0