Project Settings
Project Name proj_1 Device Name impl_1: Lattice LFCPNX : LFCPNX_100
Implementation Name impl_1 Top Module work.seven_segment_decoder
Pipelining 1 Retiming 0
Resource Sharing 1 Fanout Guide 1000
Disable I/O Insertion 0 Disable Sequential Optimizations 0
Clock Conversion 0 FSM Compiler 1

Run Status
Job Name Status CPU Time Real Time Memory Date/Time
(compiler)Complete 73 0 0 - 00m:03s - 2024-08-21
8:30 AM
(premap)Complete 5 0 0 0m:00s 0m:01s 198MB 2024-08-21
8:30 AM
(fpga_mapper)Complete 11 0 0 0m:01s 0m:02s 201MB 2024-08-21
8:30 AM
Multi-srs Generator Complete2024-08-21
8:30 AM

Area Summary
Register bits 0 I/O cells 11
Block RAMs (v_ram) 0 DSPs (dsp_used) 0
LUTs (total_luts) 7

Optimizations Summary
Combined Clock Conversion 0 / 0