Project Settings
Project Name proj_1 Device Name impl_1: Lattice LFCPNX : LFCPNX_100
Implementation Name impl_1 Top Module top_level
Pipelining 1 Retiming 0
Resource Sharing 1 Fanout Guide 1000
Disable I/O Insertion 0 Disable Sequential Optimizations 0
Clock Conversion 0 FSM Compiler 1

Run Status
Job Name Status CPU Time Real Time Memory Date/Time
(compiler)Complete 87 1 0 - 00m:02s - 2024-08-26
3:06 PM
(premap)Complete 6 0 0 0m:00s 0m:01s 199MB 2024-08-26
3:06 PM
(fpga_mapper)Complete 13 2 0 0m:01s 0m:02s 202MB 2024-08-26
3:06 PM
Multi-srs Generator Complete00m:01s2024-08-26
3:06 PM

Area Summary
Register bits 30 I/O cells 12
Block RAMs (v_ram) 0 DSPs (dsp_used) 0
LUTs (total_luts) 19

Timing Summary
Clock NameReq FreqEst FreqSlack
clk21.0 MHz404.6 MHz997.529

Optimizations Summary
Combined Clock Conversion 1 / 0