Synthesis Report
#Build: Synplify Pro (R) U-2023.03LR-SP1-2, Build 296R, Mar  7 2024
#install: C:\lscc\radiant\2023.2\synpbase
#OS: Windows 10 or later
#Hostname: DESKTOP-CQ0R02Q

# Wed Aug 21 09:33:45 2024

#Implementation: impl_1


Copyright (C) 1994-2023 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: U-2023.03LR-SP1-2
Install: C:\lscc\radiant\2023.2\synpbase
OS: Windows 10 or later
Hostname: DESKTOP-CQ0R02Q

Implementation : impl_1
Synopsys HDL Compiler, Version comp202303synp1, Build 300R, Built Mar  7 2024 08:13:58, @

@N|Running in 64-bit mode
###########################################################[

Copyright (C) 1994-2023 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: U-2023.03LR-SP1-2
Install: C:\lscc\radiant\2023.2\synpbase
OS: Windows 10 or later
Hostname: DESKTOP-CQ0R02Q

Implementation : impl_1
Synopsys VHDL Compiler, Version comp202303synp1, Build 300R, Built Mar  7 2024 08:13:58, @

@N|Running in 64-bit mode
@N:"D:\02_LSCC\13_VHDL\LAB04\LAB04\source\impl_1\FSM.vhd":7:7:7:17|Top entity is set to counter_fsm.
@N: CD140 :	| Using the VHDL 1993 Standard for file 'C:\lscc\radiant\2023.2\ip\pmi\pmi_lfcpnx.vhd'.
@N: CD140 :	| Using the VHDL 1993 Standard for file 'D:\02_LSCC\13_VHDL\LAB04\LAB04\source\impl_1\FSM.vhd'.
@N: CD140 :	| Using the VHDL 1993 Standard for file 'C:\lscc\radiant\2023.2\cae_library\synthesis\vhdl\lfcpnx.vhd'.
VHDL syntax check successful!

At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 102MB peak: 102MB)


Process completed successfully.
# Wed Aug 21 09:33:45 2024

###########################################################]
###########################################################[

Copyright (C) 1994-2023 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: U-2023.03LR-SP1-2
Install: C:\lscc\radiant\2023.2\synpbase
OS: Windows 10 or later
Hostname: DESKTOP-CQ0R02Q

Implementation : impl_1
Synopsys Verilog Compiler, Version comp202303synp1, Build 300R, Built Mar  7 2024 08:13:58, @

@N|Running in 64-bit mode
@I::"C:\lscc\radiant\2023.2\synpbase\lib\lucent\lfcpnx.v" (library work)
@I::"C:\lscc\radiant\2023.2\synpbase\lib\lucent\pmi_def.v" (library work)
@I::"C:\lscc\radiant\2023.2\synpbase\lib\vlog\hypermods.v" (library __hyper__lib__)
@I::"C:\lscc\radiant\2023.2\synpbase\lib\vlog\scemi_objects.v" (library snps_haps)
@I::"C:\lscc\radiant\2023.2\synpbase\lib\vlog\scemi_pipes.svh" (library snps_haps)
@I::"C:\lscc\radiant\2023.2\ip\pmi\pmi_lfcpnx.v" (library work)
@I:"C:\lscc\radiant\2023.2\ip\pmi\pmi_lfcpnx.v":"C:\lscc\radiant\2023.2\ip\pmi\pmi_addsub.v" (library work)
@I:"C:\lscc\radiant\2023.2\ip\pmi\pmi_addsub.v":"C:\lscc\radiant\2023.2\ip\pmi\../common/adder_subtractor/rtl\lscc_add_sub.v" (library work)
@N: CG334 :"C:\lscc\radiant\2023.2\ip\pmi\../common/adder_subtractor/rtl\lscc_add_sub.v":313:13:313:25|Read directive translate_off.
@N: CG333 :"C:\lscc\radiant\2023.2\ip\pmi\../common/adder_subtractor/rtl\lscc_add_sub.v":333:13:333:24|Read directive translate_on.
@I:"C:\lscc\radiant\2023.2\ip\pmi\pmi_lfcpnx.v":"C:\lscc\radiant\2023.2\ip\pmi\pmi_add.v" (library work)
@I:"C:\lscc\radiant\2023.2\ip\pmi\pmi_add.v":"C:\lscc\radiant\2023.2\ip\pmi\../common/adder/rtl\lscc_adder.v" (library work)
@I:"C:\lscc\radiant\2023.2\ip\pmi\pmi_lfcpnx.v":"C:\lscc\radiant\2023.2\ip\pmi\pmi_complex_mult.v" (library work)
@I:"C:\lscc\radiant\2023.2\ip\pmi\pmi_complex_mult.v":"C:\lscc\radiant\2023.2\ip\pmi\../common/complex_mult/rtl\lscc_complex_mult.v" (library work)
@N: CG334 :"C:\lscc\radiant\2023.2\ip\pmi\pmi_complex_mult.v":92:11:92:23|Read directive translate_off.
@N: CG333 :"C:\lscc\radiant\2023.2\ip\pmi\pmi_complex_mult.v":101:11:101:22|Read directive translate_on.
@I:"C:\lscc\radiant\2023.2\ip\pmi\pmi_lfcpnx.v":"C:\lscc\radiant\2023.2\ip\pmi\pmi_counter.v" (library work)
@I:"C:\lscc\radiant\2023.2\ip\pmi\pmi_counter.v":"C:\lscc\radiant\2023.2\ip\pmi\../common/counter/rtl\lscc_cntr.v" (library work)
@N: CG334 :"C:\lscc\radiant\2023.2\ip\pmi\../common/counter/rtl\lscc_cntr.v":129:13:129:25|Read directive translate_off.
@N: CG333 :"C:\lscc\radiant\2023.2\ip\pmi\../common/counter/rtl\lscc_cntr.v":143:13:143:24|Read directive translate_on.
@I:"C:\lscc\radiant\2023.2\ip\pmi\pmi_lfcpnx.v":"C:\lscc\radiant\2023.2\ip\pmi\pmi_distributed_dpram.v" (library work)
@I:"C:\lscc\radiant\2023.2\ip\pmi\pmi_distributed_dpram.v":"C:\lscc\radiant\2023.2\ip\pmi\../common/distributed_dpram/rtl\lscc_distributed_dpram.v" (library work)
@I:"C:\lscc\radiant\2023.2\ip\pmi\pmi_lfcpnx.v":"C:\lscc\radiant\2023.2\ip\pmi\pmi_distributed_spram.v" (library work)
@I:"C:\lscc\radiant\2023.2\ip\pmi\pmi_distributed_spram.v":"C:\lscc\radiant\2023.2\ip\pmi\../common/distributed_spram/rtl\lscc_distributed_spram.v" (library work)
@I:"C:\lscc\radiant\2023.2\ip\pmi\pmi_lfcpnx.v":"C:\lscc\radiant\2023.2\ip\pmi\pmi_distributed_rom.v" (library work)
@I:"C:\lscc\radiant\2023.2\ip\pmi\pmi_distributed_rom.v":"C:\lscc\radiant\2023.2\ip\pmi\../common/distributed_rom/rtl\lscc_distributed_rom.v" (library work)
@I:"C:\lscc\radiant\2023.2\ip\pmi\pmi_lfcpnx.v":"C:\lscc\radiant\2023.2\ip\pmi\pmi_distributed_shift_reg.v" (library work)
@I:"C:\lscc\radiant\2023.2\ip\pmi\pmi_distributed_shift_reg.v":"C:\lscc\radiant\2023.2\ip\pmi\../common/ram_shift_reg/rtl\lscc_shift_register.v" (library work)
@N: CG334 :"C:\lscc\radiant\2023.2\ip\pmi\pmi_distributed_shift_reg.v":126:11:126:23|Read directive translate_off.
@N: CG333 :"C:\lscc\radiant\2023.2\ip\pmi\pmi_distributed_shift_reg.v":135:11:135:22|Read directive translate_on.
@I:"C:\lscc\radiant\2023.2\ip\pmi\pmi_lfcpnx.v":"C:\lscc\radiant\2023.2\ip\pmi\pmi_fifo.v" (library work)
@I:"C:\lscc\radiant\2023.2\ip\pmi\pmi_fifo.v":"C:\lscc\radiant\2023.2\ip\pmi\../avant/fifo/rtl\lscc_fifo.v" (library work)
@N: CG334 :"C:\lscc\radiant\2023.2\ip\pmi\../avant/fifo/rtl\lscc_fifo.v":3260:17:3260:29|Read directive translate_off.
@N: CG333 :"C:\lscc\radiant\2023.2\ip\pmi\../avant/fifo/rtl\lscc_fifo.v":3267:17:3267:28|Read directive translate_on.
@I:"C:\lscc\radiant\2023.2\ip\pmi\pmi_lfcpnx.v":"C:\lscc\radiant\2023.2\ip\pmi\pmi_fifo_dc.v" (library work)
@I:"C:\lscc\radiant\2023.2\ip\pmi\pmi_fifo_dc.v":"C:\lscc\radiant\2023.2\ip\pmi\../avant/fifo_dc/rtl\lscc_fifo_dc.v" (library work)
@N: CG334 :"C:\lscc\radiant\2023.2\ip\pmi\../avant/fifo_dc/rtl\lscc_fifo_dc.v":4898:25:4898:37|Read directive translate_off.
@N: CG333 :"C:\lscc\radiant\2023.2\ip\pmi\../avant/fifo_dc/rtl\lscc_fifo_dc.v":4902:25:4902:36|Read directive translate_on.
@N: CG334 :"C:\lscc\radiant\2023.2\ip\pmi\../avant/fifo_dc/rtl\lscc_fifo_dc.v":4933:29:4933:41|Read directive translate_off.
@N: CG333 :"C:\lscc\radiant\2023.2\ip\pmi\../avant/fifo_dc/rtl\lscc_fifo_dc.v":4937:29:4937:40|Read directive translate_on.
@I:"C:\lscc\radiant\2023.2\ip\pmi\pmi_lfcpnx.v":"C:\lscc\radiant\2023.2\ip\pmi\pmi_mac.v" (library work)
@I:"C:\lscc\radiant\2023.2\ip\pmi\pmi_mac.v":"C:\lscc\radiant\2023.2\ip\pmi\../common/mult_accumulate/rtl\lscc_mult_accumulate.v" (library work)
@N: CG334 :"C:\lscc\radiant\2023.2\ip\pmi\pmi_mac.v":94:11:94:23|Read directive translate_off.
@N: CG333 :"C:\lscc\radiant\2023.2\ip\pmi\pmi_mac.v":109:11:109:22|Read directive translate_on.
@I:"C:\lscc\radiant\2023.2\ip\pmi\pmi_lfcpnx.v":"C:\lscc\radiant\2023.2\ip\pmi\pmi_multaddsubsum.v" (library work)
@I:"C:\lscc\radiant\2023.2\ip\pmi\pmi_multaddsubsum.v":"C:\lscc\radiant\2023.2\ip\pmi\../common/mult_add_sub_sum/rtl\lscc_mult_add_sub_sum.v" (library work)
@N: CG334 :"C:\lscc\radiant\2023.2\ip\pmi\../common/mult_add_sub_sum/rtl\lscc_mult_add_sub_sum.v":210:13:210:25|Read directive translate_off.
@N: CG333 :"C:\lscc\radiant\2023.2\ip\pmi\../common/mult_add_sub_sum/rtl\lscc_mult_add_sub_sum.v":227:13:227:24|Read directive translate_on.
@N: CG334 :"C:\lscc\radiant\2023.2\ip\pmi\pmi_multaddsubsum.v":84:11:84:23|Read directive translate_off.
@N: CG333 :"C:\lscc\radiant\2023.2\ip\pmi\pmi_multaddsubsum.v":93:11:93:22|Read directive translate_on.
@I:"C:\lscc\radiant\2023.2\ip\pmi\pmi_lfcpnx.v":"C:\lscc\radiant\2023.2\ip\pmi\pmi_multaddsub.v" (library work)
@I:"C:\lscc\radiant\2023.2\ip\pmi\pmi_multaddsub.v":"C:\lscc\radiant\2023.2\ip\pmi\../common/mult_add_sub/rtl\lscc_mult_add_sub.v" (library work)
@N: CG334 :"C:\lscc\radiant\2023.2\ip\pmi\pmi_multaddsub.v":91:11:91:23|Read directive translate_off.
@N: CG333 :"C:\lscc\radiant\2023.2\ip\pmi\pmi_multaddsub.v":100:11:100:22|Read directive translate_on.
@I:"C:\lscc\radiant\2023.2\ip\pmi\pmi_lfcpnx.v":"C:\lscc\radiant\2023.2\ip\pmi\pmi_mult.v" (library work)
@I:"C:\lscc\radiant\2023.2\ip\pmi\pmi_mult.v":"C:\lscc\radiant\2023.2\ip\pmi\../common/multiplier/rtl\lscc_multiplier.v" (library work)
@N: CG334 :"C:\lscc\radiant\2023.2\ip\pmi\pmi_mult.v":87:11:87:23|Read directive translate_off.
@N: CG333 :"C:\lscc\radiant\2023.2\ip\pmi\pmi_mult.v":96:11:96:22|Read directive translate_on.
@I:"C:\lscc\radiant\2023.2\ip\pmi\pmi_lfcpnx.v":"C:\lscc\radiant\2023.2\ip\pmi\pmi_ram_dp.v" (library work)
@I:"C:\lscc\radiant\2023.2\ip\pmi\pmi_ram_dp.v":"C:\lscc\radiant\2023.2\ip\pmi\../avant/ram_dp/rtl\lscc_ram_dp.v" (library work)
@N: CG334 :"C:\lscc\radiant\2023.2\ip\pmi\../avant/ram_dp/rtl\lscc_ram_dp.v":1060:25:1060:37|Read directive translate_off.
@N: CG333 :"C:\lscc\radiant\2023.2\ip\pmi\../avant/ram_dp/rtl\lscc_ram_dp.v":1064:25:1064:36|Read directive translate_on.
@N: CG334 :"C:\lscc\radiant\2023.2\ip\pmi\../avant/ram_dp/rtl\lscc_ram_dp.v":1095:29:1095:41|Read directive translate_off.
@N: CG333 :"C:\lscc\radiant\2023.2\ip\pmi\../avant/ram_dp/rtl\lscc_ram_dp.v":1099:29:1099:40|Read directive translate_on.
@I:"C:\lscc\radiant\2023.2\ip\pmi\pmi_lfcpnx.v":"C:\lscc\radiant\2023.2\ip\pmi\pmi_ram_dp_be.v" (library work)
@N: CG334 :"C:\lscc\radiant\2023.2\ip\pmi\pmi_ram_dp_be.v":146:11:146:23|Read directive translate_off.
@N: CG333 :"C:\lscc\radiant\2023.2\ip\pmi\pmi_ram_dp_be.v":155:11:155:22|Read directive translate_on.
@I:"C:\lscc\radiant\2023.2\ip\pmi\pmi_lfcpnx.v":"C:\lscc\radiant\2023.2\ip\pmi\pmi_ram_dp_true.v" (library work)
@I:"C:\lscc\radiant\2023.2\ip\pmi\pmi_ram_dp_true.v":"C:\lscc\radiant\2023.2\ip\pmi\../avant/ram_dp_true/rtl\lscc_ram_dp_true.v" (library work)
@N: CG334 :"C:\lscc\radiant\2023.2\ip\pmi\../avant/ram_dp_true/rtl\lscc_ram_dp_true.v":1880:29:1880:41|Read directive translate_off.
@N: CG333 :"C:\lscc\radiant\2023.2\ip\pmi\../avant/ram_dp_true/rtl\lscc_ram_dp_true.v":1885:29:1885:40|Read directive translate_on.
@N: CG334 :"C:\lscc\radiant\2023.2\ip\pmi\../avant/ram_dp_true/rtl\lscc_ram_dp_true.v":1916:33:1916:45|Read directive translate_off.
@N: CG333 :"C:\lscc\radiant\2023.2\ip\pmi\../avant/ram_dp_true/rtl\lscc_ram_dp_true.v":1920:33:1920:44|Read directive translate_on.
@N: CG334 :"C:\lscc\radiant\2023.2\ip\pmi\../avant/ram_dp_true/rtl\lscc_ram_dp_true.v":1953:29:1953:41|Read directive translate_off.
@N: CG333 :"C:\lscc\radiant\2023.2\ip\pmi\../avant/ram_dp_true/rtl\lscc_ram_dp_true.v":1958:29:1958:40|Read directive translate_on.
@N: CG334 :"C:\lscc\radiant\2023.2\ip\pmi\../avant/ram_dp_true/rtl\lscc_ram_dp_true.v":1988:33:1988:45|Read directive translate_off.
@N: CG333 :"C:\lscc\radiant\2023.2\ip\pmi\../avant/ram_dp_true/rtl\lscc_ram_dp_true.v":1992:33:1992:44|Read directive translate_on.
@N: CG334 :"C:\lscc\radiant\2023.2\ip\pmi\../avant/ram_dp_true/rtl\lscc_ram_dp_true.v":2508:29:2508:41|Read directive translate_off.
@N: CG333 :"C:\lscc\radiant\2023.2\ip\pmi\../avant/ram_dp_true/rtl\lscc_ram_dp_true.v":2513:29:2513:40|Read directive translate_on.
@N: CG334 :"C:\lscc\radiant\2023.2\ip\pmi\../avant/ram_dp_true/rtl\lscc_ram_dp_true.v":2544:33:2544:45|Read directive translate_off.
@N: CG333 :"C:\lscc\radiant\2023.2\ip\pmi\../avant/ram_dp_true/rtl\lscc_ram_dp_true.v":2548:33:2548:44|Read directive translate_on.
@N: CG334 :"C:\lscc\radiant\2023.2\ip\pmi\../avant/ram_dp_true/rtl\lscc_ram_dp_true.v":2581:29:2581:41|Read directive translate_off.
@N: CG333 :"C:\lscc\radiant\2023.2\ip\pmi\../avant/ram_dp_true/rtl\lscc_ram_dp_true.v":2586:29:2586:40|Read directive translate_on.
@N: CG334 :"C:\lscc\radiant\2023.2\ip\pmi\../avant/ram_dp_true/rtl\lscc_ram_dp_true.v":2617:33:2617:45|Read directive translate_off.
@N: CG333 :"C:\lscc\radiant\2023.2\ip\pmi\../avant/ram_dp_true/rtl\lscc_ram_dp_true.v":2621:33:2621:44|Read directive translate_on.
@N: CG334 :"C:\lscc\radiant\2023.2\ip\pmi\../avant/ram_dp_true/rtl\lscc_ram_dp_true.v":3108:29:3108:41|Read directive translate_off.
@N: CG333 :"C:\lscc\radiant\2023.2\ip\pmi\../avant/ram_dp_true/rtl\lscc_ram_dp_true.v":3113:29:3113:40|Read directive translate_on.
@N: CG334 :"C:\lscc\radiant\2023.2\ip\pmi\../avant/ram_dp_true/rtl\lscc_ram_dp_true.v":3144:33:3144:45|Read directive translate_off.
@N: CG333 :"C:\lscc\radiant\2023.2\ip\pmi\../avant/ram_dp_true/rtl\lscc_ram_dp_true.v":3148:33:3148:44|Read directive translate_on.
@N: CG334 :"C:\lscc\radiant\2023.2\ip\pmi\../avant/ram_dp_true/rtl\lscc_ram_dp_true.v":3181:29:3181:41|Read directive translate_off.
@N: CG333 :"C:\lscc\radiant\2023.2\ip\pmi\../avant/ram_dp_true/rtl\lscc_ram_dp_true.v":3186:29:3186:40|Read directive translate_on.
@N: CG334 :"C:\lscc\radiant\2023.2\ip\pmi\../avant/ram_dp_true/rtl\lscc_ram_dp_true.v":3217:33:3217:45|Read directive translate_off.
@N: CG333 :"C:\lscc\radiant\2023.2\ip\pmi\../avant/ram_dp_true/rtl\lscc_ram_dp_true.v":3221:33:3221:44|Read directive translate_on.
@I:"C:\lscc\radiant\2023.2\ip\pmi\pmi_lfcpnx.v":"C:\lscc\radiant\2023.2\ip\pmi\pmi_ram_dq.v" (library work)
@I:"C:\lscc\radiant\2023.2\ip\pmi\pmi_ram_dq.v":"C:\lscc\radiant\2023.2\ip\pmi\../avant/ram_dq/rtl\lscc_ram_dq.v" (library work)
@N: CG334 :"C:\lscc\radiant\2023.2\ip\pmi\../avant/ram_dq/rtl\lscc_ram_dq.v":1485:25:1485:37|Read directive translate_off.
@N: CG333 :"C:\lscc\radiant\2023.2\ip\pmi\../avant/ram_dq/rtl\lscc_ram_dq.v":1491:25:1491:36|Read directive translate_on.
@I:"C:\lscc\radiant\2023.2\ip\pmi\pmi_lfcpnx.v":"C:\lscc\radiant\2023.2\ip\pmi\pmi_ram_dq_be.v" (library work)
@N: CG334 :"C:\lscc\radiant\2023.2\ip\pmi\pmi_ram_dq_be.v":87:11:87:23|Read directive translate_off.
@N: CG333 :"C:\lscc\radiant\2023.2\ip\pmi\pmi_ram_dq_be.v":95:11:95:22|Read directive translate_on.
@I:"C:\lscc\radiant\2023.2\ip\pmi\pmi_lfcpnx.v":"C:\lscc\radiant\2023.2\ip\pmi\pmi_rom.v" (library work)
@I:"C:\lscc\radiant\2023.2\ip\pmi\pmi_rom.v":"C:\lscc\radiant\2023.2\ip\pmi\../avant/rom/rtl\lscc_rom.v" (library work)
@N: CG334 :"C:\lscc\radiant\2023.2\ip\pmi\../avant/rom/rtl\lscc_rom.v":970:25:970:37|Read directive translate_off.
@N: CG333 :"C:\lscc\radiant\2023.2\ip\pmi\../avant/rom/rtl\lscc_rom.v":976:25:976:36|Read directive translate_on.
@I:"C:\lscc\radiant\2023.2\ip\pmi\pmi_lfcpnx.v":"C:\lscc\radiant\2023.2\ip\pmi\pmi_sub.v" (library work)
@I:"C:\lscc\radiant\2023.2\ip\pmi\pmi_sub.v":"C:\lscc\radiant\2023.2\ip\pmi\../common/subtractor/rtl\lscc_subtractor.v" (library work)
Verilog syntax check successful!

At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 131MB peak: 131MB)


Process completed successfully.
# Wed Aug 21 09:33:46 2024

###########################################################]
###########################################################[
@N:"D:\02_LSCC\13_VHDL\LAB04\LAB04\source\impl_1\FSM.vhd":7:7:7:17|Top entity is set to counter_fsm.
@N: CD140 :	| Using the VHDL 1993 Standard for file 'C:\lscc\radiant\2023.2\ip\pmi\pmi_lfcpnx.vhd'.
@N: CD140 :	| Using the VHDL 1993 Standard for file 'D:\02_LSCC\13_VHDL\LAB04\LAB04\source\impl_1\FSM.vhd'.
@N: CD140 :	| Using the VHDL 1993 Standard for file 'C:\lscc\radiant\2023.2\cae_library\synthesis\vhdl\lfcpnx.vhd'.
VHDL syntax check successful!
@N: CD630 :"D:\02_LSCC\13_VHDL\LAB04\LAB04\source\impl_1\FSM.vhd":7:7:7:17|Synthesizing work.counter_fsm.behavioral.
@N: CD233 :"D:\02_LSCC\13_VHDL\LAB04\LAB04\source\impl_1\FSM.vhd":20:16:20:17|Using sequential encoding for type state_type.
@N: CD604 :"D:\02_LSCC\13_VHDL\LAB04\LAB04\source\impl_1\FSM.vhd":50:12:50:25|OTHERS clause is not synthesized.
Post processing for work.counter_fsm.behavioral
Running optimization stage 1 on counter_fsm .......
Finished optimization stage 1 on counter_fsm (CPU Time 0h:00m:00s, Memory Used current: 104MB peak: 104MB)
Running optimization stage 2 on counter_fsm .......
@N: CL201 :"D:\02_LSCC\13_VHDL\LAB04\LAB04\source\impl_1\FSM.vhd":27:0:27:1|Trying to extract state machine for register state.
Extracted state machine for register state
State machine has 4 reachable states with original encodings of:
   00
   01
   10
   11
Finished optimization stage 2 on counter_fsm (CPU Time 0h:00m:00s, Memory Used current: 104MB peak: 105MB)

For a summary of runtime per design unit, please see file:
==========================================================
@L: D:\02_LSCC\13_VHDL\LAB04\LAB04\impl_1\synwork\layer0.duruntime



At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 104MB peak: 105MB)


Process completed successfully.
# Wed Aug 21 09:33:46 2024

###########################################################]
###########################################################[

Copyright (C) 1994-2023 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: U-2023.03LR-SP1-2
Install: C:\lscc\radiant\2023.2\synpbase
OS: Windows 10 or later
Hostname: DESKTOP-CQ0R02Q

Implementation : impl_1
Synopsys Synopsys Netlist Linker, Version comp202303synp1, Build 300R, Built Mar  7 2024 08:13:58, @

@N|Running in 64-bit mode

At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 90MB peak: 91MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime

Process completed successfully.
# Wed Aug 21 09:33:48 2024

###########################################################]

For a summary of runtime and memory usage for all design units, please see file:
==========================================================
@L: D:\02_LSCC\13_VHDL\LAB04\LAB04\impl_1\synwork\LAB04_impl_1_comp.rt.csv

@END

At c_hdl Exit (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:00s; Memory used current: 23MB peak: 23MB)

Process took 0h:00m:02s realtime, 0h:00m:01s cputime

Process completed successfully.
# Wed Aug 21 09:33:48 2024

###########################################################]
###########################################################[

Copyright (C) 1994-2023 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: U-2023.03LR-SP1-2
Install: C:\lscc\radiant\2023.2\synpbase
OS: Windows 10 or later
Hostname: DESKTOP-CQ0R02Q

Implementation : impl_1
Synopsys Synopsys Netlist Linker, Version comp202303synp1, Build 300R, Built Mar  7 2024 08:13:58, @

@N|Running in 64-bit mode

At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 90MB peak: 91MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime

Process completed successfully.
# Wed Aug 21 09:33:49 2024

###########################################################]
Premap Report

# Wed Aug 21 09:33:53 2024


Copyright (C) 1994-2023 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: U-2023.03LR-SP1-2
Install: C:\lscc\radiant\2023.2\synpbase
OS: Windows 10 or later
Hostname: DESKTOP-CQ0R02Q

Implementation : impl_1
Synopsys Lattice Technology Pre-mapping, Version map202303lat, Build 248R, Built Mar  7 2024 08:35:47, @


Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 122MB peak: 122MB)


Done reading skeleton netlist (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 127MB peak: 136MB)

@A: MF827 |No constraint file specified.
@L: D:\02_LSCC\13_VHDL\LAB04\LAB04\impl_1\LAB04_impl_1_scck.rpt 
See clock summary report "D:\02_LSCC\13_VHDL\LAB04\LAB04\impl_1\LAB04_impl_1_scck.rpt"
@N: MF916 |Option synthesis_strategy=base is enabled. 
@N: MF248 |Running in 64-bit mode.
@N: MF667 |Clock conversion disabled. (Command "set_option -fix_gated_and_generated_clocks 0" in the project file.)

Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 131MB peak: 136MB)


Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 131MB peak: 136MB)


Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 143MB)


Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 145MB)

NConnInternalConnection caching is on

Starting HSTDM IP insertion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 193MB peak: 194MB)


Finished HSTDM IP insertion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 193MB peak: 194MB)


Started DisTri Cleanup (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 193MB peak: 194MB)


Finished DisTri Cleanup (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 193MB peak: 194MB)

Encoding state machine state[0:3] (in view: work.counter_fsm(behavioral))
original code -> new code
   00 -> 00
   01 -> 01
   10 -> 10
   11 -> 11
@N: MO225 :"d:\02_lscc\13_vhdl\lab04\lab04\source\impl_1\fsm.vhd":27:0:27:1|There are no possible illegal states for state machine state[0:3] (in view: work.counter_fsm(behavioral)); safe FSM implementation is not required.

Starting clock optimization report phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 196MB peak: 196MB)


Finished clock optimization report phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 196MB peak: 196MB)

@N: FX1184 |Applying syn_allowed_resources blockrams=208 on top level netlist counter_fsm 

Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 196MB peak: 196MB)



Clock Summary
******************

          Start               Requested     Requested     Clock        Clock          Clock
Level     Clock               Frequency     Period        Type         Group          Load 
-------------------------------------------------------------------------------------------
0 -       counter_fsm|clk     200.0 MHz     5.000         inferred     (multiple)     12   
===========================================================================================



Clock Load Summary
***********************

                    Clock     Source        Clock Pin          Non-clock Pin     Non-clock Pin
Clock               Load      Pin           Seq Example        Seq Example       Comb Example 
----------------------------------------------------------------------------------------------
counter_fsm|clk     12        clk(port)     Disp_en[2:0].C     -                 -            
==============================================================================================

@W: MT530 :"d:\02_lscc\13_vhdl\lab04\lab04\source\impl_1\fsm.vhd":27:0:27:1|Found inferred clock counter_fsm|clk which controls 12 sequential elements including state[1]. This clock has no specified timing constraint which may adversely impact design performance. 

ICG Latch Removal Summary:
Number of ICG latches removed: 0
Number of ICG latches not removed:	0


@S |Clock Optimization Summary



#### START OF PREMAP CLOCK OPTIMIZATION REPORT #####[

1 non-gated/non-generated clock tree(s) driving 12 clock pin(s) of sequential element(s)
0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
0 instances converted, 0 sequential instances remain driven by gated/generated clocks

=========================== Non-Gated/Non-Generated Clocks ============================
Clock Tree ID     Driving Element     Drive Element Type     Fanout     Sample Instance
---------------------------------------------------------------------------------------
@KP:ckid0_0       clk                 port                   12         state[1]       
=======================================================================================


##### END OF CLOCK OPTIMIZATION REPORT ######


Summary of user generated gated clocks:
0 user generated gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)

@N: FX1143 |Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized.
Finished Pre Mapping Phase.

Starting constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 197MB peak: 197MB)


Finished constraint checker preprocessing (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 197MB peak: 197MB)


Finished constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 197MB peak: 197MB)

Pre-mapping successful!

At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 199MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Wed Aug 21 09:33:55 2024

###########################################################]
Map & Optimize Report

# Wed Aug 21 09:33:55 2024


Copyright (C) 1994-2023 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: U-2023.03LR-SP1-2
Install: C:\lscc\radiant\2023.2\synpbase
OS: Windows 10 or later
Hostname: DESKTOP-CQ0R02Q

Implementation : impl_1
Synopsys Lattice Technology Mapper, Version map202303lat, Build 248R, Built Mar  7 2024 08:35:47, @


Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 122MB peak: 122MB)

@N: MF916 |Option synthesis_strategy=base is enabled. 
@N: MF248 |Running in 64-bit mode.
@N: MF667 |Clock conversion disabled. (Command "set_option -fix_gated_and_generated_clocks 0" in the project file.)

Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 124MB peak: 136MB)


Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 124MB peak: 136MB)


Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 138MB)


Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)



Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 192MB peak: 192MB)


Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 195MB peak: 195MB)


Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 197MB peak: 197MB)


Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 197MB peak: 197MB)


Available hyper_sources - for debug and ip models
	None Found

NConnInternalConnection caching is on

Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 197MB peak: 197MB)


Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 197MB peak: 198MB)


Finished Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 197MB peak: 198MB)


Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 197MB peak: 198MB)


Finished preparing to map (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 197MB peak: 198MB)


Finished technology mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 198MB peak: 198MB)

Pass		 CPU time		Worst Slack		Luts / Registers
------------------------------------------------------------
   1		0h:00m:00s		     3.02ns		  20 /        12

Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 198MB peak: 198MB)

@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.  

Finished restoring hierarchy (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 198MB peak: 198MB)


Starting CDBProcessSetClockGroups... (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 199MB peak: 199MB)


Finished with CDBProcessSetClockGroups (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 199MB peak: 199MB)


Start Writing Netlists (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 145MB peak: 199MB)

Writing Analyst data base D:\02_LSCC\13_VHDL\LAB04\LAB04\impl_1\synwork\LAB04_impl_1_m.srm

Finished Writing Netlist Databases (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 199MB peak: 199MB)

Writing Verilog Simulation files

Writing scf file... (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 201MB peak: 201MB)

@N: BW103 |The default time unit for the Synopsys Constraint File (SDC or FDC) is 1ns.
@N: BW107 |Synopsys Constraint File capacitance units using default value of 1pF 

Finished Writing Verilog Simulation files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 201MB peak: 201MB)


Finished Writing Netlists (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 201MB peak: 202MB)


Start final timing analysis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:00s; Memory used current: 200MB peak: 202MB)

@W: MT420 |Found inferred clock counter_fsm|clk with period 5.00ns. Please declare a user-defined clock on port clk.


##### START OF TIMING REPORT #####[
# Timing report written on Wed Aug 21 09:33:57 2024
#


Top view:               counter_fsm
Requested Frequency:    200.0 MHz
Wire load mode:         top
Paths requested:        5
Constraint File(s):    
@N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report.

@N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock.



Performance Summary
*******************


Worst slack in design: 2.980

                    Requested     Estimated     Requested     Estimated               Clock        Clock     
Starting Clock      Frequency     Frequency     Period        Period        Slack     Type         Group     
-------------------------------------------------------------------------------------------------------------
counter_fsm|clk     200.0 MHz     495.0 MHz     5.000         2.020         2.980     inferred     (multiple)
=============================================================================================================





Clock Relationships
*******************

Clocks                            |    rise  to  rise   |    fall  to  fall   |    rise  to  fall   |    fall  to  rise 
------------------------------------------------------------------------------------------------------------------------
Starting         Ending           |  constraint  slack  |  constraint  slack  |  constraint  slack  |  constraint  slack
------------------------------------------------------------------------------------------------------------------------
counter_fsm|clk  counter_fsm|clk  |  5.000       2.980  |  No paths    -      |  No paths    -      |  No paths    -    
========================================================================================================================
 Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.



Interface Information 
*********************

No IO constraint found



====================================
Detailed Report for Clock: counter_fsm|clk
====================================



Starting Points with Worst Slack
********************************

             Starting                                             Arrival          
Instance     Reference           Type        Pin     Net          Time        Slack
             Clock                                                                 
-----------------------------------------------------------------------------------
state[0]     counter_fsm|clk     FD1P3DX     Q       state[0]     0.943       2.980
state[1]     counter_fsm|clk     FD1P3DX     Q       state[1]     0.923       3.523
===================================================================================


Ending Points with Worst Slack
******************************

                    Starting                                                   Required          
Instance            Reference           Type         Pin     Net               Time         Slack
                    Clock                                                                        
-------------------------------------------------------------------------------------------------
Data_out_0io[0]     counter_fsm|clk     OFD1P3DX     D       Data_out_5[0]     4.789        2.980
Data_out_0io[1]     counter_fsm|clk     OFD1P3DX     D       Data_out_5[1]     4.789        2.980
Data_out_0io[2]     counter_fsm|clk     OFD1P3DX     D       Data_out_5[2]     4.789        2.980
Data_out_0io[3]     counter_fsm|clk     OFD1P3DX     D       Data_out_5[3]     4.789        2.980
Data_out_0io[4]     counter_fsm|clk     OFD1P3DX     D       Data_out_5[4]     4.789        2.980
Data_out_0io[5]     counter_fsm|clk     OFD1P3DX     D       Data_out_5[5]     4.789        2.980
Data_out_0io[6]     counter_fsm|clk     OFD1P3DX     D       Data_out_5[6]     4.789        2.980
Disp_en_0io[0]      counter_fsm|clk     OFD1P3DX     D       state_6_d         4.789        3.503
Disp_en_0io[1]      counter_fsm|clk     OFD1P3DX     D       state_d[2]        4.789        3.503
Disp_en_0io[2]      counter_fsm|clk     OFD1P3DX     D       N_12_i_i          4.789        3.503
=================================================================================================



Worst Path Information
***********************


Path information for path number 1: 
      Requested Period:                      5.000
    - Setup time:                            0.211
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         4.789

    - Propagation time:                      1.809
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (critical) :                     2.980

    Number of logic level(s):                2
    Starting point:                          state[0] / Q
    Ending point:                            Data_out_0io[0] / D
    The start point is clocked by            counter_fsm|clk [rising] (rise=0.000 fall=2.500 period=5.000) on pin CK
    The end   point is clocked by            counter_fsm|clk [rising] (rise=0.000 fall=2.500 period=5.000) on pin CK

Instance / Net                         Pin      Pin               Arrival     No. of    
Name                      Type         Name     Dir     Delay     Time        Fan Out(s)
----------------------------------------------------------------------------------------
state[0]                  FD1P3DX      Q        Out     0.943     0.943 r     -         
state[0]                  Net          -        -       -         -           19        
Data_out_0io_RNO_0[0]     LUT4         C        In      0.000     0.943 r     -         
Data_out_0io_RNO_0[0]     LUT4         Z        Out     0.523     1.466 r     -         
N_34                      Net          -        -       -         -           1         
Data_out_0io_RNO[0]       LUT4         A        In      0.000     1.466 r     -         
Data_out_0io_RNO[0]       LUT4         Z        Out     0.343     1.809 r     -         
Data_out_5[0]             Net          -        -       -         -           1         
Data_out_0io[0]           OFD1P3DX     D        In      0.000     1.809 r     -         
========================================================================================



##### END OF TIMING REPORT #####]

Timing exceptions that could not be applied

Finished final timing analysis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:00s; Memory used current: 201MB peak: 202MB)


Finished timing report (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:00s; Memory used current: 201MB peak: 202MB)

---------------------------------------
Resource Usage Report
Part: lfcpnx_100-9

Register bits: 12 of 79872 (0%)
PIC Latch:       0
I/O cells:       33


Details:
FD1P3DX:        2
GSR:            1
IB:             23
INV:            1
LUT4:           19
OB:             10
OFD1P3DX:       10
VHI:            1
VLO:            1

Resource Usage inside macros:
Registers: 0
LUTs: 0
EBRs: 0
LRAMs: 0
DSPs: 0
Distributed RAMs: 0
Carry Chains: 0
Blackboxes: 0

Mapping Summary:
Total number of registers: 12 + 0 = 12 of 79872 (0.02%)
Total number of LUTs: 19 + 0 = 19 
Total number of EBRs: 0 + 0 = 0 of 208 (0.00%)
Total number of LRAMs: 0 + 0 = 0 of 7 (0.00%)
Total number of DSPs: 0 + 0 = 0 of 156 (0.00%)
Total number of Distributed RAMs: 0 + 0 = 0 
Total number of Carry Chains: 0 + 0 = 0 
Total number of BlackBoxes: 3 + 0 = 3 
Mapper successful!

At Mapper Exit (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 62MB peak: 202MB)

Process took 0h:00m:02s realtime, 0h:00m:01s cputime
# Wed Aug 21 09:33:57 2024

###########################################################]