Timing Report
Lattice Timing Report -  Setup  and Hold, Version Radiant Software (64-bit) 2023.2.1.288.0

Tue Jun 25 17:24:01 2024

Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp.   All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
Copyright (c) 2001 Agere Systems   All rights reserved.
Copyright (c) 2002-2023 Lattice Semiconductor Corporation,  All rights reserved.

Command line:    timing -sethld -sp 9_High-Performance_1.0V -hsp m -v 10 -u 10 -endpoints 10 -nperend 1 -html -rpt LAB01_impl_1.tw1 LAB01_impl_1_map.udb -gui -msgset C:/Users/ssyahril/OneDrive - Lattice Semiconductor Corp/Documents/Insights/Constraint Deep Dive/Radiant Lab/LAB_01/promote.xml

-------------------------------------------
Design:          top
Family:          LFCPNX
Device:          LFCPNX-50
Package:         CBG256
Performance:     9_High-Performance_1.0V
Package Status:                     Final          Version 16
Performance Hardware Data Status :   Final Version 3.9
-------------------------------------------


=====================================================================
                    Table of Contents
=====================================================================
  • 1 Timing Overview
  • 1.1 SDC Constraints
  • 1.2 Constraint Coverage
  • 1.3 Overall Summary
  • 1.4 Unconstrained Report
  • 1.5 Combinational Loop
  • 1.6 Error/Warning Messages
  • 2 Setup at Speed Grade 9_High-Performance_1.0V Corner at 85 Degrees
  • 2.1 Clock Summary
  • 2.2 Endpoint slacks
  • 2.3 Detailed Report
  • 3 Setup at Speed Grade 9_High-Performance_1.0V Corner at 0 Degrees
  • 3.1 Clock Summary
  • 3.2 Endpoint slacks
  • 3.3 Detailed Report
  • 4 Hold at Speed Grade m Corner at 0 Degrees
  • 4.1 Endpoint slacks
  • 4.2 Detailed Report
  • ===================================================================== End of Table of Contents ===================================================================== 1 Timing Overview 1.1 SDC Constraints create_generated_clock -name {clk2} -source [get_pins {MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK}] -multiply_by 2 [get_pins {MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS }] create_generated_clock -name {clk1} -source [get_pins {MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK}] -multiply_by 2 [get_pins {MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP }] create_clock -name {Clk} -period 20 [get_nets Clk_c] 1.2 Constraint Coverage Constraint Coverage: 45.4545% 1.3 Overall Summary Setup at Speed Grade 9_High-Performance_1.0V Corner at 85 Degrees Timing Errors: 0 endpoints; Total Negative Slack: 0.000 ns Setup at Speed Grade 9_High-Performance_1.0V Corner at 0 Degrees Timing Errors: 0 endpoints; Total Negative Slack: 0.000 ns Hold at Speed Grade m Corner at 0 Degrees Timing Errors: 0 endpoints; Total Negative Slack: 0.000 ns 1.4 Unconstrained Report 1.4.1 Unconstrained Start/End Points Clocked but unconstrained timing start points ------------------------------------------------------------------- Listing 2 Start Points | Type ------------------------------------------------------------------- B_sig1.ff_inst/Q | No required time A_Sig1.ff_inst/Q | No required time ------------------------------------------------------------------- | Number of unconstrained timing start po | ints | 2 | ------------------------------------------------------------------- Clocked but unconstrained timing end points ------------------------------------------------------------------- Listing 2 End Points | Type ------------------------------------------------------------------- A_Sig_c.ff_inst/DF | No arrival time B_sig_c.ff_inst/DF | No arrival time ------------------------------------------------------------------- | Number of unconstrained timing end poin | ts | 2 | ------------------------------------------------------------------- 1.4.2 Start/End Points Without Timing Constraints I/O ports without constraint ---------------------------- Possible constraints to use on I/O ports are: set_input_delay, set_output_delay, set_max_delay, create_clock, create_generated_clock, ... ------------------------------------------------------------------- Listing 5 Start or End Points | Type ------------------------------------------------------------------- Clk | input B | input A | input out2 | output out1 | output ------------------------------------------------------------------- | Number of I/O ports without constraint | 5 | ------------------------------------------------------------------- Nets without clock definition Define a clock on a top level port or a generated clock on a clock divider pin associated with this net(s). -------------------------------------------------- There is no instance satisfying reporting criteria 1.5 Combinational Loop None 1.6 Error/Warning Messages WARNING "70009502" - The preferred point for defining clocks is top level ports and driver pins. Pad delays will not be taken into consideration if clocks are defined on nets. 2 Setup at Speed Grade 9_High-Performance_1.0V Corner at 85 Degrees 2.1 Clock Summary 2.1.1 Clock "clk1" create_generated_clock -name {clk1} -source [get_pins {MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK}] -multiply_by 2 [get_pins {MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP }] Single Clock Domain ------------------------------------------------------------------------------------------------------- Clock clk1 | | Period | Frequency ------------------------------------------------------------------------------------------------------- From clk1 | Target | 10.000 ns | 100.000 MHz | Actual (all paths) | 2.000 ns | 500.000 MHz A_Sig_c.ff_inst/CLK (MPW) | (50% duty cycle) | 2.000 ns | 500.000 MHz ------------------------------------------------------------------------------------------------------- Clock Domain Crossing ------------------------------------------------------------------------------------------------------ Clock clk1 | Worst Time Between Edges | Comment ------------------------------------------------------------------------------------------------------ From clk2 | ---- | No path From Clk | ---- | No path ------------------------------------------------------------------------------------------------------ 2.1.2 Clock "clk2" create_generated_clock -name {clk2} -source [get_pins {MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK}] -multiply_by 2 [get_pins {MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS }] Single Clock Domain ------------------------------------------------------------------------------------------------------- Clock clk2 | | Period | Frequency ------------------------------------------------------------------------------------------------------- From clk2 | Target | 10.000 ns | 100.000 MHz | Actual (all paths) | 2.000 ns | 500.000 MHz B_sig1.ff_inst/CLK (MPW) | (50% duty cycle) | 2.000 ns | 500.000 MHz ------------------------------------------------------------------------------------------------------- Clock Domain Crossing ------------------------------------------------------------------------------------------------------ Clock clk2 | Worst Time Between Edges | Comment ------------------------------------------------------------------------------------------------------ From clk1 | 2.500 ns | slack = 1.634 ns From Clk | ---- | No path ------------------------------------------------------------------------------------------------------ 2.1.3 Clock "Clk" create_clock -name {Clk} -period 20 [get_nets Clk_c] Single Clock Domain ------------------------------------------------------------------------------------------------------- Clock Clk | | Period | Frequency ------------------------------------------------------------------------------------------------------- From Clk | Target | 20.000 ns | 50.000 MHz | Actual (all paths) | ---- | ---- ------------------------------------------------------------------------------------------------------- Clock Domain Crossing ------------------------------------------------------------------------------------------------------ Clock Clk | Worst Time Between Edges | Comment ------------------------------------------------------------------------------------------------------ From clk1 | ---- | No path From clk2 | ---- | No path ------------------------------------------------------------------------------------------------------ 2.2 Endpoint slacks ------------------------------------------------------- Listing 2 End Points | Slack ------------------------------------------------------- B_sig1.ff_inst/DF | 1.634 ns A_Sig1.ff_inst/DF | 9.324 ns ------------------------------------------------------- | Setup # of endpoints with negative slack:| 0 | ------------------------------------------------------- 2.3 Detailed Report XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX Detail report of critical paths XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Detailed Report for timing paths +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ ++++Path 1 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Path Begin : A_Sig_c.ff_inst/Q (SLICE) Path End : B_sig1.ff_inst/DF (SLICE) Source Clock : clk1 (R) Destination Clock: clk2 (R) Logic Level : 2 Delay Ratio : 44.0% (route), 56.0% (logic) Clock Skew : 0.000 ns Setup Constraint : 2.500 ns Common Path Skew : 0.000 ns Path Slack : 1.634 ns (Passed) Source Clock Path { "path_begin": { "type":"pin", "log_name":"Clk_pad.bb_inst/O", "phy_name":"Clk_pad.bb_inst/PADDI" }, "path_end": { "type":"pin", "log_name":"A_Sig_c.ff_inst/CLK", "phy_name":"A_Sig_c.SLICE_1/CLK" }, "path_sections":[ { "type":"net_delay", "net": { "log_name":"MyPLL/lscc_pll_inst/REFCK", "phy_name":"Clk_c" }, "arrive":0.300, "delay":0.300 }, { "type":"site_delay", "pin0": { "log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK", "phy_name":"MyPLL.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/REFCK" }, "pin1": { "log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP", "phy_name":"MyPLL.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP" }, "arrive":0.300, "delay":0.000 }, { "type":"site_delay", "pin0": { "log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK", "phy_name":"MyPLL.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/REFCK" }, "pin1": { "log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP", "phy_name":"MyPLL.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP" }, "arrive":0.300, "delay":0.000 }, { "type":"net_delay", "net": { "log_name":"MyPLL/lscc_pll_inst/clk1", "phy_name":"clk1" }, "arrive":0.707, "delay":0.407 }, { "type":"site_delay", "pin0": { "log_name":"", "phy_name":"" }, "pin1": { "log_name":"", "phy_name":"" }, "arrive":0.707, "delay":0.000 } ] } Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- -------------- ---------------- --------- --------------------- ------ Clk_pad.bb_inst/PADDI SEIO18A_CORE CLOCK LATENCY 0.000 0.000 1 MyPLL/lscc_pll_inst/REFCK NET DELAY 0.300 0.300 1 MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK->MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP PLL_CORE 0.000 0.300 2 MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK->MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP (TOTAL_ADJUSTMENTS) PLL_CORE 0.000 0.300 2 MyPLL/lscc_pll_inst/clk1 NET DELAY 0.407 0.707 2 A_Sig_c.ff_inst/CLK CLOCK PIN 0.000 0.707 1 Data Path { "path_begin": { "type":"pin", "log_name":"A_Sig_c.ff_inst/Q", "phy_name":"A_Sig_c.SLICE_1/Q0" }, "path_end": { "type":"pin", "log_name":"B_sig1.ff_inst/DF", "phy_name":"SLICE_0/DI0" }, "path_sections":[ { "type":"site_delay", "pin0": { "log_name":"A_Sig_c.ff_inst/CLK", "phy_name":"A_Sig_c.SLICE_1/CLK" }, "pin1": { "log_name":"A_Sig_c.ff_inst/Q", "phy_name":"A_Sig_c.SLICE_1/Q0" }, "arrive":1.011, "delay":0.304 }, { "type":"net_delay", "net": { "log_name":"A_Sig", "phy_name":"A_Sig" }, "arrive":1.418, "delay":0.407 }, { "type":"site_delay", "pin0": { "log_name":"i8_2_lut/B", "phy_name":"SLICE_0/B0" }, "pin1": { "log_name":"i8_2_lut/Z", "phy_name":"SLICE_0/F0" }, "arrive":1.631, "delay":0.213 }, { "type":"net_delay", "net": { "log_name":"out2_c_N_1", "phy_name":"out2_c_N_1" }, "arrive":1.631, "delay":0.000 }, { "type":"site_delay", "pin0": { "log_name":"", "phy_name":"" }, "pin1": { "log_name":"", "phy_name":"" }, "arrive":1.631, "delay":0.000 } ] } Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- -------------- ---------------- --------- --------------------- ------ A_Sig_c.ff_inst/CLK->A_Sig_c.ff_inst/Q SLICE REG_DEL 0.304 1.011 2 A_Sig NET DELAY 0.407 1.418 2 i8_2_lut/B->i8_2_lut/Z SLICE CTOF_DEL 0.213 1.631 1 out2_c_N_1 NET DELAY 0.000 1.631 1 B_sig1.ff_inst/DF ENDPOINT 0.000 1.631 1 Destination Clock Path { "path_begin": { "type":"pin", "log_name":"Clk_pad.bb_inst/O", "phy_name":"Clk_pad.bb_inst/PADDI" }, "path_end": { "type":"pin", "log_name":"B_sig1.ff_inst/CLK", "phy_name":"SLICE_0/CLK" }, "path_sections":[ { "type":"site_delay", "pin0": { "log_name":"", "phy_name":"" }, "pin1": { "log_name":"", "phy_name":"" }, "arrive":2.500, "delay":0.000 }, { "type":"net_delay", "net": { "log_name":"MyPLL/lscc_pll_inst/REFCK", "phy_name":"Clk_c" }, "arrive":2.800, "delay":0.300 }, { "type":"site_delay", "pin0": { "log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK", "phy_name":"MyPLL.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/REFCK" }, "pin1": { "log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS", "phy_name":"MyPLL.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS" }, "arrive":2.800, "delay":0.000 }, { "type":"site_delay", "pin0": { "log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK", "phy_name":"MyPLL.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/REFCK" }, "pin1": { "log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS", "phy_name":"MyPLL.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS" }, "arrive":2.800, "delay":0.000 }, { "type":"net_delay", "net": { "log_name":"MyPLL/lscc_pll_inst/clk2", "phy_name":"clk2" }, "arrive":3.207, "delay":0.407 }, { "type":"site_delay", "pin0": { "log_name":"", "phy_name":"" }, "pin1": { "log_name":"", "phy_name":"" }, "arrive":3.207, "delay":0.000 } ] } Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- -------------- ---------------- --------- --------------------- ------ CONSTRAINT 0.000 2.500 1 Clk_pad.bb_inst/PADDI SEIO18A_CORE CLOCK LATENCY 0.000 2.500 1 MyPLL/lscc_pll_inst/REFCK NET DELAY 0.300 2.800 1 MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK->MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS PLL_CORE 0.000 2.800 2 MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK->MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS (TOTAL_ADJUSTMENTS) PLL_CORE 0.000 2.800 2 MyPLL/lscc_pll_inst/clk2 NET DELAY 0.407 3.207 2 B_sig1.ff_inst/CLK CLOCK PIN 0.000 3.207 1 Uncertainty -(0.000) 3.207 Common Path Skew 0.000 3.207 Setup time -(-0.058) 3.265 ---------------------------------------- -------------- ---------------- --------- --------------------- ------ Required Time 3.265 Arrival Time -(1.631) ---------------------------------------- -------------- ---------------- --------- --------------------- ------ Path Slack (Passed) 1.634 ++++ Path 2 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Path Begin : A_Sig_c.ff_inst/Q (SLICE) Path End : A_Sig1.ff_inst/DF (SLICE) Source Clock : clk1 (R) Destination Clock: clk1 (R) Logic Level : 1 Delay Ratio : 57.2% (route), 42.8% (logic) Clock Skew : 0.000 ns Setup Constraint : 10.000 ns Common Path Skew : 0.000 ns Path Slack : 9.324 ns (Passed) Source Clock Path { "path_begin": { "type":"pin", "log_name":"Clk_pad.bb_inst/O", "phy_name":"Clk_pad.bb_inst/PADDI" }, "path_end": { "type":"pin", "log_name":"A_Sig_c.ff_inst/CLK", "phy_name":"A_Sig_c.SLICE_1/CLK" }, "path_sections":[ { "type":"net_delay", "net": { "log_name":"MyPLL/lscc_pll_inst/REFCK", "phy_name":"Clk_c" }, "arrive":0.300, "delay":0.300 }, { "type":"site_delay", "pin0": { "log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK", "phy_name":"MyPLL.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/REFCK" }, "pin1": { "log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP", "phy_name":"MyPLL.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP" }, "arrive":0.300, "delay":0.000 }, { "type":"site_delay", "pin0": { "log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK", "phy_name":"MyPLL.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/REFCK" }, "pin1": { "log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP", "phy_name":"MyPLL.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP" }, "arrive":0.300, "delay":0.000 }, { "type":"net_delay", "net": { "log_name":"MyPLL/lscc_pll_inst/clk1", "phy_name":"clk1" }, "arrive":0.707, "delay":0.407 }, { "type":"site_delay", "pin0": { "log_name":"", "phy_name":"" }, "pin1": { "log_name":"", "phy_name":"" }, "arrive":0.707, "delay":0.000 } ] } Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- -------------- ---------------- --------- --------------------- ------ Clk_pad.bb_inst/PADDI SEIO18A_CORE CLOCK LATENCY 0.000 0.000 1 MyPLL/lscc_pll_inst/REFCK NET DELAY 0.300 0.300 1 MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK->MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP PLL_CORE 0.000 0.300 2 MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK->MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP (TOTAL_ADJUSTMENTS) PLL_CORE 0.000 0.300 2 MyPLL/lscc_pll_inst/clk1 NET DELAY 0.407 0.707 2 A_Sig_c.ff_inst/CLK CLOCK PIN 0.000 0.707 1 Data Path { "path_begin": { "type":"pin", "log_name":"A_Sig_c.ff_inst/Q", "phy_name":"A_Sig_c.SLICE_1/Q0" }, "path_end": { "type":"pin", "log_name":"A_Sig1.ff_inst/DF", "phy_name":"A_Sig1.SLICE_2/M0" }, "path_sections":[ { "type":"site_delay", "pin0": { "log_name":"A_Sig_c.ff_inst/CLK", "phy_name":"A_Sig_c.SLICE_1/CLK" }, "pin1": { "log_name":"A_Sig_c.ff_inst/Q", "phy_name":"A_Sig_c.SLICE_1/Q0" }, "arrive":1.011, "delay":0.304 }, { "type":"net_delay", "net": { "log_name":"A_Sig", "phy_name":"A_Sig" }, "arrive":1.418, "delay":0.407 }, { "type":"site_delay", "pin0": { "log_name":"", "phy_name":"" }, "pin1": { "log_name":"", "phy_name":"" }, "arrive":1.418, "delay":0.000 } ] } Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- -------------- ---------------- --------- --------------------- ------ A_Sig_c.ff_inst/CLK->A_Sig_c.ff_inst/Q SLICE REG_DEL 0.304 1.011 2 A_Sig NET DELAY 0.407 1.418 2 A_Sig1.ff_inst/DF ENDPOINT 0.000 1.418 1 Destination Clock Path { "path_begin": { "type":"pin", "log_name":"Clk_pad.bb_inst/O", "phy_name":"Clk_pad.bb_inst/PADDI" }, "path_end": { "type":"pin", "log_name":"A_Sig1.ff_inst/CLK", "phy_name":"A_Sig1.SLICE_2/CLK" }, "path_sections":[ { "type":"site_delay", "pin0": { "log_name":"", "phy_name":"" }, "pin1": { "log_name":"", "phy_name":"" }, "arrive":10.000, "delay":0.000 }, { "type":"net_delay", "net": { "log_name":"MyPLL/lscc_pll_inst/REFCK", "phy_name":"Clk_c" }, "arrive":10.300, "delay":0.300 }, { "type":"site_delay", "pin0": { "log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK", "phy_name":"MyPLL.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/REFCK" }, "pin1": { "log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP", "phy_name":"MyPLL.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP" }, "arrive":10.300, "delay":0.000 }, { "type":"site_delay", "pin0": { "log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK", "phy_name":"MyPLL.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/REFCK" }, "pin1": { "log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP", "phy_name":"MyPLL.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP" }, "arrive":10.300, "delay":0.000 }, { "type":"net_delay", "net": { "log_name":"MyPLL/lscc_pll_inst/clk1", "phy_name":"clk1" }, "arrive":10.707, "delay":0.407 }, { "type":"site_delay", "pin0": { "log_name":"", "phy_name":"" }, "pin1": { "log_name":"", "phy_name":"" }, "arrive":10.707, "delay":0.000 } ] } Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- -------------- ---------------- --------- --------------------- ------ CONSTRAINT 0.000 10.000 1 Clk_pad.bb_inst/PADDI SEIO18A_CORE CLOCK LATENCY 0.000 10.000 1 MyPLL/lscc_pll_inst/REFCK NET DELAY 0.300 10.300 1 MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK->MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP PLL_CORE 0.000 10.300 2 MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK->MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP (TOTAL_ADJUSTMENTS) PLL_CORE 0.000 10.300 2 MyPLL/lscc_pll_inst/clk1 NET DELAY 0.407 10.707 2 A_Sig1.ff_inst/CLK CLOCK PIN 0.000 10.707 1 Uncertainty -(0.000) 10.707 Common Path Skew 0.000 10.707 Setup time -(-0.035) 10.742 ---------------------------------------- -------------- ---------------- --------- --------------------- ------ Required Time 10.742 Arrival Time -(1.418) ---------------------------------------- -------------- ---------------- --------- --------------------- ------ Path Slack (Passed) 9.324 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ End of Detailed Report for timing paths +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ ########################################################## 3 Setup at Speed Grade 9_High-Performance_1.0V Corner at 0 Degrees 3.1 Clock Summary 3.1.1 Clock "clk1" create_generated_clock -name {clk1} -source [get_pins {MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK}] -multiply_by 2 [get_pins {MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP }] Single Clock Domain ------------------------------------------------------------------------------------------------------- Clock clk1 | | Period | Frequency ------------------------------------------------------------------------------------------------------- From clk1 | Target | 10.000 ns | 100.000 MHz | Actual (all paths) | 2.000 ns | 500.000 MHz A_Sig_c.ff_inst/CLK (MPW) | (50% duty cycle) | 2.000 ns | 500.000 MHz ------------------------------------------------------------------------------------------------------- Clock Domain Crossing ------------------------------------------------------------------------------------------------------ Clock clk1 | Worst Time Between Edges | Comment ------------------------------------------------------------------------------------------------------ From clk2 | ---- | No path From Clk | ---- | No path ------------------------------------------------------------------------------------------------------ 3.1.2 Clock "clk2" create_generated_clock -name {clk2} -source [get_pins {MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK}] -multiply_by 2 [get_pins {MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS }] Single Clock Domain ------------------------------------------------------------------------------------------------------- Clock clk2 | | Period | Frequency ------------------------------------------------------------------------------------------------------- From clk2 | Target | 10.000 ns | 100.000 MHz | Actual (all paths) | 2.000 ns | 500.000 MHz B_sig1.ff_inst/CLK (MPW) | (50% duty cycle) | 2.000 ns | 500.000 MHz ------------------------------------------------------------------------------------------------------- Clock Domain Crossing ------------------------------------------------------------------------------------------------------ Clock clk2 | Worst Time Between Edges | Comment ------------------------------------------------------------------------------------------------------ From clk1 | 2.500 ns | slack = 1.633 ns From Clk | ---- | No path ------------------------------------------------------------------------------------------------------ 3.1.3 Clock "Clk" create_clock -name {Clk} -period 20 [get_nets Clk_c] Single Clock Domain ------------------------------------------------------------------------------------------------------- Clock Clk | | Period | Frequency ------------------------------------------------------------------------------------------------------- From Clk | Target | 20.000 ns | 50.000 MHz | Actual (all paths) | ---- | ---- ------------------------------------------------------------------------------------------------------- Clock Domain Crossing ------------------------------------------------------------------------------------------------------ Clock Clk | Worst Time Between Edges | Comment ------------------------------------------------------------------------------------------------------ From clk1 | ---- | No path From clk2 | ---- | No path ------------------------------------------------------------------------------------------------------ 3.2 Endpoint slacks ------------------------------------------------------- Listing 2 End Points | Slack ------------------------------------------------------- B_sig1.ff_inst/DF | 1.633 ns A_Sig1.ff_inst/DF | 9.323 ns ------------------------------------------------------- | Setup # of endpoints with negative slack:| 0 | ------------------------------------------------------- 3.3 Detailed Report XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX Detail report of critical paths XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Detailed Report for timing paths +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ ++++Path 1 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Path Begin : A_Sig_c.ff_inst/Q (SLICE) Path End : B_sig1.ff_inst/DF (SLICE) Source Clock : clk1 (R) Destination Clock: clk2 (R) Logic Level : 2 Delay Ratio : 44.0% (route), 56.0% (logic) Clock Skew : 0.000 ns Setup Constraint : 2.500 ns Common Path Skew : 0.000 ns Path Slack : 1.633 ns (Passed) Source Clock Path { "path_begin": { "type":"pin", "log_name":"Clk_pad.bb_inst/O", "phy_name":"Clk_pad.bb_inst/PADDI" }, "path_end": { "type":"pin", "log_name":"A_Sig_c.ff_inst/CLK", "phy_name":"A_Sig_c.SLICE_1/CLK" }, "path_sections":[ { "type":"net_delay", "net": { "log_name":"MyPLL/lscc_pll_inst/REFCK", "phy_name":"Clk_c" }, "arrive":0.300, "delay":0.300 }, { "type":"site_delay", "pin0": { "log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK", "phy_name":"MyPLL.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/REFCK" }, "pin1": { "log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP", "phy_name":"MyPLL.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP" }, "arrive":0.300, "delay":0.000 }, { "type":"site_delay", "pin0": { "log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK", "phy_name":"MyPLL.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/REFCK" }, "pin1": { "log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP", "phy_name":"MyPLL.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP" }, "arrive":0.300, "delay":0.000 }, { "type":"net_delay", "net": { "log_name":"MyPLL/lscc_pll_inst/clk1", "phy_name":"clk1" }, "arrive":0.707, "delay":0.407 }, { "type":"site_delay", "pin0": { "log_name":"", "phy_name":"" }, "pin1": { "log_name":"", "phy_name":"" }, "arrive":0.707, "delay":0.000 } ] } Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- -------------- ---------------- --------- --------------------- ------ Clk_pad.bb_inst/PADDI SEIO18A_CORE CLOCK LATENCY 0.000 0.000 1 MyPLL/lscc_pll_inst/REFCK NET DELAY 0.300 0.300 1 MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK->MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP PLL_CORE 0.000 0.300 2 MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK->MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP (TOTAL_ADJUSTMENTS) PLL_CORE 0.000 0.300 2 MyPLL/lscc_pll_inst/clk1 NET DELAY 0.407 0.707 2 A_Sig_c.ff_inst/CLK CLOCK PIN 0.000 0.707 1 Data Path { "path_begin": { "type":"pin", "log_name":"A_Sig_c.ff_inst/Q", "phy_name":"A_Sig_c.SLICE_1/Q0" }, "path_end": { "type":"pin", "log_name":"B_sig1.ff_inst/DF", "phy_name":"SLICE_0/DI0" }, "path_sections":[ { "type":"site_delay", "pin0": { "log_name":"A_Sig_c.ff_inst/CLK", "phy_name":"A_Sig_c.SLICE_1/CLK" }, "pin1": { "log_name":"A_Sig_c.ff_inst/Q", "phy_name":"A_Sig_c.SLICE_1/Q0" }, "arrive":1.012, "delay":0.305 }, { "type":"net_delay", "net": { "log_name":"A_Sig", "phy_name":"A_Sig" }, "arrive":1.419, "delay":0.407 }, { "type":"site_delay", "pin0": { "log_name":"i8_2_lut/B", "phy_name":"SLICE_0/B0" }, "pin1": { "log_name":"i8_2_lut/Z", "phy_name":"SLICE_0/F0" }, "arrive":1.632, "delay":0.213 }, { "type":"net_delay", "net": { "log_name":"out2_c_N_1", "phy_name":"out2_c_N_1" }, "arrive":1.632, "delay":0.000 }, { "type":"site_delay", "pin0": { "log_name":"", "phy_name":"" }, "pin1": { "log_name":"", "phy_name":"" }, "arrive":1.632, "delay":0.000 } ] } Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- -------------- ---------------- --------- --------------------- ------ A_Sig_c.ff_inst/CLK->A_Sig_c.ff_inst/Q SLICE REG_DEL 0.305 1.012 2 A_Sig NET DELAY 0.407 1.419 2 i8_2_lut/B->i8_2_lut/Z SLICE CTOF_DEL 0.213 1.632 1 out2_c_N_1 NET DELAY 0.000 1.632 1 B_sig1.ff_inst/DF ENDPOINT 0.000 1.632 1 Destination Clock Path { "path_begin": { "type":"pin", "log_name":"Clk_pad.bb_inst/O", "phy_name":"Clk_pad.bb_inst/PADDI" }, "path_end": { "type":"pin", "log_name":"B_sig1.ff_inst/CLK", "phy_name":"SLICE_0/CLK" }, "path_sections":[ { "type":"site_delay", "pin0": { "log_name":"", "phy_name":"" }, "pin1": { "log_name":"", "phy_name":"" }, "arrive":2.500, "delay":0.000 }, { "type":"net_delay", "net": { "log_name":"MyPLL/lscc_pll_inst/REFCK", "phy_name":"Clk_c" }, "arrive":2.800, "delay":0.300 }, { "type":"site_delay", "pin0": { "log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK", "phy_name":"MyPLL.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/REFCK" }, "pin1": { "log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS", "phy_name":"MyPLL.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS" }, "arrive":2.800, "delay":0.000 }, { "type":"site_delay", "pin0": { "log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK", "phy_name":"MyPLL.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/REFCK" }, "pin1": { "log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS", "phy_name":"MyPLL.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS" }, "arrive":2.800, "delay":0.000 }, { "type":"net_delay", "net": { "log_name":"MyPLL/lscc_pll_inst/clk2", "phy_name":"clk2" }, "arrive":3.207, "delay":0.407 }, { "type":"site_delay", "pin0": { "log_name":"", "phy_name":"" }, "pin1": { "log_name":"", "phy_name":"" }, "arrive":3.207, "delay":0.000 } ] } Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- -------------- ---------------- --------- --------------------- ------ CONSTRAINT 0.000 2.500 1 Clk_pad.bb_inst/PADDI SEIO18A_CORE CLOCK LATENCY 0.000 2.500 1 MyPLL/lscc_pll_inst/REFCK NET DELAY 0.300 2.800 1 MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK->MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS PLL_CORE 0.000 2.800 2 MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK->MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS (TOTAL_ADJUSTMENTS) PLL_CORE 0.000 2.800 2 MyPLL/lscc_pll_inst/clk2 NET DELAY 0.407 3.207 2 B_sig1.ff_inst/CLK CLOCK PIN 0.000 3.207 1 Uncertainty -(0.000) 3.207 Common Path Skew 0.000 3.207 Setup time -(-0.058) 3.265 ---------------------------------------- -------------- ---------------- --------- --------------------- ------ Required Time 3.265 Arrival Time -(1.632) ---------------------------------------- -------------- ---------------- --------- --------------------- ------ Path Slack (Passed) 1.633 ++++ Path 2 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Path Begin : A_Sig_c.ff_inst/Q (SLICE) Path End : A_Sig1.ff_inst/DF (SLICE) Source Clock : clk1 (R) Destination Clock: clk1 (R) Logic Level : 1 Delay Ratio : 57.2% (route), 42.8% (logic) Clock Skew : 0.000 ns Setup Constraint : 10.000 ns Common Path Skew : 0.000 ns Path Slack : 9.323 ns (Passed) Source Clock Path { "path_begin": { "type":"pin", "log_name":"Clk_pad.bb_inst/O", "phy_name":"Clk_pad.bb_inst/PADDI" }, "path_end": { "type":"pin", "log_name":"A_Sig_c.ff_inst/CLK", "phy_name":"A_Sig_c.SLICE_1/CLK" }, "path_sections":[ { "type":"net_delay", "net": { "log_name":"MyPLL/lscc_pll_inst/REFCK", "phy_name":"Clk_c" }, "arrive":0.300, "delay":0.300 }, { "type":"site_delay", "pin0": { "log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK", "phy_name":"MyPLL.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/REFCK" }, "pin1": { "log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP", "phy_name":"MyPLL.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP" }, "arrive":0.300, "delay":0.000 }, { "type":"site_delay", "pin0": { "log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK", "phy_name":"MyPLL.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/REFCK" }, "pin1": { "log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP", "phy_name":"MyPLL.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP" }, "arrive":0.300, "delay":0.000 }, { "type":"net_delay", "net": { "log_name":"MyPLL/lscc_pll_inst/clk1", "phy_name":"clk1" }, "arrive":0.707, "delay":0.407 }, { "type":"site_delay", "pin0": { "log_name":"", "phy_name":"" }, "pin1": { "log_name":"", "phy_name":"" }, "arrive":0.707, "delay":0.000 } ] } Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- -------------- ---------------- --------- --------------------- ------ Clk_pad.bb_inst/PADDI SEIO18A_CORE CLOCK LATENCY 0.000 0.000 1 MyPLL/lscc_pll_inst/REFCK NET DELAY 0.300 0.300 1 MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK->MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP PLL_CORE 0.000 0.300 2 MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK->MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP (TOTAL_ADJUSTMENTS) PLL_CORE 0.000 0.300 2 MyPLL/lscc_pll_inst/clk1 NET DELAY 0.407 0.707 2 A_Sig_c.ff_inst/CLK CLOCK PIN 0.000 0.707 1 Data Path { "path_begin": { "type":"pin", "log_name":"A_Sig_c.ff_inst/Q", "phy_name":"A_Sig_c.SLICE_1/Q0" }, "path_end": { "type":"pin", "log_name":"A_Sig1.ff_inst/DF", "phy_name":"A_Sig1.SLICE_2/M0" }, "path_sections":[ { "type":"site_delay", "pin0": { "log_name":"A_Sig_c.ff_inst/CLK", "phy_name":"A_Sig_c.SLICE_1/CLK" }, "pin1": { "log_name":"A_Sig_c.ff_inst/Q", "phy_name":"A_Sig_c.SLICE_1/Q0" }, "arrive":1.012, "delay":0.305 }, { "type":"net_delay", "net": { "log_name":"A_Sig", "phy_name":"A_Sig" }, "arrive":1.419, "delay":0.407 }, { "type":"site_delay", "pin0": { "log_name":"", "phy_name":"" }, "pin1": { "log_name":"", "phy_name":"" }, "arrive":1.419, "delay":0.000 } ] } Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- -------------- ---------------- --------- --------------------- ------ A_Sig_c.ff_inst/CLK->A_Sig_c.ff_inst/Q SLICE REG_DEL 0.305 1.012 2 A_Sig NET DELAY 0.407 1.419 2 A_Sig1.ff_inst/DF ENDPOINT 0.000 1.419 1 Destination Clock Path { "path_begin": { "type":"pin", "log_name":"Clk_pad.bb_inst/O", "phy_name":"Clk_pad.bb_inst/PADDI" }, "path_end": { "type":"pin", "log_name":"A_Sig1.ff_inst/CLK", "phy_name":"A_Sig1.SLICE_2/CLK" }, "path_sections":[ { "type":"site_delay", "pin0": { "log_name":"", "phy_name":"" }, "pin1": { "log_name":"", "phy_name":"" }, "arrive":10.000, "delay":0.000 }, { "type":"net_delay", "net": { "log_name":"MyPLL/lscc_pll_inst/REFCK", "phy_name":"Clk_c" }, "arrive":10.300, "delay":0.300 }, { "type":"site_delay", "pin0": { "log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK", "phy_name":"MyPLL.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/REFCK" }, "pin1": { "log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP", "phy_name":"MyPLL.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP" }, "arrive":10.300, "delay":0.000 }, { "type":"site_delay", "pin0": { "log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK", "phy_name":"MyPLL.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/REFCK" }, "pin1": { "log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP", "phy_name":"MyPLL.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP" }, "arrive":10.300, "delay":0.000 }, { "type":"net_delay", "net": { "log_name":"MyPLL/lscc_pll_inst/clk1", "phy_name":"clk1" }, "arrive":10.707, "delay":0.407 }, { "type":"site_delay", "pin0": { "log_name":"", "phy_name":"" }, "pin1": { "log_name":"", "phy_name":"" }, "arrive":10.707, "delay":0.000 } ] } Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- -------------- ---------------- --------- --------------------- ------ CONSTRAINT 0.000 10.000 1 Clk_pad.bb_inst/PADDI SEIO18A_CORE CLOCK LATENCY 0.000 10.000 1 MyPLL/lscc_pll_inst/REFCK NET DELAY 0.300 10.300 1 MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK->MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP PLL_CORE 0.000 10.300 2 MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK->MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP (TOTAL_ADJUSTMENTS) PLL_CORE 0.000 10.300 2 MyPLL/lscc_pll_inst/clk1 NET DELAY 0.407 10.707 2 A_Sig1.ff_inst/CLK CLOCK PIN 0.000 10.707 1 Uncertainty -(0.000) 10.707 Common Path Skew 0.000 10.707 Setup time -(-0.035) 10.742 ---------------------------------------- -------------- ---------------- --------- --------------------- ------ Required Time 10.742 Arrival Time -(1.419) ---------------------------------------- -------------- ---------------- --------- --------------------- ------ Path Slack (Passed) 9.323 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ End of Detailed Report for timing paths +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ ########################################################## 4 Hold at Speed Grade m Corner at 0 Degrees 4.1 Endpoint slacks ------------------------------------------------------- Listing 2 End Points | Slack ------------------------------------------------------- B_sig1.ff_inst/DF | 0.475 ns A_Sig1.ff_inst/DF | 0.483 ns ------------------------------------------------------- | Hold # of endpoints with negative slack: | 0 | ------------------------------------------------------- 4.2 Detailed Report XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX Detail report of critical paths XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Detailed Report for timing paths +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ ++++Path 1 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Path Begin : B_sig_c.ff_inst/Q (SLICE) Path End : B_sig1.ff_inst/DF (SLICE) Source Clock : clk2 (R) Destination Clock: clk2 (R) Logic Level : 2 Delay Ratio : 50.9% (route), 49.1% (logic) Clock Skew : 0.000 ns Hold Constraint : 0.000 ns Common Path Skew : 0.000 ns Path Slack : 0.475 ns (Passed) Source Clock Path { "path_begin": { "type":"pin", "log_name":"Clk_pad.bb_inst/O", "phy_name":"Clk_pad.bb_inst/PADDI" }, "path_end": { "type":"pin", "log_name":"B_sig_c.ff_inst/CLK", "phy_name":"B_sig_c.SLICE_3/CLK" }, "path_sections":[ { "type":"net_delay", "net": { "log_name":"MyPLL/lscc_pll_inst/REFCK", "phy_name":"Clk_c" }, "arrive":0.300, "delay":0.300 }, { "type":"site_delay", "pin0": { "log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK", "phy_name":"MyPLL.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/REFCK" }, "pin1": { "log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS", "phy_name":"MyPLL.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS" }, "arrive":0.300, "delay":0.000 }, { "type":"site_delay", "pin0": { "log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK", "phy_name":"MyPLL.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/REFCK" }, "pin1": { "log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS", "phy_name":"MyPLL.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS" }, "arrive":0.300, "delay":0.000 }, { "type":"net_delay", "net": { "log_name":"MyPLL/lscc_pll_inst/clk2", "phy_name":"clk2" }, "arrive":0.707, "delay":0.407 }, { "type":"site_delay", "pin0": { "log_name":"", "phy_name":"" }, "pin1": { "log_name":"", "phy_name":"" }, "arrive":0.707, "delay":0.000 } ] } Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- -------------- ---------------- ----- --------------------- ------ Clk_pad.bb_inst/PADDI SEIO18A_CORE CLOCK LATENCY 0.000 0.000 1 MyPLL/lscc_pll_inst/REFCK NET DELAY 0.300 0.300 1 MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK->MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS PLL_CORE 0.000 0.300 2 MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK->MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS (TOTAL_ADJUSTMENTS) PLL_CORE 0.000 0.300 2 MyPLL/lscc_pll_inst/clk2 NET DELAY 0.407 0.707 2 B_sig_c.ff_inst/CLK CLOCK PIN 0.000 0.707 1 Data Path { "path_begin": { "type":"pin", "log_name":"B_sig_c.ff_inst/Q", "phy_name":"B_sig_c.SLICE_3/Q0" }, "path_end": { "type":"pin", "log_name":"B_sig1.ff_inst/DF", "phy_name":"SLICE_0/DI0" }, "path_sections":[ { "type":"site_delay", "pin0": { "log_name":"B_sig_c.ff_inst/CLK", "phy_name":"B_sig_c.SLICE_3/CLK" }, "pin1": { "log_name":"B_sig_c.ff_inst/Q", "phy_name":"B_sig_c.SLICE_3/Q0" }, "arrive":0.880, "delay":0.173 }, { "type":"net_delay", "net": { "log_name":"B_sig", "phy_name":"B_sig" }, "arrive":1.180, "delay":0.300 }, { "type":"site_delay", "pin0": { "log_name":"i8_2_lut/A", "phy_name":"SLICE_0/A0" }, "pin1": { "log_name":"i8_2_lut/Z", "phy_name":"SLICE_0/F0" }, "arrive":1.296, "delay":0.116 }, { "type":"net_delay", "net": { "log_name":"out2_c_N_1", "phy_name":"out2_c_N_1" }, "arrive":1.296, "delay":0.000 }, { "type":"site_delay", "pin0": { "log_name":"", "phy_name":"" }, "pin1": { "log_name":"", "phy_name":"" }, "arrive":1.296, "delay":0.000 } ] } Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- -------------- ---------------- ----- --------------------- ------ B_sig_c.ff_inst/CLK->B_sig_c.ff_inst/Q SLICE REG_DEL 0.173 0.880 1 B_sig NET DELAY 0.300 1.180 1 i8_2_lut/A->i8_2_lut/Z SLICE CTOF_DEL 0.116 1.296 1 out2_c_N_1 NET DELAY 0.000 1.296 1 B_sig1.ff_inst/DF ENDPOINT 0.000 1.296 1 Destination Clock Path { "path_begin": { "type":"pin", "log_name":"Clk_pad.bb_inst/O", "phy_name":"Clk_pad.bb_inst/PADDI" }, "path_end": { "type":"pin", "log_name":"B_sig1.ff_inst/CLK", "phy_name":"SLICE_0/CLK" }, "path_sections":[ { "type":"site_delay", "pin0": { "log_name":"", "phy_name":"" }, "pin1": { "log_name":"", "phy_name":"" }, "arrive":0.000, "delay":0.000 }, { "type":"net_delay", "net": { "log_name":"MyPLL/lscc_pll_inst/REFCK", "phy_name":"Clk_c" }, "arrive":0.300, "delay":0.300 }, { "type":"site_delay", "pin0": { "log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK", "phy_name":"MyPLL.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/REFCK" }, "pin1": { "log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS", "phy_name":"MyPLL.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS" }, "arrive":0.300, "delay":0.000 }, { "type":"site_delay", "pin0": { "log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK", "phy_name":"MyPLL.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/REFCK" }, "pin1": { "log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS", "phy_name":"MyPLL.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS" }, "arrive":0.300, "delay":0.000 }, { "type":"net_delay", "net": { "log_name":"MyPLL/lscc_pll_inst/clk2", "phy_name":"clk2" }, "arrive":0.707, "delay":0.407 }, { "type":"site_delay", "pin0": { "log_name":"", "phy_name":"" }, "pin1": { "log_name":"", "phy_name":"" }, "arrive":0.707, "delay":0.000 } ] } Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- -------------- ---------------- ----- --------------------- ------ CONSTRAINT 0.000 0.000 1 Clk_pad.bb_inst/PADDI SEIO18A_CORE CLOCK LATENCY 0.000 0.000 1 MyPLL/lscc_pll_inst/REFCK NET DELAY 0.300 0.300 1 MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK->MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS PLL_CORE 0.000 0.300 2 MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK->MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS (TOTAL_ADJUSTMENTS) PLL_CORE 0.000 0.300 2 MyPLL/lscc_pll_inst/clk2 NET DELAY 0.407 0.707 2 B_sig1.ff_inst/CLK CLOCK PIN 0.000 0.707 1 Uncertainty 0.000 0.707 Common Path Skew 0.000 0.707 Hold time 0.114 0.821 ---------------------------------------- -------------- ---------------- ----- --------------------- ------ Required Time -0.821 Arrival Time 1.296 ---------------------------------------- -------------- ---------------- ----- --------------------- ------ Path Slack (Passed) 0.475 ++++ Path 2 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Path Begin : A_Sig_c.ff_inst/Q (SLICE) Path End : A_Sig1.ff_inst/DF (SLICE) Source Clock : clk1 (R) Destination Clock: clk1 (R) Logic Level : 1 Delay Ratio : 70.2% (route), 29.8% (logic) Clock Skew : 0.000 ns Hold Constraint : 0.000 ns Common Path Skew : 0.000 ns Path Slack : 0.483 ns (Passed) Source Clock Path { "path_begin": { "type":"pin", "log_name":"Clk_pad.bb_inst/O", "phy_name":"Clk_pad.bb_inst/PADDI" }, "path_end": { "type":"pin", "log_name":"A_Sig_c.ff_inst/CLK", "phy_name":"A_Sig_c.SLICE_1/CLK" }, "path_sections":[ { "type":"net_delay", "net": { "log_name":"MyPLL/lscc_pll_inst/REFCK", "phy_name":"Clk_c" }, "arrive":0.300, "delay":0.300 }, { "type":"site_delay", "pin0": { "log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK", "phy_name":"MyPLL.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/REFCK" }, "pin1": { "log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP", "phy_name":"MyPLL.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP" }, "arrive":0.300, "delay":0.000 }, { "type":"site_delay", "pin0": { "log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK", "phy_name":"MyPLL.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/REFCK" }, "pin1": { "log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP", "phy_name":"MyPLL.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP" }, "arrive":0.300, "delay":0.000 }, { "type":"net_delay", "net": { "log_name":"MyPLL/lscc_pll_inst/clk1", "phy_name":"clk1" }, "arrive":0.707, "delay":0.407 }, { "type":"site_delay", "pin0": { "log_name":"", "phy_name":"" }, "pin1": { "log_name":"", "phy_name":"" }, "arrive":0.707, "delay":0.000 } ] } Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- -------------- ---------------- ----- --------------------- ------ Clk_pad.bb_inst/PADDI SEIO18A_CORE CLOCK LATENCY 0.000 0.000 1 MyPLL/lscc_pll_inst/REFCK NET DELAY 0.300 0.300 1 MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK->MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP PLL_CORE 0.000 0.300 2 MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK->MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP (TOTAL_ADJUSTMENTS) PLL_CORE 0.000 0.300 2 MyPLL/lscc_pll_inst/clk1 NET DELAY 0.407 0.707 2 A_Sig_c.ff_inst/CLK CLOCK PIN 0.000 0.707 1 Data Path { "path_begin": { "type":"pin", "log_name":"A_Sig_c.ff_inst/Q", "phy_name":"A_Sig_c.SLICE_1/Q0" }, "path_end": { "type":"pin", "log_name":"A_Sig1.ff_inst/DF", "phy_name":"A_Sig1.SLICE_2/M0" }, "path_sections":[ { "type":"site_delay", "pin0": { "log_name":"A_Sig_c.ff_inst/CLK", "phy_name":"A_Sig_c.SLICE_1/CLK" }, "pin1": { "log_name":"A_Sig_c.ff_inst/Q", "phy_name":"A_Sig_c.SLICE_1/Q0" }, "arrive":0.880, "delay":0.173 }, { "type":"net_delay", "net": { "log_name":"A_Sig", "phy_name":"A_Sig" }, "arrive":1.287, "delay":0.407 }, { "type":"site_delay", "pin0": { "log_name":"", "phy_name":"" }, "pin1": { "log_name":"", "phy_name":"" }, "arrive":1.287, "delay":0.000 } ] } Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- -------------- ---------------- ----- --------------------- ------ A_Sig_c.ff_inst/CLK->A_Sig_c.ff_inst/Q SLICE REG_DEL 0.173 0.880 2 A_Sig NET DELAY 0.407 1.287 2 A_Sig1.ff_inst/DF ENDPOINT 0.000 1.287 1 Destination Clock Path { "path_begin": { "type":"pin", "log_name":"Clk_pad.bb_inst/O", "phy_name":"Clk_pad.bb_inst/PADDI" }, "path_end": { "type":"pin", "log_name":"A_Sig1.ff_inst/CLK", "phy_name":"A_Sig1.SLICE_2/CLK" }, "path_sections":[ { "type":"site_delay", "pin0": { "log_name":"", "phy_name":"" }, "pin1": { "log_name":"", "phy_name":"" }, "arrive":0.000, "delay":0.000 }, { "type":"net_delay", "net": { "log_name":"MyPLL/lscc_pll_inst/REFCK", "phy_name":"Clk_c" }, "arrive":0.300, "delay":0.300 }, { "type":"site_delay", "pin0": { "log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK", "phy_name":"MyPLL.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/REFCK" }, "pin1": { "log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP", "phy_name":"MyPLL.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP" }, "arrive":0.300, "delay":0.000 }, { "type":"site_delay", "pin0": { "log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK", "phy_name":"MyPLL.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/REFCK" }, "pin1": { "log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP", "phy_name":"MyPLL.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP" }, "arrive":0.300, "delay":0.000 }, { "type":"net_delay", "net": { "log_name":"MyPLL/lscc_pll_inst/clk1", "phy_name":"clk1" }, "arrive":0.707, "delay":0.407 }, { "type":"site_delay", "pin0": { "log_name":"", "phy_name":"" }, "pin1": { "log_name":"", "phy_name":"" }, "arrive":0.707, "delay":0.000 } ] } Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- -------------- ---------------- ----- --------------------- ------ CONSTRAINT 0.000 0.000 1 Clk_pad.bb_inst/PADDI SEIO18A_CORE CLOCK LATENCY 0.000 0.000 1 MyPLL/lscc_pll_inst/REFCK NET DELAY 0.300 0.300 1 MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK->MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP PLL_CORE 0.000 0.300 2 MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK->MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP (TOTAL_ADJUSTMENTS) PLL_CORE 0.000 0.300 2 MyPLL/lscc_pll_inst/clk1 NET DELAY 0.407 0.707 2 A_Sig1.ff_inst/CLK CLOCK PIN 0.000 0.707 1 Uncertainty 0.000 0.707 Common Path Skew 0.000 0.707 Hold time 0.097 0.804 ---------------------------------------- -------------- ---------------- ----- --------------------- ------ Required Time -0.804 Arrival Time 1.287 ---------------------------------------- -------------- ---------------- ----- --------------------- ------ Path Slack (Passed) 0.483 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ End of Detailed Report for timing paths +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ ##########################################################

















































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