Timing Report
Lattice Timing Report - Setup and Hold, Version Radiant Software (64-bit) 2023.2.1.288.0
Tue Jun 25 17:24:30 2024
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2023 Lattice Semiconductor Corporation, All rights reserved.
Command line: timing -sethld -v 10 -u 10 -endpoints 10 -nperend 5 -sp 9_High-Performance_1.0V -hsp m -pwrprd -html -rpt LAB01_impl_1.twr LAB01_impl_1.udb -gui -msgset C:/Users/ssyahril/OneDrive - Lattice Semiconductor Corp/Documents/Insights/Constraint Deep Dive/Radiant Lab/LAB_01/promote.xml
-------------------------------------------
Design: top
Family: LFCPNX
Device: LFCPNX-50
Package: CBG256
Performance: 9_High-Performance_1.0V
Package Status: Final Version 16
Performance Hardware Data Status : Final Version 3.9
-------------------------------------------
=====================================================================
Table of Contents
=====================================================================
1 Timing Overview
1.1 SDC Constraints
1.2 Constraint Coverage
1.3 Overall Summary
1.4 Unconstrained Report
1.5 Combinational Loop
1.6 Error/Warning Messages
2 Setup at Speed Grade 9_High-Performance_1.0V Corner at 85 Degrees
2.1 Clock Summary
2.2 Endpoint slacks
2.3 Detailed Report
3 Setup at Speed Grade 9_High-Performance_1.0V Corner at 0 Degrees
3.1 Clock Summary
3.2 Endpoint slacks
3.3 Detailed Report
4 Hold at Speed Grade m Corner at 0 Degrees
4.1 Endpoint slacks
4.2 Detailed Report
=====================================================================
End of Table of Contents
=====================================================================
1 Timing Overview
1.1 SDC Constraints
create_generated_clock -name {clk2} -source [get_pins {MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK}] -multiply_by 2 [get_pins {MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS }]
create_generated_clock -name {clk1} -source [get_pins {MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK}] -multiply_by 2 [get_pins {MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP }]
create_clock -name {Clk} -period 20 [get_nets Clk_c]
1.2 Constraint Coverage
Constraint Coverage: 45.4545%
1.3 Overall Summary
Setup at Speed Grade 9_High-Performance_1.0V Corner at 85 Degrees Timing Errors: 1 endpoints; Total Negative Slack: 1.728 ns
Setup at Speed Grade 9_High-Performance_1.0V Corner at 0 Degrees Timing Errors: 1 endpoints; Total Negative Slack: 1.750 ns
Hold at Speed Grade m Corner at 0 Degrees Timing Errors: 0 endpoints; Total Negative Slack: 0.000 ns
1.4 Unconstrained Report
1.4.1 Unconstrained Start/End Points
Clocked but unconstrained timing start points
-------------------------------------------------------------------
Listing 2 Start Points | Type
-------------------------------------------------------------------
B_sig1.ff_inst/Q | No required time
A_Sig1.ff_inst/Q | No required time
-------------------------------------------------------------------
|
Number of unconstrained timing start po |
ints | 2
|
-------------------------------------------------------------------
Clocked but unconstrained timing end points
-------------------------------------------------------------------
Listing 2 End Points | Type
-------------------------------------------------------------------
A_Sig_c.ff_inst/DF | No arrival time
B_sig_c.ff_inst/DF | No arrival time
-------------------------------------------------------------------
|
Number of unconstrained timing end poin |
ts | 2
|
-------------------------------------------------------------------
1.4.2 Start/End Points Without Timing Constraints
I/O ports without constraint
----------------------------
Possible constraints to use on I/O ports are:
set_input_delay,
set_output_delay,
set_max_delay,
create_clock,
create_generated_clock,
...
-------------------------------------------------------------------
Listing 5 Start or End Points | Type
-------------------------------------------------------------------
Clk | input
B | input
A | input
out2 | output
out1 | output
-------------------------------------------------------------------
|
Number of I/O ports without constraint | 5
|
-------------------------------------------------------------------
Nets without clock definition
Define a clock on a top level port or a generated clock on a clock divider pin associated with this net(s).
--------------------------------------------------
There is no instance satisfying reporting criteria
1.5 Combinational Loop
None
1.6 Error/Warning Messages
WARNING "70009502" - The preferred point for defining clocks is top level ports and driver pins. Pad delays will not be taken into consideration if clocks are defined on nets.
2 Setup at Speed Grade 9_High-Performance_1.0V Corner at 85 Degrees
2.1 Clock Summary
2.1.1 Clock "clk1"
create_generated_clock -name {clk1} -source [get_pins {MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK}] -multiply_by 2 [get_pins {MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP }]
Single Clock Domain
-------------------------------------------------------------------------------------------------------
Clock clk1 | | Period | Frequency
-------------------------------------------------------------------------------------------------------
From clk1 | Target | 10.000 ns | 100.000 MHz
| Actual (all paths) | 2.801 ns | 357.015 MHz
A_Sig_c.ff_inst/CLK (MPW) | (50% duty cycle) | 2.000 ns | 500.000 MHz
-------------------------------------------------------------------------------------------------------
Clock Domain Crossing
------------------------------------------------------------------------------------------------------
Clock clk1 | Worst Time Between Edges | Comment
------------------------------------------------------------------------------------------------------
From clk2 | ---- | No path
From Clk | ---- | No path
------------------------------------------------------------------------------------------------------
2.1.2 Clock "clk2"
create_generated_clock -name {clk2} -source [get_pins {MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK}] -multiply_by 2 [get_pins {MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS }]
Single Clock Domain
-------------------------------------------------------------------------------------------------------
Clock clk2 | | Period | Frequency
-------------------------------------------------------------------------------------------------------
From clk2 | Target | 10.000 ns | 100.000 MHz
| Actual (all paths) | 2.000 ns | 500.000 MHz
B_sig1.ff_inst/CLK (MPW) | (50% duty cycle) | 2.000 ns | 500.000 MHz
-------------------------------------------------------------------------------------------------------
Clock Domain Crossing
------------------------------------------------------------------------------------------------------
Clock clk2 | Worst Time Between Edges | Comment
------------------------------------------------------------------------------------------------------
From clk1 | 2.500 ns | slack = -1.728 ns
From Clk | ---- | No path
------------------------------------------------------------------------------------------------------
2.1.3 Clock "Clk"
create_clock -name {Clk} -period 20 [get_nets Clk_c]
Single Clock Domain
-------------------------------------------------------------------------------------------------------
Clock Clk | | Period | Frequency
-------------------------------------------------------------------------------------------------------
From Clk | Target | 20.000 ns | 50.000 MHz
| Actual (all paths) | ---- | ----
-------------------------------------------------------------------------------------------------------
Clock Domain Crossing
------------------------------------------------------------------------------------------------------
Clock Clk | Worst Time Between Edges | Comment
------------------------------------------------------------------------------------------------------
From clk1 | ---- | No path
From clk2 | ---- | No path
------------------------------------------------------------------------------------------------------
2.2 Endpoint slacks
-------------------------------------------------------
Listing 2 End Points | Slack
-------------------------------------------------------
B_sig1.ff_inst/DF | -1.728 ns
A_Sig1.ff_inst/DF | 7.199 ns
-------------------------------------------------------
|
Setup # of endpoints with negative slack:| 1
|
-------------------------------------------------------
2.3 Detailed Report
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
Detail report of critical paths
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Detailed Report for timing paths
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++++Path 1 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Path Begin : A_Sig_c.ff_inst/Q (SLICE_R4C4D)
Path End : B_sig1.ff_inst/DF (SLICE_R50C100D)
Source Clock : clk1 (R)
Destination Clock: clk2 (R)
Logic Level : 2
Delay Ratio : 87.8% (route), 12.2% (logic)
Clock Skew : -0.163 ns
Setup Constraint : 2.500 ns
Common Path Skew : 0.017 ns
Path Slack : -1.728 ns (Failed)
Source Clock Path
{
"path_begin":
{
"type":"pin",
"log_name":"Clk_pad.bb_inst/O",
"phy_name":"Clk_pad.bb_inst/PADDI"
},
"path_end":
{
"type":"pin",
"log_name":"A_Sig_c.ff_inst/CLK",
"phy_name":"A_Sig_c.SLICE_1/CLK"
},
"path_sections":[
{
"type":"net_delay",
"net":
{
"log_name":"MyPLL/lscc_pll_inst/REFCK",
"phy_name":"Clk_c"
},
"arrive":0.309,
"delay":0.309
},
{
"type":"site_delay",
"pin0":
{
"log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK",
"phy_name":"MyPLL.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/REFCK"
},
"pin1":
{
"log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP",
"phy_name":"MyPLL.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP"
},
"arrive":0.309,
"delay":0.000
},
{
"type":"site_delay",
"pin0":
{
"log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK",
"phy_name":"MyPLL.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/REFCK"
},
"pin1":
{
"log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP",
"phy_name":"MyPLL.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP"
},
"arrive":0.309,
"delay":0.000
},
{
"type":"net_delay",
"net":
{
"log_name":"MyPLL/lscc_pll_inst/clk1",
"phy_name":"clk1"
},
"arrive":2.808,
"delay":2.499
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":2.808,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- ---------------- ---------------- --------- --------------------- ------
Clk_pad.bb_inst/PADDI SEIO18A_CORE_K15 CLOCK LATENCY 0.000 0.000 1
MyPLL/lscc_pll_inst/REFCK NET DELAY 0.309 0.309 1
MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK->MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP
PLL_CORE_PLL_LLC 0.000 0.309 2
MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK->MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP (TOTAL_ADJUSTMENTS)
PLL_CORE_PLL_LLC 0.000 0.309 2
MyPLL/lscc_pll_inst/clk1 NET DELAY 2.499 2.808 2
A_Sig_c.ff_inst/CLK CLOCK PIN 0.000 2.808 1
Data Path
{
"path_begin":
{
"type":"pin",
"log_name":"A_Sig_c.ff_inst/Q",
"phy_name":"A_Sig_c.SLICE_1/Q0"
},
"path_end":
{
"type":"pin",
"log_name":"B_sig1.ff_inst/DF",
"phy_name":"SLICE_0/DI0"
},
"path_sections":[
{
"type":"site_delay",
"pin0":
{
"log_name":"A_Sig_c.ff_inst/CLK",
"phy_name":"A_Sig_c.SLICE_1/CLK"
},
"pin1":
{
"log_name":"A_Sig_c.ff_inst/Q",
"phy_name":"A_Sig_c.SLICE_1/Q0"
},
"arrive":3.100,
"delay":0.292
},
{
"type":"net_delay",
"net":
{
"log_name":"A_Sig",
"phy_name":"A_Sig"
},
"arrive":6.735,
"delay":3.635
},
{
"type":"site_delay",
"pin0":
{
"log_name":"i8_2_lut/B",
"phy_name":"SLICE_0/D0"
},
"pin1":
{
"log_name":"i8_2_lut/Z",
"phy_name":"SLICE_0/F0"
},
"arrive":6.948,
"delay":0.213
},
{
"type":"net_delay",
"net":
{
"log_name":"out2_c_N_1",
"phy_name":"out2_c_N_1"
},
"arrive":6.948,
"delay":0.000
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":6.948,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- ---------------- ---------------- --------- --------------------- ------
A_Sig_c.ff_inst/CLK->A_Sig_c.ff_inst/Q SLICE_R4C4D REG_DEL 0.292 3.100 2
A_Sig NET DELAY 3.635 6.735 2
i8_2_lut/B->i8_2_lut/Z SLICE_R50C100D CTOF_DEL 0.213 6.948 1
out2_c_N_1 NET DELAY 0.000 6.948 1
B_sig1.ff_inst/DF ENDPOINT 0.000 6.948 1
Destination Clock Path
{
"path_begin":
{
"type":"pin",
"log_name":"Clk_pad.bb_inst/O",
"phy_name":"Clk_pad.bb_inst/PADDI"
},
"path_end":
{
"type":"pin",
"log_name":"B_sig1.ff_inst/CLK",
"phy_name":"SLICE_0/CLK"
},
"path_sections":[
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":2.500,
"delay":0.000
},
{
"type":"net_delay",
"net":
{
"log_name":"MyPLL/lscc_pll_inst/REFCK",
"phy_name":"Clk_c"
},
"arrive":2.790,
"delay":0.290
},
{
"type":"site_delay",
"pin0":
{
"log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK",
"phy_name":"MyPLL.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/REFCK"
},
"pin1":
{
"log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS",
"phy_name":"MyPLL.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS"
},
"arrive":2.790,
"delay":0.000
},
{
"type":"site_delay",
"pin0":
{
"log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK",
"phy_name":"MyPLL.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/REFCK"
},
"pin1":
{
"log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS",
"phy_name":"MyPLL.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS"
},
"arrive":2.790,
"delay":0.000
},
{
"type":"net_delay",
"net":
{
"log_name":"MyPLL/lscc_pll_inst/clk2",
"phy_name":"clk2"
},
"arrive":5.145,
"delay":2.355
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":5.145,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- ---------------- ---------------- --------- --------------------- ------
CONSTRAINT 0.000 2.500 1
Clk_pad.bb_inst/PADDI SEIO18A_CORE_K15 CLOCK LATENCY 0.000 2.500 1
MyPLL/lscc_pll_inst/REFCK NET DELAY 0.290 2.790 1
MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK->MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS
PLL_CORE_PLL_LLC 0.000 2.790 2
MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK->MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS (TOTAL_ADJUSTMENTS)
PLL_CORE_PLL_LLC 0.000 2.790 2
MyPLL/lscc_pll_inst/clk2 NET DELAY 2.355 5.145 2
B_sig1.ff_inst/CLK CLOCK PIN 0.000 5.145 1
Uncertainty -(0.000) 5.145
Common Path Skew 0.017 5.162
Setup time -(-0.058) 5.220
---------------------------------------- ---------------- ---------------- --------- --------------------- ------
Required Time 5.220
Arrival Time -(6.948)
---------------------------------------- ---------------- ---------------- --------- --------------------- ------
Path Slack (Failed) -1.728
++++ Path 2 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Path Begin : A_Sig_c.ff_inst/Q (SLICE_R4C4D)
Path End : A_Sig1.ff_inst/DF (SLICE_R2C100D)
Source Clock : clk1 (R)
Destination Clock: clk1 (R)
Logic Level : 1
Delay Ratio : 89.3% (route), 10.7% (logic)
Clock Skew : -0.163 ns
Setup Constraint : 10.000 ns
Common Path Skew : 0.057 ns
Path Slack : 7.199 ns (Passed)
Source Clock Path
{
"path_begin":
{
"type":"pin",
"log_name":"Clk_pad.bb_inst/O",
"phy_name":"Clk_pad.bb_inst/PADDI"
},
"path_end":
{
"type":"pin",
"log_name":"A_Sig_c.ff_inst/CLK",
"phy_name":"A_Sig_c.SLICE_1/CLK"
},
"path_sections":[
{
"type":"net_delay",
"net":
{
"log_name":"MyPLL/lscc_pll_inst/REFCK",
"phy_name":"Clk_c"
},
"arrive":0.309,
"delay":0.309
},
{
"type":"site_delay",
"pin0":
{
"log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK",
"phy_name":"MyPLL.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/REFCK"
},
"pin1":
{
"log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP",
"phy_name":"MyPLL.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP"
},
"arrive":0.309,
"delay":0.000
},
{
"type":"site_delay",
"pin0":
{
"log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK",
"phy_name":"MyPLL.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/REFCK"
},
"pin1":
{
"log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP",
"phy_name":"MyPLL.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP"
},
"arrive":0.309,
"delay":0.000
},
{
"type":"net_delay",
"net":
{
"log_name":"MyPLL/lscc_pll_inst/clk1",
"phy_name":"clk1"
},
"arrive":2.808,
"delay":2.499
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":2.808,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- ---------------- ---------------- --------- --------------------- ------
Clk_pad.bb_inst/PADDI SEIO18A_CORE_K15 CLOCK LATENCY 0.000 0.000 1
MyPLL/lscc_pll_inst/REFCK NET DELAY 0.309 0.309 1
MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK->MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP
PLL_CORE_PLL_LLC 0.000 0.309 2
MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK->MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP (TOTAL_ADJUSTMENTS)
PLL_CORE_PLL_LLC 0.000 0.309 2
MyPLL/lscc_pll_inst/clk1 NET DELAY 2.499 2.808 2
A_Sig_c.ff_inst/CLK CLOCK PIN 0.000 2.808 1
Data Path
{
"path_begin":
{
"type":"pin",
"log_name":"A_Sig_c.ff_inst/Q",
"phy_name":"A_Sig_c.SLICE_1/Q0"
},
"path_end":
{
"type":"pin",
"log_name":"A_Sig1.ff_inst/DF",
"phy_name":"A_Sig1.SLICE_2/M0"
},
"path_sections":[
{
"type":"site_delay",
"pin0":
{
"log_name":"A_Sig_c.ff_inst/CLK",
"phy_name":"A_Sig_c.SLICE_1/CLK"
},
"pin1":
{
"log_name":"A_Sig_c.ff_inst/Q",
"phy_name":"A_Sig_c.SLICE_1/Q0"
},
"arrive":3.100,
"delay":0.292
},
{
"type":"net_delay",
"net":
{
"log_name":"A_Sig",
"phy_name":"A_Sig"
},
"arrive":5.536,
"delay":2.436
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":5.536,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- ---------------- ---------------- --------- --------------------- ------
A_Sig_c.ff_inst/CLK->A_Sig_c.ff_inst/Q SLICE_R4C4D REG_DEL 0.292 3.100 2
A_Sig NET DELAY 2.436 5.536 2
A_Sig1.ff_inst/DF ENDPOINT 0.000 5.536 1
Destination Clock Path
{
"path_begin":
{
"type":"pin",
"log_name":"Clk_pad.bb_inst/O",
"phy_name":"Clk_pad.bb_inst/PADDI"
},
"path_end":
{
"type":"pin",
"log_name":"A_Sig1.ff_inst/CLK",
"phy_name":"A_Sig1.SLICE_2/CLK"
},
"path_sections":[
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":10.000,
"delay":0.000
},
{
"type":"net_delay",
"net":
{
"log_name":"MyPLL/lscc_pll_inst/REFCK",
"phy_name":"Clk_c"
},
"arrive":10.290,
"delay":0.290
},
{
"type":"site_delay",
"pin0":
{
"log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK",
"phy_name":"MyPLL.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/REFCK"
},
"pin1":
{
"log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP",
"phy_name":"MyPLL.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP"
},
"arrive":10.290,
"delay":0.000
},
{
"type":"site_delay",
"pin0":
{
"log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK",
"phy_name":"MyPLL.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/REFCK"
},
"pin1":
{
"log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP",
"phy_name":"MyPLL.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP"
},
"arrive":10.290,
"delay":0.000
},
{
"type":"net_delay",
"net":
{
"log_name":"MyPLL/lscc_pll_inst/clk1",
"phy_name":"clk1"
},
"arrive":12.645,
"delay":2.355
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":12.645,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- ---------------- ---------------- --------- --------------------- ------
CONSTRAINT 0.000 10.000 1
Clk_pad.bb_inst/PADDI SEIO18A_CORE_K15 CLOCK LATENCY 0.000 10.000 1
MyPLL/lscc_pll_inst/REFCK NET DELAY 0.290 10.290 1
MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK->MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP
PLL_CORE_PLL_LLC 0.000 10.290 2
MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK->MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP (TOTAL_ADJUSTMENTS)
PLL_CORE_PLL_LLC 0.000 10.290 2
MyPLL/lscc_pll_inst/clk1 NET DELAY 2.355 12.645 2
A_Sig1.ff_inst/CLK CLOCK PIN 0.000 12.645 1
Uncertainty -(0.000) 12.645
Common Path Skew 0.057 12.702
Setup time -(-0.033) 12.735
---------------------------------------- ---------------- ---------------- --------- --------------------- ------
Required Time 12.735
Arrival Time -(5.536)
---------------------------------------- ---------------- ---------------- --------- --------------------- ------
Path Slack (Passed) 7.199
++++ Path 3 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Path Begin : B_sig_c.ff_inst/Q (SLICE_R50C100C)
Path End : B_sig1.ff_inst/DF (SLICE_R50C100D)
Source Clock : clk2 (R)
Destination Clock: clk2 (R)
Logic Level : 2
Delay Ratio : 31.5% (route), 68.5% (logic)
Clock Skew : -0.163 ns
Setup Constraint : 10.000 ns
Common Path Skew : 0.161 ns
Path Slack : 9.301 ns (Passed)
Source Clock Path
{
"path_begin":
{
"type":"pin",
"log_name":"Clk_pad.bb_inst/O",
"phy_name":"Clk_pad.bb_inst/PADDI"
},
"path_end":
{
"type":"pin",
"log_name":"B_sig_c.ff_inst/CLK",
"phy_name":"B_sig_c.SLICE_3/CLK"
},
"path_sections":[
{
"type":"net_delay",
"net":
{
"log_name":"MyPLL/lscc_pll_inst/REFCK",
"phy_name":"Clk_c"
},
"arrive":0.309,
"delay":0.309
},
{
"type":"site_delay",
"pin0":
{
"log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK",
"phy_name":"MyPLL.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/REFCK"
},
"pin1":
{
"log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS",
"phy_name":"MyPLL.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS"
},
"arrive":0.309,
"delay":0.000
},
{
"type":"site_delay",
"pin0":
{
"log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK",
"phy_name":"MyPLL.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/REFCK"
},
"pin1":
{
"log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS",
"phy_name":"MyPLL.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS"
},
"arrive":0.309,
"delay":0.000
},
{
"type":"net_delay",
"net":
{
"log_name":"MyPLL/lscc_pll_inst/clk2",
"phy_name":"clk2"
},
"arrive":2.808,
"delay":2.499
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":2.808,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- ---------------- ---------------- --------- --------------------- ------
Clk_pad.bb_inst/PADDI SEIO18A_CORE_K15 CLOCK LATENCY 0.000 0.000 1
MyPLL/lscc_pll_inst/REFCK NET DELAY 0.309 0.309 1
MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK->MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS
PLL_CORE_PLL_LLC 0.000 0.309 2
MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK->MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS (TOTAL_ADJUSTMENTS)
PLL_CORE_PLL_LLC 0.000 0.309 2
MyPLL/lscc_pll_inst/clk2 NET DELAY 2.499 2.808 2
B_sig_c.ff_inst/CLK CLOCK PIN 0.000 2.808 1
Data Path
{
"path_begin":
{
"type":"pin",
"log_name":"B_sig_c.ff_inst/Q",
"phy_name":"B_sig_c.SLICE_3/Q0"
},
"path_end":
{
"type":"pin",
"log_name":"B_sig1.ff_inst/DF",
"phy_name":"SLICE_0/DI0"
},
"path_sections":[
{
"type":"site_delay",
"pin0":
{
"log_name":"B_sig_c.ff_inst/CLK",
"phy_name":"B_sig_c.SLICE_3/CLK"
},
"pin1":
{
"log_name":"B_sig_c.ff_inst/Q",
"phy_name":"B_sig_c.SLICE_3/Q0"
},
"arrive":3.112,
"delay":0.304
},
{
"type":"net_delay",
"net":
{
"log_name":"B_sig",
"phy_name":"B_sig"
},
"arrive":3.350,
"delay":0.238
},
{
"type":"site_delay",
"pin0":
{
"log_name":"i8_2_lut/A",
"phy_name":"SLICE_0/C0"
},
"pin1":
{
"log_name":"i8_2_lut/Z",
"phy_name":"SLICE_0/F0"
},
"arrive":3.563,
"delay":0.213
},
{
"type":"net_delay",
"net":
{
"log_name":"out2_c_N_1",
"phy_name":"out2_c_N_1"
},
"arrive":3.563,
"delay":0.000
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":3.563,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- ---------------- ---------------- --------- --------------------- ------
B_sig_c.ff_inst/CLK->B_sig_c.ff_inst/Q SLICE_R50C100C REG_DEL 0.304 3.112 1
B_sig NET DELAY 0.238 3.350 1
i8_2_lut/A->i8_2_lut/Z SLICE_R50C100D CTOF_DEL 0.213 3.563 1
out2_c_N_1 NET DELAY 0.000 3.563 1
B_sig1.ff_inst/DF ENDPOINT 0.000 3.563 1
Destination Clock Path
{
"path_begin":
{
"type":"pin",
"log_name":"Clk_pad.bb_inst/O",
"phy_name":"Clk_pad.bb_inst/PADDI"
},
"path_end":
{
"type":"pin",
"log_name":"B_sig1.ff_inst/CLK",
"phy_name":"SLICE_0/CLK"
},
"path_sections":[
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":10.000,
"delay":0.000
},
{
"type":"net_delay",
"net":
{
"log_name":"MyPLL/lscc_pll_inst/REFCK",
"phy_name":"Clk_c"
},
"arrive":10.290,
"delay":0.290
},
{
"type":"site_delay",
"pin0":
{
"log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK",
"phy_name":"MyPLL.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/REFCK"
},
"pin1":
{
"log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS",
"phy_name":"MyPLL.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS"
},
"arrive":10.290,
"delay":0.000
},
{
"type":"site_delay",
"pin0":
{
"log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK",
"phy_name":"MyPLL.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/REFCK"
},
"pin1":
{
"log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS",
"phy_name":"MyPLL.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS"
},
"arrive":10.290,
"delay":0.000
},
{
"type":"net_delay",
"net":
{
"log_name":"MyPLL/lscc_pll_inst/clk2",
"phy_name":"clk2"
},
"arrive":12.645,
"delay":2.355
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":12.645,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- ---------------- ---------------- --------- --------------------- ------
CONSTRAINT 0.000 10.000 1
Clk_pad.bb_inst/PADDI SEIO18A_CORE_K15 CLOCK LATENCY 0.000 10.000 1
MyPLL/lscc_pll_inst/REFCK NET DELAY 0.290 10.290 1
MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK->MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS
PLL_CORE_PLL_LLC 0.000 10.290 2
MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK->MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS (TOTAL_ADJUSTMENTS)
PLL_CORE_PLL_LLC 0.000 10.290 2
MyPLL/lscc_pll_inst/clk2 NET DELAY 2.355 12.645 2
B_sig1.ff_inst/CLK CLOCK PIN 0.000 12.645 1
Uncertainty -(0.000) 12.645
Common Path Skew 0.161 12.806
Setup time -(-0.058) 12.864
---------------------------------------- ---------------- ---------------- --------- --------------------- ------
Required Time 12.864
Arrival Time -(3.563)
---------------------------------------- ---------------- ---------------- --------- --------------------- ------
Path Slack (Passed) 9.301
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
End of Detailed Report for timing paths
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
##########################################################
3 Setup at Speed Grade 9_High-Performance_1.0V Corner at 0 Degrees
3.1 Clock Summary
3.1.1 Clock "clk1"
create_generated_clock -name {clk1} -source [get_pins {MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK}] -multiply_by 2 [get_pins {MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP }]
Single Clock Domain
-------------------------------------------------------------------------------------------------------
Clock clk1 | | Period | Frequency
-------------------------------------------------------------------------------------------------------
From clk1 | Target | 10.000 ns | 100.000 MHz
| Actual (all paths) | 2.816 ns | 355.114 MHz
A_Sig_c.ff_inst/CLK (MPW) | (50% duty cycle) | 2.000 ns | 500.000 MHz
-------------------------------------------------------------------------------------------------------
Clock Domain Crossing
------------------------------------------------------------------------------------------------------
Clock clk1 | Worst Time Between Edges | Comment
------------------------------------------------------------------------------------------------------
From clk2 | ---- | No path
From Clk | ---- | No path
------------------------------------------------------------------------------------------------------
3.1.2 Clock "clk2"
create_generated_clock -name {clk2} -source [get_pins {MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK}] -multiply_by 2 [get_pins {MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS }]
Single Clock Domain
-------------------------------------------------------------------------------------------------------
Clock clk2 | | Period | Frequency
-------------------------------------------------------------------------------------------------------
From clk2 | Target | 10.000 ns | 100.000 MHz
| Actual (all paths) | 2.000 ns | 500.000 MHz
B_sig1.ff_inst/CLK (MPW) | (50% duty cycle) | 2.000 ns | 500.000 MHz
-------------------------------------------------------------------------------------------------------
Clock Domain Crossing
------------------------------------------------------------------------------------------------------
Clock clk2 | Worst Time Between Edges | Comment
------------------------------------------------------------------------------------------------------
From clk1 | 2.500 ns | slack = -1.750 ns
From Clk | ---- | No path
------------------------------------------------------------------------------------------------------
3.1.3 Clock "Clk"
create_clock -name {Clk} -period 20 [get_nets Clk_c]
Single Clock Domain
-------------------------------------------------------------------------------------------------------
Clock Clk | | Period | Frequency
-------------------------------------------------------------------------------------------------------
From Clk | Target | 20.000 ns | 50.000 MHz
| Actual (all paths) | ---- | ----
-------------------------------------------------------------------------------------------------------
Clock Domain Crossing
------------------------------------------------------------------------------------------------------
Clock Clk | Worst Time Between Edges | Comment
------------------------------------------------------------------------------------------------------
From clk1 | ---- | No path
From clk2 | ---- | No path
------------------------------------------------------------------------------------------------------
3.2 Endpoint slacks
-------------------------------------------------------
Listing 2 End Points | Slack
-------------------------------------------------------
B_sig1.ff_inst/DF | -1.750 ns
A_Sig1.ff_inst/DF | 7.184 ns
-------------------------------------------------------
|
Setup # of endpoints with negative slack:| 1
|
-------------------------------------------------------
3.3 Detailed Report
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
Detail report of critical paths
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Detailed Report for timing paths
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++++Path 1 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Path Begin : A_Sig_c.ff_inst/Q (SLICE_R4C4D)
Path End : B_sig1.ff_inst/DF (SLICE_R50C100D)
Source Clock : clk1 (R)
Destination Clock: clk2 (R)
Logic Level : 2
Delay Ratio : 87.8% (route), 12.2% (logic)
Clock Skew : -0.175 ns
Setup Constraint : 2.500 ns
Common Path Skew : 0.019 ns
Path Slack : -1.750 ns (Failed)
Source Clock Path
{
"path_begin":
{
"type":"pin",
"log_name":"Clk_pad.bb_inst/O",
"phy_name":"Clk_pad.bb_inst/PADDI"
},
"path_end":
{
"type":"pin",
"log_name":"A_Sig_c.ff_inst/CLK",
"phy_name":"A_Sig_c.SLICE_1/CLK"
},
"path_sections":[
{
"type":"net_delay",
"net":
{
"log_name":"MyPLL/lscc_pll_inst/REFCK",
"phy_name":"Clk_c"
},
"arrive":0.326,
"delay":0.326
},
{
"type":"site_delay",
"pin0":
{
"log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK",
"phy_name":"MyPLL.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/REFCK"
},
"pin1":
{
"log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP",
"phy_name":"MyPLL.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP"
},
"arrive":0.326,
"delay":0.000
},
{
"type":"site_delay",
"pin0":
{
"log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK",
"phy_name":"MyPLL.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/REFCK"
},
"pin1":
{
"log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP",
"phy_name":"MyPLL.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP"
},
"arrive":0.326,
"delay":0.000
},
{
"type":"net_delay",
"net":
{
"log_name":"MyPLL/lscc_pll_inst/clk1",
"phy_name":"clk1"
},
"arrive":3.012,
"delay":2.686
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":3.012,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- ---------------- ---------------- --------- --------------------- ------
Clk_pad.bb_inst/PADDI SEIO18A_CORE_K15 CLOCK LATENCY 0.000 0.000 1
MyPLL/lscc_pll_inst/REFCK NET DELAY 0.326 0.326 1
MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK->MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP
PLL_CORE_PLL_LLC 0.000 0.326 2
MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK->MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP (TOTAL_ADJUSTMENTS)
PLL_CORE_PLL_LLC 0.000 0.326 2
MyPLL/lscc_pll_inst/clk1 NET DELAY 2.686 3.012 2
A_Sig_c.ff_inst/CLK CLOCK PIN 0.000 3.012 1
Data Path
{
"path_begin":
{
"type":"pin",
"log_name":"A_Sig_c.ff_inst/Q",
"phy_name":"A_Sig_c.SLICE_1/Q0"
},
"path_end":
{
"type":"pin",
"log_name":"B_sig1.ff_inst/DF",
"phy_name":"SLICE_0/DI0"
},
"path_sections":[
{
"type":"site_delay",
"pin0":
{
"log_name":"A_Sig_c.ff_inst/CLK",
"phy_name":"A_Sig_c.SLICE_1/CLK"
},
"pin1":
{
"log_name":"A_Sig_c.ff_inst/Q",
"phy_name":"A_Sig_c.SLICE_1/Q0"
},
"arrive":3.305,
"delay":0.293
},
{
"type":"net_delay",
"net":
{
"log_name":"A_Sig",
"phy_name":"A_Sig"
},
"arrive":6.951,
"delay":3.646
},
{
"type":"site_delay",
"pin0":
{
"log_name":"i8_2_lut/B",
"phy_name":"SLICE_0/D0"
},
"pin1":
{
"log_name":"i8_2_lut/Z",
"phy_name":"SLICE_0/F0"
},
"arrive":7.164,
"delay":0.213
},
{
"type":"net_delay",
"net":
{
"log_name":"out2_c_N_1",
"phy_name":"out2_c_N_1"
},
"arrive":7.164,
"delay":0.000
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":7.164,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- ---------------- ---------------- --------- --------------------- ------
A_Sig_c.ff_inst/CLK->A_Sig_c.ff_inst/Q SLICE_R4C4D REG_DEL 0.293 3.305 2
A_Sig NET DELAY 3.646 6.951 2
i8_2_lut/B->i8_2_lut/Z SLICE_R50C100D CTOF_DEL 0.213 7.164 1
out2_c_N_1 NET DELAY 0.000 7.164 1
B_sig1.ff_inst/DF ENDPOINT 0.000 7.164 1
Destination Clock Path
{
"path_begin":
{
"type":"pin",
"log_name":"Clk_pad.bb_inst/O",
"phy_name":"Clk_pad.bb_inst/PADDI"
},
"path_end":
{
"type":"pin",
"log_name":"B_sig1.ff_inst/CLK",
"phy_name":"SLICE_0/CLK"
},
"path_sections":[
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":2.500,
"delay":0.000
},
{
"type":"net_delay",
"net":
{
"log_name":"MyPLL/lscc_pll_inst/REFCK",
"phy_name":"Clk_c"
},
"arrive":2.806,
"delay":0.306
},
{
"type":"site_delay",
"pin0":
{
"log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK",
"phy_name":"MyPLL.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/REFCK"
},
"pin1":
{
"log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS",
"phy_name":"MyPLL.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS"
},
"arrive":2.806,
"delay":0.000
},
{
"type":"site_delay",
"pin0":
{
"log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK",
"phy_name":"MyPLL.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/REFCK"
},
"pin1":
{
"log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS",
"phy_name":"MyPLL.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS"
},
"arrive":2.806,
"delay":0.000
},
{
"type":"net_delay",
"net":
{
"log_name":"MyPLL/lscc_pll_inst/clk2",
"phy_name":"clk2"
},
"arrive":5.337,
"delay":2.531
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":5.337,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- ---------------- ---------------- --------- --------------------- ------
CONSTRAINT 0.000 2.500 1
Clk_pad.bb_inst/PADDI SEIO18A_CORE_K15 CLOCK LATENCY 0.000 2.500 1
MyPLL/lscc_pll_inst/REFCK NET DELAY 0.306 2.806 1
MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK->MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS
PLL_CORE_PLL_LLC 0.000 2.806 2
MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK->MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS (TOTAL_ADJUSTMENTS)
PLL_CORE_PLL_LLC 0.000 2.806 2
MyPLL/lscc_pll_inst/clk2 NET DELAY 2.531 5.337 2
B_sig1.ff_inst/CLK CLOCK PIN 0.000 5.337 1
Uncertainty -(0.000) 5.337
Common Path Skew 0.019 5.356
Setup time -(-0.058) 5.414
---------------------------------------- ---------------- ---------------- --------- --------------------- ------
Required Time 5.414
Arrival Time -(7.164)
---------------------------------------- ---------------- ---------------- --------- --------------------- ------
Path Slack (Failed) -1.750
++++ Path 2 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Path Begin : A_Sig_c.ff_inst/Q (SLICE_R4C4D)
Path End : A_Sig1.ff_inst/DF (SLICE_R2C100D)
Source Clock : clk1 (R)
Destination Clock: clk1 (R)
Logic Level : 1
Delay Ratio : 89.3% (route), 10.7% (logic)
Clock Skew : -0.175 ns
Setup Constraint : 10.000 ns
Common Path Skew : 0.062 ns
Path Slack : 7.184 ns (Passed)
Source Clock Path
{
"path_begin":
{
"type":"pin",
"log_name":"Clk_pad.bb_inst/O",
"phy_name":"Clk_pad.bb_inst/PADDI"
},
"path_end":
{
"type":"pin",
"log_name":"A_Sig_c.ff_inst/CLK",
"phy_name":"A_Sig_c.SLICE_1/CLK"
},
"path_sections":[
{
"type":"net_delay",
"net":
{
"log_name":"MyPLL/lscc_pll_inst/REFCK",
"phy_name":"Clk_c"
},
"arrive":0.326,
"delay":0.326
},
{
"type":"site_delay",
"pin0":
{
"log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK",
"phy_name":"MyPLL.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/REFCK"
},
"pin1":
{
"log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP",
"phy_name":"MyPLL.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP"
},
"arrive":0.326,
"delay":0.000
},
{
"type":"site_delay",
"pin0":
{
"log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK",
"phy_name":"MyPLL.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/REFCK"
},
"pin1":
{
"log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP",
"phy_name":"MyPLL.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP"
},
"arrive":0.326,
"delay":0.000
},
{
"type":"net_delay",
"net":
{
"log_name":"MyPLL/lscc_pll_inst/clk1",
"phy_name":"clk1"
},
"arrive":3.012,
"delay":2.686
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":3.012,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- ---------------- ---------------- --------- --------------------- ------
Clk_pad.bb_inst/PADDI SEIO18A_CORE_K15 CLOCK LATENCY 0.000 0.000 1
MyPLL/lscc_pll_inst/REFCK NET DELAY 0.326 0.326 1
MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK->MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP
PLL_CORE_PLL_LLC 0.000 0.326 2
MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK->MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP (TOTAL_ADJUSTMENTS)
PLL_CORE_PLL_LLC 0.000 0.326 2
MyPLL/lscc_pll_inst/clk1 NET DELAY 2.686 3.012 2
A_Sig_c.ff_inst/CLK CLOCK PIN 0.000 3.012 1
Data Path
{
"path_begin":
{
"type":"pin",
"log_name":"A_Sig_c.ff_inst/Q",
"phy_name":"A_Sig_c.SLICE_1/Q0"
},
"path_end":
{
"type":"pin",
"log_name":"A_Sig1.ff_inst/DF",
"phy_name":"A_Sig1.SLICE_2/M0"
},
"path_sections":[
{
"type":"site_delay",
"pin0":
{
"log_name":"A_Sig_c.ff_inst/CLK",
"phy_name":"A_Sig_c.SLICE_1/CLK"
},
"pin1":
{
"log_name":"A_Sig_c.ff_inst/Q",
"phy_name":"A_Sig_c.SLICE_1/Q0"
},
"arrive":3.305,
"delay":0.293
},
{
"type":"net_delay",
"net":
{
"log_name":"A_Sig",
"phy_name":"A_Sig"
},
"arrive":5.748,
"delay":2.443
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":5.748,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- ---------------- ---------------- --------- --------------------- ------
A_Sig_c.ff_inst/CLK->A_Sig_c.ff_inst/Q SLICE_R4C4D REG_DEL 0.293 3.305 2
A_Sig NET DELAY 2.443 5.748 2
A_Sig1.ff_inst/DF ENDPOINT 0.000 5.748 1
Destination Clock Path
{
"path_begin":
{
"type":"pin",
"log_name":"Clk_pad.bb_inst/O",
"phy_name":"Clk_pad.bb_inst/PADDI"
},
"path_end":
{
"type":"pin",
"log_name":"A_Sig1.ff_inst/CLK",
"phy_name":"A_Sig1.SLICE_2/CLK"
},
"path_sections":[
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":10.000,
"delay":0.000
},
{
"type":"net_delay",
"net":
{
"log_name":"MyPLL/lscc_pll_inst/REFCK",
"phy_name":"Clk_c"
},
"arrive":10.306,
"delay":0.306
},
{
"type":"site_delay",
"pin0":
{
"log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK",
"phy_name":"MyPLL.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/REFCK"
},
"pin1":
{
"log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP",
"phy_name":"MyPLL.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP"
},
"arrive":10.306,
"delay":0.000
},
{
"type":"site_delay",
"pin0":
{
"log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK",
"phy_name":"MyPLL.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/REFCK"
},
"pin1":
{
"log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP",
"phy_name":"MyPLL.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP"
},
"arrive":10.306,
"delay":0.000
},
{
"type":"net_delay",
"net":
{
"log_name":"MyPLL/lscc_pll_inst/clk1",
"phy_name":"clk1"
},
"arrive":12.837,
"delay":2.531
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":12.837,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- ---------------- ---------------- --------- --------------------- ------
CONSTRAINT 0.000 10.000 1
Clk_pad.bb_inst/PADDI SEIO18A_CORE_K15 CLOCK LATENCY 0.000 10.000 1
MyPLL/lscc_pll_inst/REFCK NET DELAY 0.306 10.306 1
MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK->MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP
PLL_CORE_PLL_LLC 0.000 10.306 2
MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK->MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP (TOTAL_ADJUSTMENTS)
PLL_CORE_PLL_LLC 0.000 10.306 2
MyPLL/lscc_pll_inst/clk1 NET DELAY 2.531 12.837 2
A_Sig1.ff_inst/CLK CLOCK PIN 0.000 12.837 1
Uncertainty -(0.000) 12.837
Common Path Skew 0.062 12.899
Setup time -(-0.033) 12.932
---------------------------------------- ---------------- ---------------- --------- --------------------- ------
Required Time 12.932
Arrival Time -(5.748)
---------------------------------------- ---------------- ---------------- --------- --------------------- ------
Path Slack (Passed) 7.184
++++ Path 3 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Path Begin : B_sig_c.ff_inst/Q (SLICE_R50C100C)
Path End : B_sig1.ff_inst/DF (SLICE_R50C100D)
Source Clock : clk2 (R)
Destination Clock: clk2 (R)
Logic Level : 2
Delay Ratio : 30.6% (route), 69.4% (logic)
Clock Skew : -0.175 ns
Setup Constraint : 10.000 ns
Common Path Skew : 0.173 ns
Path Slack : 9.310 ns (Passed)
Source Clock Path
{
"path_begin":
{
"type":"pin",
"log_name":"Clk_pad.bb_inst/O",
"phy_name":"Clk_pad.bb_inst/PADDI"
},
"path_end":
{
"type":"pin",
"log_name":"B_sig_c.ff_inst/CLK",
"phy_name":"B_sig_c.SLICE_3/CLK"
},
"path_sections":[
{
"type":"net_delay",
"net":
{
"log_name":"MyPLL/lscc_pll_inst/REFCK",
"phy_name":"Clk_c"
},
"arrive":0.326,
"delay":0.326
},
{
"type":"site_delay",
"pin0":
{
"log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK",
"phy_name":"MyPLL.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/REFCK"
},
"pin1":
{
"log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS",
"phy_name":"MyPLL.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS"
},
"arrive":0.326,
"delay":0.000
},
{
"type":"site_delay",
"pin0":
{
"log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK",
"phy_name":"MyPLL.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/REFCK"
},
"pin1":
{
"log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS",
"phy_name":"MyPLL.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS"
},
"arrive":0.326,
"delay":0.000
},
{
"type":"net_delay",
"net":
{
"log_name":"MyPLL/lscc_pll_inst/clk2",
"phy_name":"clk2"
},
"arrive":3.012,
"delay":2.686
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":3.012,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- ---------------- ---------------- --------- --------------------- ------
Clk_pad.bb_inst/PADDI SEIO18A_CORE_K15 CLOCK LATENCY 0.000 0.000 1
MyPLL/lscc_pll_inst/REFCK NET DELAY 0.326 0.326 1
MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK->MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS
PLL_CORE_PLL_LLC 0.000 0.326 2
MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK->MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS (TOTAL_ADJUSTMENTS)
PLL_CORE_PLL_LLC 0.000 0.326 2
MyPLL/lscc_pll_inst/clk2 NET DELAY 2.686 3.012 2
B_sig_c.ff_inst/CLK CLOCK PIN 0.000 3.012 1
Data Path
{
"path_begin":
{
"type":"pin",
"log_name":"B_sig_c.ff_inst/Q",
"phy_name":"B_sig_c.SLICE_3/Q0"
},
"path_end":
{
"type":"pin",
"log_name":"B_sig1.ff_inst/DF",
"phy_name":"SLICE_0/DI0"
},
"path_sections":[
{
"type":"site_delay",
"pin0":
{
"log_name":"B_sig_c.ff_inst/CLK",
"phy_name":"B_sig_c.SLICE_3/CLK"
},
"pin1":
{
"log_name":"B_sig_c.ff_inst/Q",
"phy_name":"B_sig_c.SLICE_3/Q0"
},
"arrive":3.317,
"delay":0.305
},
{
"type":"net_delay",
"net":
{
"log_name":"B_sig",
"phy_name":"B_sig"
},
"arrive":3.545,
"delay":0.228
},
{
"type":"site_delay",
"pin0":
{
"log_name":"i8_2_lut/A",
"phy_name":"SLICE_0/C0"
},
"pin1":
{
"log_name":"i8_2_lut/Z",
"phy_name":"SLICE_0/F0"
},
"arrive":3.758,
"delay":0.213
},
{
"type":"net_delay",
"net":
{
"log_name":"out2_c_N_1",
"phy_name":"out2_c_N_1"
},
"arrive":3.758,
"delay":0.000
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":3.758,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- ---------------- ---------------- --------- --------------------- ------
B_sig_c.ff_inst/CLK->B_sig_c.ff_inst/Q SLICE_R50C100C REG_DEL 0.305 3.317 1
B_sig NET DELAY 0.228 3.545 1
i8_2_lut/A->i8_2_lut/Z SLICE_R50C100D CTOF_DEL 0.213 3.758 1
out2_c_N_1 NET DELAY 0.000 3.758 1
B_sig1.ff_inst/DF ENDPOINT 0.000 3.758 1
Destination Clock Path
{
"path_begin":
{
"type":"pin",
"log_name":"Clk_pad.bb_inst/O",
"phy_name":"Clk_pad.bb_inst/PADDI"
},
"path_end":
{
"type":"pin",
"log_name":"B_sig1.ff_inst/CLK",
"phy_name":"SLICE_0/CLK"
},
"path_sections":[
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":10.000,
"delay":0.000
},
{
"type":"net_delay",
"net":
{
"log_name":"MyPLL/lscc_pll_inst/REFCK",
"phy_name":"Clk_c"
},
"arrive":10.306,
"delay":0.306
},
{
"type":"site_delay",
"pin0":
{
"log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK",
"phy_name":"MyPLL.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/REFCK"
},
"pin1":
{
"log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS",
"phy_name":"MyPLL.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS"
},
"arrive":10.306,
"delay":0.000
},
{
"type":"site_delay",
"pin0":
{
"log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK",
"phy_name":"MyPLL.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/REFCK"
},
"pin1":
{
"log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS",
"phy_name":"MyPLL.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS"
},
"arrive":10.306,
"delay":0.000
},
{
"type":"net_delay",
"net":
{
"log_name":"MyPLL/lscc_pll_inst/clk2",
"phy_name":"clk2"
},
"arrive":12.837,
"delay":2.531
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":12.837,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- ---------------- ---------------- --------- --------------------- ------
CONSTRAINT 0.000 10.000 1
Clk_pad.bb_inst/PADDI SEIO18A_CORE_K15 CLOCK LATENCY 0.000 10.000 1
MyPLL/lscc_pll_inst/REFCK NET DELAY 0.306 10.306 1
MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK->MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS
PLL_CORE_PLL_LLC 0.000 10.306 2
MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK->MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS (TOTAL_ADJUSTMENTS)
PLL_CORE_PLL_LLC 0.000 10.306 2
MyPLL/lscc_pll_inst/clk2 NET DELAY 2.531 12.837 2
B_sig1.ff_inst/CLK CLOCK PIN 0.000 12.837 1
Uncertainty -(0.000) 12.837
Common Path Skew 0.173 13.010
Setup time -(-0.058) 13.068
---------------------------------------- ---------------- ---------------- --------- --------------------- ------
Required Time 13.068
Arrival Time -(3.758)
---------------------------------------- ---------------- ---------------- --------- --------------------- ------
Path Slack (Passed) 9.310
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
End of Detailed Report for timing paths
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
##########################################################
4 Hold at Speed Grade m Corner at 0 Degrees
4.1 Endpoint slacks
-------------------------------------------------------
Listing 2 End Points | Slack
-------------------------------------------------------
B_sig1.ff_inst/DF | 0.286 ns
A_Sig1.ff_inst/DF | 1.426 ns
-------------------------------------------------------
|
Hold # of endpoints with negative slack: | 0
|
-------------------------------------------------------
4.2 Detailed Report
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
Detail report of critical paths
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Detailed Report for timing paths
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++++Path 1 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Path Begin : B_sig_c.ff_inst/Q (SLICE_R50C100C)
Path End : B_sig1.ff_inst/DF (SLICE_R50C100D)
Source Clock : clk2 (R)
Destination Clock: clk2 (R)
Logic Level : 2
Delay Ratio : 27.9% (route), 72.1% (logic)
Clock Skew : 0.136 ns
Hold Constraint : 0.000 ns
Common Path Skew : -0.135 ns
Path Slack : 0.286 ns (Passed)
Source Clock Path
{
"path_begin":
{
"type":"pin",
"log_name":"Clk_pad.bb_inst/O",
"phy_name":"Clk_pad.bb_inst/PADDI"
},
"path_end":
{
"type":"pin",
"log_name":"B_sig_c.ff_inst/CLK",
"phy_name":"B_sig_c.SLICE_3/CLK"
},
"path_sections":[
{
"type":"net_delay",
"net":
{
"log_name":"MyPLL/lscc_pll_inst/REFCK",
"phy_name":"Clk_c"
},
"arrive":0.240,
"delay":0.240
},
{
"type":"site_delay",
"pin0":
{
"log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK",
"phy_name":"MyPLL.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/REFCK"
},
"pin1":
{
"log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS",
"phy_name":"MyPLL.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS"
},
"arrive":0.240,
"delay":0.000
},
{
"type":"site_delay",
"pin0":
{
"log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK",
"phy_name":"MyPLL.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/REFCK"
},
"pin1":
{
"log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS",
"phy_name":"MyPLL.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS"
},
"arrive":0.240,
"delay":0.000
},
{
"type":"net_delay",
"net":
{
"log_name":"MyPLL/lscc_pll_inst/clk2",
"phy_name":"clk2"
},
"arrive":2.117,
"delay":1.877
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":2.117,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- ---------------- ---------------- ------ --------------------- ------
Clk_pad.bb_inst/PADDI SEIO18A_CORE_K15 CLOCK LATENCY 0.000 0.000 1
MyPLL/lscc_pll_inst/REFCK NET DELAY 0.240 0.240 1
MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK->MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS
PLL_CORE_PLL_LLC 0.000 0.240 2
MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK->MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS (TOTAL_ADJUSTMENTS)
PLL_CORE_PLL_LLC 0.000 0.240 2
MyPLL/lscc_pll_inst/clk2 NET DELAY 1.877 2.117 2
B_sig_c.ff_inst/CLK CLOCK PIN 0.000 2.117 1
Data Path
{
"path_begin":
{
"type":"pin",
"log_name":"B_sig_c.ff_inst/Q",
"phy_name":"B_sig_c.SLICE_3/Q0"
},
"path_end":
{
"type":"pin",
"log_name":"B_sig1.ff_inst/DF",
"phy_name":"SLICE_0/DI0"
},
"path_sections":[
{
"type":"site_delay",
"pin0":
{
"log_name":"B_sig_c.ff_inst/CLK",
"phy_name":"B_sig_c.SLICE_3/CLK"
},
"pin1":
{
"log_name":"B_sig_c.ff_inst/Q",
"phy_name":"B_sig_c.SLICE_3/Q0"
},
"arrive":2.290,
"delay":0.173
},
{
"type":"net_delay",
"net":
{
"log_name":"B_sig",
"phy_name":"B_sig"
},
"arrive":2.402,
"delay":0.112
},
{
"type":"site_delay",
"pin0":
{
"log_name":"i8_2_lut/A",
"phy_name":"SLICE_0/C0"
},
"pin1":
{
"log_name":"i8_2_lut/Z",
"phy_name":"SLICE_0/F0"
},
"arrive":2.518,
"delay":0.116
},
{
"type":"net_delay",
"net":
{
"log_name":"out2_c_N_1",
"phy_name":"out2_c_N_1"
},
"arrive":2.518,
"delay":0.000
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":2.518,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- ---------------- ---------------- ------ --------------------- ------
B_sig_c.ff_inst/CLK->B_sig_c.ff_inst/Q SLICE_R50C100C REG_DEL 0.173 2.290 1
B_sig NET DELAY 0.112 2.402 1
i8_2_lut/A->i8_2_lut/Z SLICE_R50C100D CTOF_DEL 0.116 2.518 1
out2_c_N_1 NET DELAY 0.000 2.518 1
B_sig1.ff_inst/DF ENDPOINT 0.000 2.518 1
Destination Clock Path
{
"path_begin":
{
"type":"pin",
"log_name":"Clk_pad.bb_inst/O",
"phy_name":"Clk_pad.bb_inst/PADDI"
},
"path_end":
{
"type":"pin",
"log_name":"B_sig1.ff_inst/CLK",
"phy_name":"SLICE_0/CLK"
},
"path_sections":[
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":0.000,
"delay":0.000
},
{
"type":"net_delay",
"net":
{
"log_name":"MyPLL/lscc_pll_inst/REFCK",
"phy_name":"Clk_c"
},
"arrive":0.257,
"delay":0.257
},
{
"type":"site_delay",
"pin0":
{
"log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK",
"phy_name":"MyPLL.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/REFCK"
},
"pin1":
{
"log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS",
"phy_name":"MyPLL.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS"
},
"arrive":0.257,
"delay":0.000
},
{
"type":"site_delay",
"pin0":
{
"log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK",
"phy_name":"MyPLL.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/REFCK"
},
"pin1":
{
"log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS",
"phy_name":"MyPLL.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS"
},
"arrive":0.257,
"delay":0.000
},
{
"type":"net_delay",
"net":
{
"log_name":"MyPLL/lscc_pll_inst/clk2",
"phy_name":"clk2"
},
"arrive":2.253,
"delay":1.996
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":2.253,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- ---------------- ---------------- ------ --------------------- ------
CONSTRAINT 0.000 0.000 1
Clk_pad.bb_inst/PADDI SEIO18A_CORE_K15 CLOCK LATENCY 0.000 0.000 1
MyPLL/lscc_pll_inst/REFCK NET DELAY 0.257 0.257 1
MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK->MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS
PLL_CORE_PLL_LLC 0.000 0.257 2
MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK->MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS (TOTAL_ADJUSTMENTS)
PLL_CORE_PLL_LLC 0.000 0.257 2
MyPLL/lscc_pll_inst/clk2 NET DELAY 1.996 2.253 2
B_sig1.ff_inst/CLK CLOCK PIN 0.000 2.253 1
Uncertainty 0.000 2.253
Common Path Skew -0.135 2.118
Hold time 0.114 2.232
---------------------------------------- ---------------- ---------------- ------ --------------------- ------
Required Time -2.232
Arrival Time 2.518
---------------------------------------- ---------------- ---------------- ------ --------------------- ------
Path Slack (Passed) 0.286
++++ Path 2 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Path Begin : A_Sig_c.ff_inst/Q (SLICE_R4C4D)
Path End : A_Sig1.ff_inst/DF (SLICE_R2C100D)
Source Clock : clk1 (R)
Destination Clock: clk1 (R)
Logic Level : 1
Delay Ratio : 88.8% (route), 11.2% (logic)
Clock Skew : 0.136 ns
Hold Constraint : 0.000 ns
Common Path Skew : -0.066 ns
Path Slack : 1.426 ns (Passed)
Source Clock Path
{
"path_begin":
{
"type":"pin",
"log_name":"Clk_pad.bb_inst/O",
"phy_name":"Clk_pad.bb_inst/PADDI"
},
"path_end":
{
"type":"pin",
"log_name":"A_Sig_c.ff_inst/CLK",
"phy_name":"A_Sig_c.SLICE_1/CLK"
},
"path_sections":[
{
"type":"net_delay",
"net":
{
"log_name":"MyPLL/lscc_pll_inst/REFCK",
"phy_name":"Clk_c"
},
"arrive":0.240,
"delay":0.240
},
{
"type":"site_delay",
"pin0":
{
"log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK",
"phy_name":"MyPLL.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/REFCK"
},
"pin1":
{
"log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP",
"phy_name":"MyPLL.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP"
},
"arrive":0.240,
"delay":0.000
},
{
"type":"site_delay",
"pin0":
{
"log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK",
"phy_name":"MyPLL.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/REFCK"
},
"pin1":
{
"log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP",
"phy_name":"MyPLL.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP"
},
"arrive":0.240,
"delay":0.000
},
{
"type":"net_delay",
"net":
{
"log_name":"MyPLL/lscc_pll_inst/clk1",
"phy_name":"clk1"
},
"arrive":2.117,
"delay":1.877
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":2.117,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- ---------------- ---------------- ------ --------------------- ------
Clk_pad.bb_inst/PADDI SEIO18A_CORE_K15 CLOCK LATENCY 0.000 0.000 1
MyPLL/lscc_pll_inst/REFCK NET DELAY 0.240 0.240 1
MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK->MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP
PLL_CORE_PLL_LLC 0.000 0.240 2
MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK->MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP (TOTAL_ADJUSTMENTS)
PLL_CORE_PLL_LLC 0.000 0.240 2
MyPLL/lscc_pll_inst/clk1 NET DELAY 1.877 2.117 2
A_Sig_c.ff_inst/CLK CLOCK PIN 0.000 2.117 1
Data Path
{
"path_begin":
{
"type":"pin",
"log_name":"A_Sig_c.ff_inst/Q",
"phy_name":"A_Sig_c.SLICE_1/Q0"
},
"path_end":
{
"type":"pin",
"log_name":"A_Sig1.ff_inst/DF",
"phy_name":"A_Sig1.SLICE_2/M0"
},
"path_sections":[
{
"type":"site_delay",
"pin0":
{
"log_name":"A_Sig_c.ff_inst/CLK",
"phy_name":"A_Sig_c.SLICE_1/CLK"
},
"pin1":
{
"log_name":"A_Sig_c.ff_inst/Q",
"phy_name":"A_Sig_c.SLICE_1/Q0"
},
"arrive":2.295,
"delay":0.178
},
{
"type":"net_delay",
"net":
{
"log_name":"A_Sig",
"phy_name":"A_Sig"
},
"arrive":3.707,
"delay":1.412
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":3.707,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- ---------------- ---------------- ------ --------------------- ------
A_Sig_c.ff_inst/CLK->A_Sig_c.ff_inst/Q SLICE_R4C4D REG_DEL 0.178 2.295 2
A_Sig NET DELAY 1.412 3.707 2
A_Sig1.ff_inst/DF ENDPOINT 0.000 3.707 1
Destination Clock Path
{
"path_begin":
{
"type":"pin",
"log_name":"Clk_pad.bb_inst/O",
"phy_name":"Clk_pad.bb_inst/PADDI"
},
"path_end":
{
"type":"pin",
"log_name":"A_Sig1.ff_inst/CLK",
"phy_name":"A_Sig1.SLICE_2/CLK"
},
"path_sections":[
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":0.000,
"delay":0.000
},
{
"type":"net_delay",
"net":
{
"log_name":"MyPLL/lscc_pll_inst/REFCK",
"phy_name":"Clk_c"
},
"arrive":0.257,
"delay":0.257
},
{
"type":"site_delay",
"pin0":
{
"log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK",
"phy_name":"MyPLL.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/REFCK"
},
"pin1":
{
"log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP",
"phy_name":"MyPLL.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP"
},
"arrive":0.257,
"delay":0.000
},
{
"type":"site_delay",
"pin0":
{
"log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK",
"phy_name":"MyPLL.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/REFCK"
},
"pin1":
{
"log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP",
"phy_name":"MyPLL.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP"
},
"arrive":0.257,
"delay":0.000
},
{
"type":"net_delay",
"net":
{
"log_name":"MyPLL/lscc_pll_inst/clk1",
"phy_name":"clk1"
},
"arrive":2.253,
"delay":1.996
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":2.253,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- ---------------- ---------------- ------ --------------------- ------
CONSTRAINT 0.000 0.000 1
Clk_pad.bb_inst/PADDI SEIO18A_CORE_K15 CLOCK LATENCY 0.000 0.000 1
MyPLL/lscc_pll_inst/REFCK NET DELAY 0.257 0.257 1
MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK->MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP
PLL_CORE_PLL_LLC 0.000 0.257 2
MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK->MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP (TOTAL_ADJUSTMENTS)
PLL_CORE_PLL_LLC 0.000 0.257 2
MyPLL/lscc_pll_inst/clk1 NET DELAY 1.996 2.253 2
A_Sig1.ff_inst/CLK CLOCK PIN 0.000 2.253 1
Uncertainty 0.000 2.253
Common Path Skew -0.066 2.187
Hold time 0.094 2.281
---------------------------------------- ---------------- ---------------- ------ --------------------- ------
Required Time -2.281
Arrival Time 3.707
---------------------------------------- ---------------- ---------------- ------ --------------------- ------
Path Slack (Passed) 1.426
++++ Path 3 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Path Begin : A_Sig_c.ff_inst/Q (SLICE_R4C4D)
Path End : B_sig1.ff_inst/DF (SLICE_R50C100D)
Source Clock : clk1 (R)
Destination Clock: clk2 (R)
Logic Level : 2
Delay Ratio : 87.4% (route), 12.6% (logic)
Clock Skew : 0.136 ns
Hold Constraint : -7.500 ns
Common Path Skew : -0.016 ns
Path Slack : 9.594 ns (Passed)
Source Clock Path
{
"path_begin":
{
"type":"pin",
"log_name":"Clk_pad.bb_inst/O",
"phy_name":"Clk_pad.bb_inst/PADDI"
},
"path_end":
{
"type":"pin",
"log_name":"A_Sig_c.ff_inst/CLK",
"phy_name":"A_Sig_c.SLICE_1/CLK"
},
"path_sections":[
{
"type":"net_delay",
"net":
{
"log_name":"MyPLL/lscc_pll_inst/REFCK",
"phy_name":"Clk_c"
},
"arrive":0.240,
"delay":0.240
},
{
"type":"site_delay",
"pin0":
{
"log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK",
"phy_name":"MyPLL.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/REFCK"
},
"pin1":
{
"log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP",
"phy_name":"MyPLL.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP"
},
"arrive":0.240,
"delay":0.000
},
{
"type":"site_delay",
"pin0":
{
"log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK",
"phy_name":"MyPLL.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/REFCK"
},
"pin1":
{
"log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP",
"phy_name":"MyPLL.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP"
},
"arrive":0.240,
"delay":0.000
},
{
"type":"net_delay",
"net":
{
"log_name":"MyPLL/lscc_pll_inst/clk1",
"phy_name":"clk1"
},
"arrive":2.117,
"delay":1.877
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":2.117,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- ---------------- ---------------- ------ --------------------- ------
Clk_pad.bb_inst/PADDI SEIO18A_CORE_K15 CLOCK LATENCY 0.000 0.000 1
MyPLL/lscc_pll_inst/REFCK NET DELAY 0.240 0.240 1
MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK->MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP
PLL_CORE_PLL_LLC 0.000 0.240 2
MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK->MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP (TOTAL_ADJUSTMENTS)
PLL_CORE_PLL_LLC 0.000 0.240 2
MyPLL/lscc_pll_inst/clk1 NET DELAY 1.877 2.117 2
A_Sig_c.ff_inst/CLK CLOCK PIN 0.000 2.117 1
Data Path
{
"path_begin":
{
"type":"pin",
"log_name":"A_Sig_c.ff_inst/Q",
"phy_name":"A_Sig_c.SLICE_1/Q0"
},
"path_end":
{
"type":"pin",
"log_name":"B_sig1.ff_inst/DF",
"phy_name":"SLICE_0/DI0"
},
"path_sections":[
{
"type":"site_delay",
"pin0":
{
"log_name":"A_Sig_c.ff_inst/CLK",
"phy_name":"A_Sig_c.SLICE_1/CLK"
},
"pin1":
{
"log_name":"A_Sig_c.ff_inst/Q",
"phy_name":"A_Sig_c.SLICE_1/Q0"
},
"arrive":2.295,
"delay":0.178
},
{
"type":"net_delay",
"net":
{
"log_name":"A_Sig",
"phy_name":"A_Sig"
},
"arrive":4.329,
"delay":2.034
},
{
"type":"site_delay",
"pin0":
{
"log_name":"i8_2_lut/B",
"phy_name":"SLICE_0/D0"
},
"pin1":
{
"log_name":"i8_2_lut/Z",
"phy_name":"SLICE_0/F0"
},
"arrive":4.445,
"delay":0.116
},
{
"type":"net_delay",
"net":
{
"log_name":"out2_c_N_1",
"phy_name":"out2_c_N_1"
},
"arrive":4.445,
"delay":0.000
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":4.445,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- ---------------- ---------------- ------ --------------------- ------
A_Sig_c.ff_inst/CLK->A_Sig_c.ff_inst/Q SLICE_R4C4D REG_DEL 0.178 2.295 2
A_Sig NET DELAY 2.034 4.329 2
i8_2_lut/B->i8_2_lut/Z SLICE_R50C100D CTOF_DEL 0.116 4.445 1
out2_c_N_1 NET DELAY 0.000 4.445 1
B_sig1.ff_inst/DF ENDPOINT 0.000 4.445 1
Destination Clock Path
{
"path_begin":
{
"type":"pin",
"log_name":"Clk_pad.bb_inst/O",
"phy_name":"Clk_pad.bb_inst/PADDI"
},
"path_end":
{
"type":"pin",
"log_name":"B_sig1.ff_inst/CLK",
"phy_name":"SLICE_0/CLK"
},
"path_sections":[
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":-7.500,
"delay":0.000
},
{
"type":"net_delay",
"net":
{
"log_name":"MyPLL/lscc_pll_inst/REFCK",
"phy_name":"Clk_c"
},
"arrive":-7.243,
"delay":0.257
},
{
"type":"site_delay",
"pin0":
{
"log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK",
"phy_name":"MyPLL.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/REFCK"
},
"pin1":
{
"log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS",
"phy_name":"MyPLL.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS"
},
"arrive":-7.243,
"delay":0.000
},
{
"type":"site_delay",
"pin0":
{
"log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK",
"phy_name":"MyPLL.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/REFCK"
},
"pin1":
{
"log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS",
"phy_name":"MyPLL.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS"
},
"arrive":-7.243,
"delay":0.000
},
{
"type":"net_delay",
"net":
{
"log_name":"MyPLL/lscc_pll_inst/clk2",
"phy_name":"clk2"
},
"arrive":-5.247,
"delay":1.996
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":-5.247,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- ---------------- ---------------- ------ --------------------- ------
CONSTRAINT 0.000 -7.500 1
Clk_pad.bb_inst/PADDI SEIO18A_CORE_K15 CLOCK LATENCY 0.000 -7.500 1
MyPLL/lscc_pll_inst/REFCK NET DELAY 0.257 -7.243 1
MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK->MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS
PLL_CORE_PLL_LLC 0.000 -7.243 2
MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK->MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS (TOTAL_ADJUSTMENTS)
PLL_CORE_PLL_LLC 0.000 -7.243 2
MyPLL/lscc_pll_inst/clk2 NET DELAY 1.996 -5.247 2
B_sig1.ff_inst/CLK CLOCK PIN 0.000 -5.247 1
Uncertainty 0.000 -5.247
Common Path Skew -0.016 -5.263
Hold time 0.114 -5.149
---------------------------------------- ---------------- ---------------- ------ --------------------- ------
Required Time 5.149
Arrival Time 4.445
---------------------------------------- ---------------- ---------------- ------ --------------------- ------
Path Slack (Passed) 9.594
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
End of Detailed Report for timing paths
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
##########################################################