Timing Report
Lattice Timing Report -  Setup  and Hold, Version Radiant Software (64-bit) 2023.2.1.288.0

Wed Jun  5 12:16:43 2024

Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp.   All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
Copyright (c) 2001 Agere Systems   All rights reserved.
Copyright (c) 2002-2023 Lattice Semiconductor Corporation,  All rights reserved.

Command line:    timing -sethld -sp 9_High-Performance_1.0V -hsp m -v 10 -u 10 -endpoints 10 -nperend 1 -html -rpt lab03_impl_1.tw1 lab03_impl_1_map.udb -gui -msgset C:/Users/ssyahril/Downloads/FAE_F2F_Training_Labs_V2/FAE_F2F_Training_Labs_V2/LAB_03/promote.xml

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Design:          top
Family:          LIFCL
Device:          LIFCL-17
Package:         QFN72
Performance:     9_High-Performance_1.0V
Package Status:                     Final          Version 23
Performance Hardware Data Status :   Final Version 118.1
-------------------------------------------


=====================================================================
                    Table of Contents
=====================================================================
  • 1 Timing Overview
  • 1.1 SDC Constraints
  • 1.2 Constraint Coverage
  • 1.3 Overall Summary
  • 1.4 Unconstrained Report
  • 1.5 Combinational Loop
  • 2 Setup at Speed Grade 9_High-Performance_1.0V Corner at 85 Degrees
  • 2.1 Clock Summary
  • 2.2 Endpoint slacks
  • 2.3 Detailed Report
  • 3 Setup at Speed Grade 9_High-Performance_1.0V Corner at 0 Degrees
  • 3.1 Clock Summary
  • 3.2 Endpoint slacks
  • 3.3 Detailed Report
  • 4 Hold at Speed Grade m Corner at 0 Degrees
  • 4.1 Endpoint slacks
  • 4.2 Detailed Report
  • ===================================================================== End of Table of Contents ===================================================================== 1 Timing Overview 1.1 SDC Constraints create_clock -name {CLK1} -period 10 [get_ports Clk] create_generated_clock -name {CLK2} -source [get_pins Clk_pad.bb_inst/O] -edges {1 2 9} [get_pins MyDCC/CLKO] 1.2 Constraint Coverage Constraint Coverage: 66.6667% 1.3 Overall Summary Setup at Speed Grade 9_High-Performance_1.0V Corner at 85 Degrees Timing Errors: 0 endpoints; Total Negative Slack: 0.000 ns Setup at Speed Grade 9_High-Performance_1.0V Corner at 0 Degrees Timing Errors: 0 endpoints; Total Negative Slack: 0.000 ns Hold at Speed Grade m Corner at 0 Degrees Timing Errors: 0 endpoints; Total Negative Slack: 0.000 ns 1.4 Unconstrained Report 1.4.1 Unconstrained Start/End Points Clocked but unconstrained timing start points ------------------------------------------------------------------- Listing 8 Start Points | Type ------------------------------------------------------------------- CNT2_d_i8.ff_inst/Q | No required time CNT2_d_i7.ff_inst/Q | No required time CNT2_d_i6.ff_inst/Q | No required time CNT2_d_i5.ff_inst/Q | No required time CNT2_d_i4.ff_inst/Q | No required time CNT2_d_i3.ff_inst/Q | No required time CNT2_d_i2.ff_inst/Q | No required time CNT2_d_i1.ff_inst/Q | No required time ------------------------------------------------------------------- | Number of unconstrained timing start po | ints | 8 | ------------------------------------------------------------------- Clocked but unconstrained timing end points ------------------------------------------------------------------- Listing 2 End Points | Type ------------------------------------------------------------------- CNT1_e3_e3_e3_21__i1.ff_inst/CE | No arrival time CNT1_e3_e3_e3_21__i0.ff_inst/CE | No arrival time ------------------------------------------------------------------- | Number of unconstrained timing end poin | ts | 2 | ------------------------------------------------------------------- 1.4.2 Start/End Points Without Timing Constraints I/O ports without constraint ---------------------------- Possible constraints to use on I/O ports are: set_input_delay, set_output_delay, set_max_delay, create_clock, create_generated_clock, ... ------------------------------------------------------------------- Listing 9 Start or End Points | Type ------------------------------------------------------------------- En1 | input out2[5] | output out2[6] | output out2[7] | output out2[4] | output out2[3] | output out2[2] | output out2[1] | output out2[0] | output ------------------------------------------------------------------- | Number of I/O ports without constraint | 9 | ------------------------------------------------------------------- Nets without clock definition Define a clock on a top level port or a generated clock on a clock divider pin associated with this net(s). -------------------------------------------------- There is no instance satisfying reporting criteria 1.5 Combinational Loop None 2 Setup at Speed Grade 9_High-Performance_1.0V Corner at 85 Degrees 2.1 Clock Summary 2.1.1 Clock "CLK1" create_clock -name {CLK1} -period 10 [get_ports Clk] Single Clock Domain ------------------------------------------------------------------------------------------------------- Clock CLK1 | | Period | Frequency ------------------------------------------------------------------------------------------------------- From CLK1 | Target | 10.000 ns | 100.000 MHz | Actual (all paths) | 5.000 ns | 200.000 MHz Clk_pad.bb_inst/B (MPW) | (50% duty cycle) | 5.000 ns | 200.000 MHz ------------------------------------------------------------------------------------------------------- Clock Domain Crossing ------------------------------------------------------------------------------------------------------ Clock CLK1 | Worst Time Between Edges | Comment ------------------------------------------------------------------------------------------------------ From CLK2 | ---- | No path ------------------------------------------------------------------------------------------------------ 2.1.2 Clock "CLK2" create_generated_clock -name {CLK2} -source [get_pins Clk_pad.bb_inst/O] -edges {1 2 9} [get_pins MyDCC/CLKO] Single Clock Domain ------------------------------------------------------------------------------------------------------- Clock CLK2 | | Period | Frequency ------------------------------------------------------------------------------------------------------- From CLK2 | Target | 40.000 ns | 25.000 MHz | Actual (all paths) | 2.000 ns | 500.000 MHz CNT2_d_i8.ff_inst/CLK (MPW) | (50% duty cycle) | 2.000 ns | 500.000 MHz ------------------------------------------------------------------------------------------------------- Clock Domain Crossing ------------------------------------------------------------------------------------------------------ Clock CLK2 | Worst Time Between Edges | Comment ------------------------------------------------------------------------------------------------------ From CLK1 | ---- | No path ------------------------------------------------------------------------------------------------------ 2.2 Endpoint slacks ------------------------------------------------------- Listing 10 End Points | Slack ------------------------------------------------------- CNT2_d_i1.ff_inst/DF | 4.186 ns CNT2_d_i3.ff_inst/DF | 4.186 ns CNT2_d_i5.ff_inst/DF | 4.186 ns CNT2_d_i7.ff_inst/DF | 4.186 ns CNT2_d_i2.ff_inst/DF | 4.189 ns CNT2_d_i4.ff_inst/DF | 4.189 ns CNT2_d_i6.ff_inst/DF | 4.189 ns CNT2_d_i8.ff_inst/DF | 4.189 ns MyDCC/CE | 8.613 ns CNT1_e3_e3_e3_21__i1.ff_inst/DF | 9.106 ns ------------------------------------------------------- | Setup # of endpoints with negative slack:| 0 | ------------------------------------------------------- 2.3 Detailed Report XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX Detail report of critical paths XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Detailed Report for timing paths +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ ++++Path 1 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Path Begin : CNT2_e3_e3_e3_20__i0.ff_inst/Q (SLICE) Path End : CNT2_d_i1.ff_inst/DF (SLICE) Source Clock : CLK2 (R) Destination Clock: CLK2 (F) Logic Level : 1 Delay Ratio : 58.6% (route), 41.4% (logic) Clock Skew : -0.107 ns Setup Constraint : 5.000 ns Common Path Skew : 0.000 ns Path Slack : 4.186 ns (Passed) Source Clock Path { "path_begin": { "type":"port", "log_name":"Clk", "phy_name":"Clk" }, "path_end": { "type":"pin", "log_name":"CNT2_e3_e3_e3_20__i0.ff_inst/CLK", "phy_name":"SLICE_1/CLK" }, "path_sections":[ { "type":"net_delay", "net": { "log_name":"Clk", "phy_name":"Clk" }, "arrive":0.000, "delay":0.000 }, { "type":"site_delay", "pin0": { "log_name":"Clk_pad.bb_inst/B", "phy_name":"Clk_pad.bb_inst/IOPAD" }, "pin1": { "log_name":"Clk_pad.bb_inst/O", "phy_name":"Clk_pad.bb_inst/PADDI" }, "arrive":1.366, "delay":1.366 }, { "type":"net_delay", "net": { "log_name":"Clk_c", "phy_name":"Clk_c" }, "arrive":1.801, "delay":0.435 }, { "type":"site_delay", "pin0": { "log_name":"MyDCC/CLKI", "phy_name":"MyDCC/CLKI" }, "pin1": { "log_name":"MyDCC/CLKO", "phy_name":"MyDCC/CLKO" }, "arrive":1.801, "delay":0.000 }, { "type":"net_delay", "net": { "log_name":"clk2", "phy_name":"clk2" }, "arrive":2.236, "delay":0.435 }, { "type":"site_delay", "pin0": { "log_name":"", "phy_name":"" }, "pin1": { "log_name":"", "phy_name":"" }, "arrive":2.236, "delay":0.000 } ] } Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- -------------- ---------------- --------- --------------------- ------ Clk top CLOCK LATENCY 0.000 0.000 1 Clk NET DELAY 0.000 0.000 1 Clk_pad.bb_inst/B->Clk_pad.bb_inst/O SEIO33_CORE PADI_DEL 1.366 1.366 3 Clk_c NET DELAY 0.435 1.801 3 MyDCC/CLKI->MyDCC/CLKO DCC DCC_DEL 0.000 1.801 13 clk2 NET DELAY 0.435 2.236 13 CNT2_e3_e3_e3_20__i0.ff_inst/CLK CLOCK PIN 0.000 2.236 1 Data Path { "path_begin": { "type":"pin", "log_name":"CNT2_e3_e3_e3_20__i0.ff_inst/Q", "phy_name":"SLICE_1/Q1" }, "path_end": { "type":"pin", "log_name":"CNT2_d_i1.ff_inst/DF", "phy_name":"CNT2_d_i1.SLICE_14/M0" }, "path_sections":[ { "type":"site_delay", "pin0": { "log_name":"CNT2_e3_e3_e3_20__i0.ff_inst/CLK", "phy_name":"SLICE_1/CLK" }, "pin1": { "log_name":"CNT2_e3_e3_e3_20__i0.ff_inst/Q", "phy_name":"SLICE_1/Q1" }, "arrive":2.543, "delay":0.307 }, { "type":"net_delay", "net": { "log_name":"CNT2[0]", "phy_name":"CNT2[0]" }, "arrive":2.978, "delay":0.435 }, { "type":"site_delay", "pin0": { "log_name":"", "phy_name":"" }, "pin1": { "log_name":"", "phy_name":"" }, "arrive":2.978, "delay":0.000 } ] } Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- -------------- ---------------- --------- --------------------- ------ CNT2_e3_e3_e3_20__i0.ff_inst/CLK->CNT2_e3_e3_e3_20__i0.ff_inst/Q SLICE REG_DEL 0.307 2.543 2 CNT2[0] NET DELAY 0.435 2.978 2 CNT2_d_i1.ff_inst/DF ENDPOINT 0.000 2.978 1 Destination Clock Path { "path_begin": { "type":"port", "log_name":"Clk", "phy_name":"Clk" }, "path_end": { "type":"pin", "log_name":"CNT2_d_i1.ff_inst/CLK", "phy_name":"CNT2_d_i1.SLICE_14/CLK" }, "path_sections":[ { "type":"site_delay", "pin0": { "log_name":"", "phy_name":"" }, "pin1": { "log_name":"", "phy_name":"" }, "arrive":5.000, "delay":0.000 }, { "type":"net_delay", "net": { "log_name":"Clk", "phy_name":"Clk" }, "arrive":5.000, "delay":0.000 }, { "type":"site_delay", "pin0": { "log_name":"Clk_pad.bb_inst/B", "phy_name":"Clk_pad.bb_inst/IOPAD" }, "pin1": { "log_name":"Clk_pad.bb_inst/O", "phy_name":"Clk_pad.bb_inst/PADDI" }, "arrive":6.259, "delay":1.259 }, { "type":"net_delay", "net": { "log_name":"Clk_c", "phy_name":"Clk_c" }, "arrive":6.694, "delay":0.435 }, { "type":"site_delay", "pin0": { "log_name":"MyDCC/CLKI", "phy_name":"MyDCC/CLKI" }, "pin1": { "log_name":"MyDCC/CLKO", "phy_name":"MyDCC/CLKO" }, "arrive":6.694, "delay":0.000 }, { "type":"net_delay", "net": { "log_name":"clk2", "phy_name":"clk2" }, "arrive":7.129, "delay":0.435 }, { "type":"site_delay", "pin0": { "log_name":"", "phy_name":"" }, "pin1": { "log_name":"", "phy_name":"" }, "arrive":7.129, "delay":0.000 } ] } Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- -------------- ---------------- --------- --------------------- ------ CONSTRAINT 0.000 5.000 1 Clk top CLOCK LATENCY 0.000 5.000 1 Clk NET DELAY 0.000 5.000 1 Clk_pad.bb_inst/B->Clk_pad.bb_inst/O SEIO33_CORE PADI_DEL 1.259 6.259 3 Clk_c NET DELAY 0.435 6.694 3 MyDCC/CLKI->MyDCC/CLKO DCC DCC_DEL 0.000 6.694 13 clk2 NET DELAY 0.435 7.129 13 CNT2_d_i1.ff_inst/CLK CLOCK PIN 0.000 7.129 1 Uncertainty -(0.000) 7.129 Common Path Skew 0.000 7.129 Setup time -(-0.035) 7.164 ---------------------------------------- -------------- ---------------- --------- --------------------- ------ Required Time 7.164 Arrival Time -(2.978) ---------------------------------------- -------------- ---------------- --------- --------------------- ------ Path Slack (Passed) 4.186 ++++ Path 2 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Path Begin : CNT2_e3_e3_e3_20__i2.ff_inst/Q (SLICE) Path End : CNT2_d_i3.ff_inst/DF (SLICE) Source Clock : CLK2 (R) Destination Clock: CLK2 (F) Logic Level : 1 Delay Ratio : 58.6% (route), 41.4% (logic) Clock Skew : -0.107 ns Setup Constraint : 5.000 ns Common Path Skew : 0.000 ns Path Slack : 4.186 ns (Passed) Source Clock Path { "path_begin": { "type":"port", "log_name":"Clk", "phy_name":"Clk" }, "path_end": { "type":"pin", "log_name":"CNT2_e3_e3_e3_20__i1.ff_inst/CLK", "phy_name":"SLICE_2/CLK" }, "path_sections":[ { "type":"net_delay", "net": { "log_name":"Clk", "phy_name":"Clk" }, "arrive":0.000, "delay":0.000 }, { "type":"site_delay", "pin0": { "log_name":"Clk_pad.bb_inst/B", "phy_name":"Clk_pad.bb_inst/IOPAD" }, "pin1": { "log_name":"Clk_pad.bb_inst/O", "phy_name":"Clk_pad.bb_inst/PADDI" }, "arrive":1.366, "delay":1.366 }, { "type":"net_delay", "net": { "log_name":"Clk_c", "phy_name":"Clk_c" }, "arrive":1.801, "delay":0.435 }, { "type":"site_delay", "pin0": { "log_name":"MyDCC/CLKI", "phy_name":"MyDCC/CLKI" }, "pin1": { "log_name":"MyDCC/CLKO", "phy_name":"MyDCC/CLKO" }, "arrive":1.801, "delay":0.000 }, { "type":"net_delay", "net": { "log_name":"clk2", "phy_name":"clk2" }, "arrive":2.236, "delay":0.435 }, { "type":"site_delay", "pin0": { "log_name":"", "phy_name":"" }, "pin1": { "log_name":"", "phy_name":"" }, "arrive":2.236, "delay":0.000 } ] } Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- -------------- ---------------- --------- --------------------- ------ Clk top CLOCK LATENCY 0.000 0.000 1 Clk NET DELAY 0.000 0.000 1 Clk_pad.bb_inst/B->Clk_pad.bb_inst/O SEIO33_CORE PADI_DEL 1.366 1.366 3 Clk_c NET DELAY 0.435 1.801 3 MyDCC/CLKI->MyDCC/CLKO DCC DCC_DEL 0.000 1.801 13 clk2 NET DELAY 0.435 2.236 13 {CNT2_e3_e3_e3_20__i1.ff_inst/CLK CNT2_e3_e3_e3_20__i2.ff_inst/CLK} CLOCK PIN 0.000 2.236 1 Data Path { "path_begin": { "type":"pin", "log_name":"CNT2_e3_e3_e3_20__i2.ff_inst/Q", "phy_name":"SLICE_2/Q1" }, "path_end": { "type":"pin", "log_name":"CNT2_d_i3.ff_inst/DF", "phy_name":"CNT2_d_i3.SLICE_12/M0" }, "path_sections":[ { "type":"site_delay", "pin0": { "log_name":"CNT2_e3_e3_e3_20__i2.ff_inst/CLK", "phy_name":"SLICE_2/CLK" }, "pin1": { "log_name":"CNT2_e3_e3_e3_20__i2.ff_inst/Q", "phy_name":"SLICE_2/Q1" }, "arrive":2.543, "delay":0.307 }, { "type":"net_delay", "net": { "log_name":"CNT2[2]", "phy_name":"CNT2[2]" }, "arrive":2.978, "delay":0.435 }, { "type":"site_delay", "pin0": { "log_name":"", "phy_name":"" }, "pin1": { "log_name":"", "phy_name":"" }, "arrive":2.978, "delay":0.000 } ] } Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- -------------- ---------------- --------- --------------------- ------ CNT2_e3_e3_e3_20__i2.ff_inst/CLK->CNT2_e3_e3_e3_20__i2.ff_inst/Q SLICE REG_DEL 0.307 2.543 2 CNT2[2] NET DELAY 0.435 2.978 2 CNT2_d_i3.ff_inst/DF ENDPOINT 0.000 2.978 1 Destination Clock Path { "path_begin": { "type":"port", "log_name":"Clk", "phy_name":"Clk" }, "path_end": { "type":"pin", "log_name":"CNT2_d_i3.ff_inst/CLK", "phy_name":"CNT2_d_i3.SLICE_12/CLK" }, "path_sections":[ { "type":"site_delay", "pin0": { "log_name":"", "phy_name":"" }, "pin1": { "log_name":"", "phy_name":"" }, "arrive":5.000, "delay":0.000 }, { "type":"net_delay", "net": { "log_name":"Clk", "phy_name":"Clk" }, "arrive":5.000, "delay":0.000 }, { "type":"site_delay", "pin0": { "log_name":"Clk_pad.bb_inst/B", "phy_name":"Clk_pad.bb_inst/IOPAD" }, "pin1": { "log_name":"Clk_pad.bb_inst/O", "phy_name":"Clk_pad.bb_inst/PADDI" }, "arrive":6.259, "delay":1.259 }, { "type":"net_delay", "net": { "log_name":"Clk_c", "phy_name":"Clk_c" }, "arrive":6.694, "delay":0.435 }, { "type":"site_delay", "pin0": { "log_name":"MyDCC/CLKI", "phy_name":"MyDCC/CLKI" }, "pin1": { "log_name":"MyDCC/CLKO", "phy_name":"MyDCC/CLKO" }, "arrive":6.694, "delay":0.000 }, { "type":"net_delay", "net": { "log_name":"clk2", "phy_name":"clk2" }, "arrive":7.129, "delay":0.435 }, { "type":"site_delay", "pin0": { "log_name":"", "phy_name":"" }, "pin1": { "log_name":"", "phy_name":"" }, "arrive":7.129, "delay":0.000 } ] } Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- -------------- ---------------- --------- --------------------- ------ CONSTRAINT 0.000 5.000 1 Clk top CLOCK LATENCY 0.000 5.000 1 Clk NET DELAY 0.000 5.000 1 Clk_pad.bb_inst/B->Clk_pad.bb_inst/O SEIO33_CORE PADI_DEL 1.259 6.259 3 Clk_c NET DELAY 0.435 6.694 3 MyDCC/CLKI->MyDCC/CLKO DCC DCC_DEL 0.000 6.694 13 clk2 NET DELAY 0.435 7.129 13 CNT2_d_i3.ff_inst/CLK CLOCK PIN 0.000 7.129 1 Uncertainty -(0.000) 7.129 Common Path Skew 0.000 7.129 Setup time -(-0.035) 7.164 ---------------------------------------- -------------- ---------------- --------- --------------------- ------ Required Time 7.164 Arrival Time -(2.978) ---------------------------------------- -------------- ---------------- --------- --------------------- ------ Path Slack (Passed) 4.186 ++++ Path 3 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Path Begin : CNT2_e3_e3_e3_20__i4.ff_inst/Q (SLICE) Path End : CNT2_d_i5.ff_inst/DF (SLICE) Source Clock : CLK2 (R) Destination Clock: CLK2 (F) Logic Level : 1 Delay Ratio : 58.6% (route), 41.4% (logic) Clock Skew : -0.107 ns Setup Constraint : 5.000 ns Common Path Skew : 0.000 ns Path Slack : 4.186 ns (Passed) Source Clock Path { "path_begin": { "type":"port", "log_name":"Clk", "phy_name":"Clk" }, "path_end": { "type":"pin", "log_name":"CNT2_e3_e3_e3_20__i3.ff_inst/CLK", "phy_name":"SLICE_0/CLK" }, "path_sections":[ { "type":"net_delay", "net": { "log_name":"Clk", "phy_name":"Clk" }, "arrive":0.000, "delay":0.000 }, { "type":"site_delay", "pin0": { "log_name":"Clk_pad.bb_inst/B", "phy_name":"Clk_pad.bb_inst/IOPAD" }, "pin1": { "log_name":"Clk_pad.bb_inst/O", "phy_name":"Clk_pad.bb_inst/PADDI" }, "arrive":1.366, "delay":1.366 }, { "type":"net_delay", "net": { "log_name":"Clk_c", "phy_name":"Clk_c" }, "arrive":1.801, "delay":0.435 }, { "type":"site_delay", "pin0": { "log_name":"MyDCC/CLKI", "phy_name":"MyDCC/CLKI" }, "pin1": { "log_name":"MyDCC/CLKO", "phy_name":"MyDCC/CLKO" }, "arrive":1.801, "delay":0.000 }, { "type":"net_delay", "net": { "log_name":"clk2", "phy_name":"clk2" }, "arrive":2.236, "delay":0.435 }, { "type":"site_delay", "pin0": { "log_name":"", "phy_name":"" }, "pin1": { "log_name":"", "phy_name":"" }, "arrive":2.236, "delay":0.000 } ] } Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- -------------- ---------------- --------- --------------------- ------ Clk top CLOCK LATENCY 0.000 0.000 1 Clk NET DELAY 0.000 0.000 1 Clk_pad.bb_inst/B->Clk_pad.bb_inst/O SEIO33_CORE PADI_DEL 1.366 1.366 3 Clk_c NET DELAY 0.435 1.801 3 MyDCC/CLKI->MyDCC/CLKO DCC DCC_DEL 0.000 1.801 13 clk2 NET DELAY 0.435 2.236 13 {CNT2_e3_e3_e3_20__i3.ff_inst/CLK CNT2_e3_e3_e3_20__i4.ff_inst/CLK} CLOCK PIN 0.000 2.236 1 Data Path { "path_begin": { "type":"pin", "log_name":"CNT2_e3_e3_e3_20__i4.ff_inst/Q", "phy_name":"SLICE_0/Q1" }, "path_end": { "type":"pin", "log_name":"CNT2_d_i5.ff_inst/DF", "phy_name":"CNT2_d_i5.SLICE_10/M0" }, "path_sections":[ { "type":"site_delay", "pin0": { "log_name":"CNT2_e3_e3_e3_20__i4.ff_inst/CLK", "phy_name":"SLICE_0/CLK" }, "pin1": { "log_name":"CNT2_e3_e3_e3_20__i4.ff_inst/Q", "phy_name":"SLICE_0/Q1" }, "arrive":2.543, "delay":0.307 }, { "type":"net_delay", "net": { "log_name":"CNT2[4]", "phy_name":"CNT2[4]" }, "arrive":2.978, "delay":0.435 }, { "type":"site_delay", "pin0": { "log_name":"", "phy_name":"" }, "pin1": { "log_name":"", "phy_name":"" }, "arrive":2.978, "delay":0.000 } ] } Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- -------------- ---------------- --------- --------------------- ------ CNT2_e3_e3_e3_20__i4.ff_inst/CLK->CNT2_e3_e3_e3_20__i4.ff_inst/Q SLICE REG_DEL 0.307 2.543 2 CNT2[4] NET DELAY 0.435 2.978 2 CNT2_d_i5.ff_inst/DF ENDPOINT 0.000 2.978 1 Destination Clock Path { "path_begin": { "type":"port", "log_name":"Clk", "phy_name":"Clk" }, "path_end": { "type":"pin", "log_name":"CNT2_d_i5.ff_inst/CLK", "phy_name":"CNT2_d_i5.SLICE_10/CLK" }, "path_sections":[ { "type":"site_delay", "pin0": { "log_name":"", "phy_name":"" }, "pin1": { "log_name":"", "phy_name":"" }, "arrive":5.000, "delay":0.000 }, { "type":"net_delay", "net": { "log_name":"Clk", "phy_name":"Clk" }, "arrive":5.000, "delay":0.000 }, { "type":"site_delay", "pin0": { "log_name":"Clk_pad.bb_inst/B", "phy_name":"Clk_pad.bb_inst/IOPAD" }, "pin1": { "log_name":"Clk_pad.bb_inst/O", "phy_name":"Clk_pad.bb_inst/PADDI" }, "arrive":6.259, "delay":1.259 }, { "type":"net_delay", "net": { "log_name":"Clk_c", "phy_name":"Clk_c" }, "arrive":6.694, "delay":0.435 }, { "type":"site_delay", "pin0": { "log_name":"MyDCC/CLKI", "phy_name":"MyDCC/CLKI" }, "pin1": { "log_name":"MyDCC/CLKO", "phy_name":"MyDCC/CLKO" }, "arrive":6.694, "delay":0.000 }, { "type":"net_delay", "net": { "log_name":"clk2", "phy_name":"clk2" }, "arrive":7.129, "delay":0.435 }, { "type":"site_delay", "pin0": { "log_name":"", "phy_name":"" }, "pin1": { "log_name":"", "phy_name":"" }, "arrive":7.129, "delay":0.000 } ] } Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- -------------- ---------------- --------- --------------------- ------ CONSTRAINT 0.000 5.000 1 Clk top CLOCK LATENCY 0.000 5.000 1 Clk NET DELAY 0.000 5.000 1 Clk_pad.bb_inst/B->Clk_pad.bb_inst/O SEIO33_CORE PADI_DEL 1.259 6.259 3 Clk_c NET DELAY 0.435 6.694 3 MyDCC/CLKI->MyDCC/CLKO DCC DCC_DEL 0.000 6.694 13 clk2 NET DELAY 0.435 7.129 13 CNT2_d_i5.ff_inst/CLK CLOCK PIN 0.000 7.129 1 Uncertainty -(0.000) 7.129 Common Path Skew 0.000 7.129 Setup time -(-0.035) 7.164 ---------------------------------------- -------------- ---------------- --------- --------------------- ------ Required Time 7.164 Arrival Time -(2.978) ---------------------------------------- -------------- ---------------- --------- --------------------- ------ Path Slack (Passed) 4.186 ++++ Path 4 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Path Begin : CNT2_e3_e3_e3_20__i6.ff_inst/Q (SLICE) Path End : CNT2_d_i7.ff_inst/DF (SLICE) Source Clock : CLK2 (R) Destination Clock: CLK2 (F) Logic Level : 1 Delay Ratio : 58.6% (route), 41.4% (logic) Clock Skew : -0.107 ns Setup Constraint : 5.000 ns Common Path Skew : 0.000 ns Path Slack : 4.186 ns (Passed) Source Clock Path { "path_begin": { "type":"port", "log_name":"Clk", "phy_name":"Clk" }, "path_end": { "type":"pin", "log_name":"CNT2_e3_e3_e3_20__i5.ff_inst/CLK", "phy_name":"SLICE_3/CLK" }, "path_sections":[ { "type":"net_delay", "net": { "log_name":"Clk", "phy_name":"Clk" }, "arrive":0.000, "delay":0.000 }, { "type":"site_delay", "pin0": { "log_name":"Clk_pad.bb_inst/B", "phy_name":"Clk_pad.bb_inst/IOPAD" }, "pin1": { "log_name":"Clk_pad.bb_inst/O", "phy_name":"Clk_pad.bb_inst/PADDI" }, "arrive":1.366, "delay":1.366 }, { "type":"net_delay", "net": { "log_name":"Clk_c", "phy_name":"Clk_c" }, "arrive":1.801, "delay":0.435 }, { "type":"site_delay", "pin0": { "log_name":"MyDCC/CLKI", "phy_name":"MyDCC/CLKI" }, "pin1": { "log_name":"MyDCC/CLKO", "phy_name":"MyDCC/CLKO" }, "arrive":1.801, "delay":0.000 }, { "type":"net_delay", "net": { "log_name":"clk2", "phy_name":"clk2" }, "arrive":2.236, "delay":0.435 }, { "type":"site_delay", "pin0": { "log_name":"", "phy_name":"" }, "pin1": { "log_name":"", "phy_name":"" }, "arrive":2.236, "delay":0.000 } ] } Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- -------------- ---------------- --------- --------------------- ------ Clk top CLOCK LATENCY 0.000 0.000 1 Clk NET DELAY 0.000 0.000 1 Clk_pad.bb_inst/B->Clk_pad.bb_inst/O SEIO33_CORE PADI_DEL 1.366 1.366 3 Clk_c NET DELAY 0.435 1.801 3 MyDCC/CLKI->MyDCC/CLKO DCC DCC_DEL 0.000 1.801 13 clk2 NET DELAY 0.435 2.236 13 {CNT2_e3_e3_e3_20__i5.ff_inst/CLK CNT2_e3_e3_e3_20__i6.ff_inst/CLK} CLOCK PIN 0.000 2.236 1 Data Path { "path_begin": { "type":"pin", "log_name":"CNT2_e3_e3_e3_20__i6.ff_inst/Q", "phy_name":"SLICE_3/Q1" }, "path_end": { "type":"pin", "log_name":"CNT2_d_i7.ff_inst/DF", "phy_name":"CNT2_d_i7.SLICE_7/M0" }, "path_sections":[ { "type":"site_delay", "pin0": { "log_name":"CNT2_e3_e3_e3_20__i6.ff_inst/CLK", "phy_name":"SLICE_3/CLK" }, "pin1": { "log_name":"CNT2_e3_e3_e3_20__i6.ff_inst/Q", "phy_name":"SLICE_3/Q1" }, "arrive":2.543, "delay":0.307 }, { "type":"net_delay", "net": { "log_name":"CNT2[6]", "phy_name":"CNT2[6]" }, "arrive":2.978, "delay":0.435 }, { "type":"site_delay", "pin0": { "log_name":"", "phy_name":"" }, "pin1": { "log_name":"", "phy_name":"" }, "arrive":2.978, "delay":0.000 } ] } Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- -------------- ---------------- --------- --------------------- ------ CNT2_e3_e3_e3_20__i6.ff_inst/CLK->CNT2_e3_e3_e3_20__i6.ff_inst/Q SLICE REG_DEL 0.307 2.543 2 CNT2[6] NET DELAY 0.435 2.978 2 CNT2_d_i7.ff_inst/DF ENDPOINT 0.000 2.978 1 Destination Clock Path { "path_begin": { "type":"port", "log_name":"Clk", "phy_name":"Clk" }, "path_end": { "type":"pin", "log_name":"CNT2_d_i7.ff_inst/CLK", "phy_name":"CNT2_d_i7.SLICE_7/CLK" }, "path_sections":[ { "type":"site_delay", "pin0": { "log_name":"", "phy_name":"" }, "pin1": { "log_name":"", "phy_name":"" }, "arrive":5.000, "delay":0.000 }, { "type":"net_delay", "net": { "log_name":"Clk", "phy_name":"Clk" }, "arrive":5.000, "delay":0.000 }, { "type":"site_delay", "pin0": { "log_name":"Clk_pad.bb_inst/B", "phy_name":"Clk_pad.bb_inst/IOPAD" }, "pin1": { "log_name":"Clk_pad.bb_inst/O", "phy_name":"Clk_pad.bb_inst/PADDI" }, "arrive":6.259, "delay":1.259 }, { "type":"net_delay", "net": { "log_name":"Clk_c", "phy_name":"Clk_c" }, "arrive":6.694, "delay":0.435 }, { "type":"site_delay", "pin0": { "log_name":"MyDCC/CLKI", "phy_name":"MyDCC/CLKI" }, "pin1": { "log_name":"MyDCC/CLKO", "phy_name":"MyDCC/CLKO" }, "arrive":6.694, "delay":0.000 }, { "type":"net_delay", "net": { "log_name":"clk2", "phy_name":"clk2" }, "arrive":7.129, "delay":0.435 }, { "type":"site_delay", "pin0": { "log_name":"", "phy_name":"" }, "pin1": { "log_name":"", "phy_name":"" }, "arrive":7.129, "delay":0.000 } ] } Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- -------------- ---------------- --------- --------------------- ------ CONSTRAINT 0.000 5.000 1 Clk top CLOCK LATENCY 0.000 5.000 1 Clk NET DELAY 0.000 5.000 1 Clk_pad.bb_inst/B->Clk_pad.bb_inst/O SEIO33_CORE PADI_DEL 1.259 6.259 3 Clk_c NET DELAY 0.435 6.694 3 MyDCC/CLKI->MyDCC/CLKO DCC DCC_DEL 0.000 6.694 13 clk2 NET DELAY 0.435 7.129 13 CNT2_d_i7.ff_inst/CLK CLOCK PIN 0.000 7.129 1 Uncertainty -(0.000) 7.129 Common Path Skew 0.000 7.129 Setup time -(-0.035) 7.164 ---------------------------------------- -------------- ---------------- --------- --------------------- ------ Required Time 7.164 Arrival Time -(2.978) ---------------------------------------- -------------- ---------------- --------- --------------------- ------ Path Slack (Passed) 4.186 ++++ Path 5 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Path Begin : CNT2_e3_e3_e3_20__i1.ff_inst/Q (SLICE) Path End : CNT2_d_i2.ff_inst/DF (SLICE) Source Clock : CLK2 (R) Destination Clock: CLK2 (F) Logic Level : 1 Delay Ratio : 58.9% (route), 41.1% (logic) Clock Skew : -0.107 ns Setup Constraint : 5.000 ns Common Path Skew : 0.000 ns Path Slack : 4.189 ns (Passed) Source Clock Path { "path_begin": { "type":"port", "log_name":"Clk", "phy_name":"Clk" }, "path_end": { "type":"pin", "log_name":"CNT2_e3_e3_e3_20__i1.ff_inst/CLK", "phy_name":"SLICE_2/CLK" }, "path_sections":[ { "type":"net_delay", "net": { "log_name":"Clk", "phy_name":"Clk" }, "arrive":0.000, "delay":0.000 }, { "type":"site_delay", "pin0": { "log_name":"Clk_pad.bb_inst/B", "phy_name":"Clk_pad.bb_inst/IOPAD" }, "pin1": { "log_name":"Clk_pad.bb_inst/O", "phy_name":"Clk_pad.bb_inst/PADDI" }, "arrive":1.366, "delay":1.366 }, { "type":"net_delay", "net": { "log_name":"Clk_c", "phy_name":"Clk_c" }, "arrive":1.801, "delay":0.435 }, { "type":"site_delay", "pin0": { "log_name":"MyDCC/CLKI", "phy_name":"MyDCC/CLKI" }, "pin1": { "log_name":"MyDCC/CLKO", "phy_name":"MyDCC/CLKO" }, "arrive":1.801, "delay":0.000 }, { "type":"net_delay", "net": { "log_name":"clk2", "phy_name":"clk2" }, "arrive":2.236, "delay":0.435 }, { "type":"site_delay", "pin0": { "log_name":"", "phy_name":"" }, "pin1": { "log_name":"", "phy_name":"" }, "arrive":2.236, "delay":0.000 } ] } Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- -------------- ---------------- --------- --------------------- ------ Clk top CLOCK LATENCY 0.000 0.000 1 Clk NET DELAY 0.000 0.000 1 Clk_pad.bb_inst/B->Clk_pad.bb_inst/O SEIO33_CORE PADI_DEL 1.366 1.366 3 Clk_c NET DELAY 0.435 1.801 3 MyDCC/CLKI->MyDCC/CLKO DCC DCC_DEL 0.000 1.801 13 clk2 NET DELAY 0.435 2.236 13 {CNT2_e3_e3_e3_20__i1.ff_inst/CLK CNT2_e3_e3_e3_20__i2.ff_inst/CLK} CLOCK PIN 0.000 2.236 1 Data Path { "path_begin": { "type":"pin", "log_name":"CNT2_e3_e3_e3_20__i1.ff_inst/Q", "phy_name":"SLICE_2/Q0" }, "path_end": { "type":"pin", "log_name":"CNT2_d_i2.ff_inst/DF", "phy_name":"CNT2_d_i2.SLICE_13/M0" }, "path_sections":[ { "type":"site_delay", "pin0": { "log_name":"CNT2_e3_e3_e3_20__i1.ff_inst/CLK", "phy_name":"SLICE_2/CLK" }, "pin1": { "log_name":"CNT2_e3_e3_e3_20__i1.ff_inst/Q", "phy_name":"SLICE_2/Q0" }, "arrive":2.540, "delay":0.304 }, { "type":"net_delay", "net": { "log_name":"CNT2[1]", "phy_name":"CNT2[1]" }, "arrive":2.975, "delay":0.435 }, { "type":"site_delay", "pin0": { "log_name":"", "phy_name":"" }, "pin1": { "log_name":"", "phy_name":"" }, "arrive":2.975, "delay":0.000 } ] } Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- -------------- ---------------- --------- --------------------- ------ CNT2_e3_e3_e3_20__i1.ff_inst/CLK->CNT2_e3_e3_e3_20__i1.ff_inst/Q SLICE REG_DEL 0.304 2.540 2 CNT2[1] NET DELAY 0.435 2.975 2 CNT2_d_i2.ff_inst/DF ENDPOINT 0.000 2.975 1 Destination Clock Path { "path_begin": { "type":"port", "log_name":"Clk", "phy_name":"Clk" }, "path_end": { "type":"pin", "log_name":"CNT2_d_i2.ff_inst/CLK", "phy_name":"CNT2_d_i2.SLICE_13/CLK" }, "path_sections":[ { "type":"site_delay", "pin0": { "log_name":"", "phy_name":"" }, "pin1": { "log_name":"", "phy_name":"" }, "arrive":5.000, "delay":0.000 }, { "type":"net_delay", "net": { "log_name":"Clk", "phy_name":"Clk" }, "arrive":5.000, "delay":0.000 }, { "type":"site_delay", "pin0": { "log_name":"Clk_pad.bb_inst/B", "phy_name":"Clk_pad.bb_inst/IOPAD" }, "pin1": { "log_name":"Clk_pad.bb_inst/O", "phy_name":"Clk_pad.bb_inst/PADDI" }, "arrive":6.259, "delay":1.259 }, { "type":"net_delay", "net": { "log_name":"Clk_c", "phy_name":"Clk_c" }, "arrive":6.694, "delay":0.435 }, { "type":"site_delay", "pin0": { "log_name":"MyDCC/CLKI", "phy_name":"MyDCC/CLKI" }, "pin1": { "log_name":"MyDCC/CLKO", "phy_name":"MyDCC/CLKO" }, "arrive":6.694, "delay":0.000 }, { "type":"net_delay", "net": { "log_name":"clk2", "phy_name":"clk2" }, "arrive":7.129, "delay":0.435 }, { "type":"site_delay", "pin0": { "log_name":"", "phy_name":"" }, "pin1": { "log_name":"", "phy_name":"" }, "arrive":7.129, "delay":0.000 } ] } Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- -------------- ---------------- --------- --------------------- ------ CONSTRAINT 0.000 5.000 1 Clk top CLOCK LATENCY 0.000 5.000 1 Clk NET DELAY 0.000 5.000 1 Clk_pad.bb_inst/B->Clk_pad.bb_inst/O SEIO33_CORE PADI_DEL 1.259 6.259 3 Clk_c NET DELAY 0.435 6.694 3 MyDCC/CLKI->MyDCC/CLKO DCC DCC_DEL 0.000 6.694 13 clk2 NET DELAY 0.435 7.129 13 CNT2_d_i2.ff_inst/CLK CLOCK PIN 0.000 7.129 1 Uncertainty -(0.000) 7.129 Common Path Skew 0.000 7.129 Setup time -(-0.035) 7.164 ---------------------------------------- -------------- ---------------- --------- --------------------- ------ Required Time 7.164 Arrival Time -(2.975) ---------------------------------------- -------------- ---------------- --------- --------------------- ------ Path Slack (Passed) 4.189 ++++ Path 6 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Path Begin : CNT2_e3_e3_e3_20__i3.ff_inst/Q (SLICE) Path End : CNT2_d_i4.ff_inst/DF (SLICE) Source Clock : CLK2 (R) Destination Clock: CLK2 (F) Logic Level : 1 Delay Ratio : 58.9% (route), 41.1% (logic) Clock Skew : -0.107 ns Setup Constraint : 5.000 ns Common Path Skew : 0.000 ns Path Slack : 4.189 ns (Passed) Source Clock Path { "path_begin": { "type":"port", "log_name":"Clk", "phy_name":"Clk" }, "path_end": { "type":"pin", "log_name":"CNT2_e3_e3_e3_20__i3.ff_inst/CLK", "phy_name":"SLICE_0/CLK" }, "path_sections":[ { "type":"net_delay", "net": { "log_name":"Clk", "phy_name":"Clk" }, "arrive":0.000, "delay":0.000 }, { "type":"site_delay", "pin0": { "log_name":"Clk_pad.bb_inst/B", "phy_name":"Clk_pad.bb_inst/IOPAD" }, "pin1": { "log_name":"Clk_pad.bb_inst/O", "phy_name":"Clk_pad.bb_inst/PADDI" }, "arrive":1.366, "delay":1.366 }, { "type":"net_delay", "net": { "log_name":"Clk_c", "phy_name":"Clk_c" }, "arrive":1.801, "delay":0.435 }, { "type":"site_delay", "pin0": { "log_name":"MyDCC/CLKI", "phy_name":"MyDCC/CLKI" }, "pin1": { "log_name":"MyDCC/CLKO", "phy_name":"MyDCC/CLKO" }, "arrive":1.801, "delay":0.000 }, { "type":"net_delay", "net": { "log_name":"clk2", "phy_name":"clk2" }, "arrive":2.236, "delay":0.435 }, { "type":"site_delay", "pin0": { "log_name":"", "phy_name":"" }, "pin1": { "log_name":"", "phy_name":"" }, "arrive":2.236, "delay":0.000 } ] } Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- -------------- ---------------- --------- --------------------- ------ Clk top CLOCK LATENCY 0.000 0.000 1 Clk NET DELAY 0.000 0.000 1 Clk_pad.bb_inst/B->Clk_pad.bb_inst/O SEIO33_CORE PADI_DEL 1.366 1.366 3 Clk_c NET DELAY 0.435 1.801 3 MyDCC/CLKI->MyDCC/CLKO DCC DCC_DEL 0.000 1.801 13 clk2 NET DELAY 0.435 2.236 13 {CNT2_e3_e3_e3_20__i3.ff_inst/CLK CNT2_e3_e3_e3_20__i4.ff_inst/CLK} CLOCK PIN 0.000 2.236 1 Data Path { "path_begin": { "type":"pin", "log_name":"CNT2_e3_e3_e3_20__i3.ff_inst/Q", "phy_name":"SLICE_0/Q0" }, "path_end": { "type":"pin", "log_name":"CNT2_d_i4.ff_inst/DF", "phy_name":"CNT2_d_i4.SLICE_11/M0" }, "path_sections":[ { "type":"site_delay", "pin0": { "log_name":"CNT2_e3_e3_e3_20__i3.ff_inst/CLK", "phy_name":"SLICE_0/CLK" }, "pin1": { "log_name":"CNT2_e3_e3_e3_20__i3.ff_inst/Q", "phy_name":"SLICE_0/Q0" }, "arrive":2.540, "delay":0.304 }, { "type":"net_delay", "net": { "log_name":"CNT2[3]", "phy_name":"CNT2[3]" }, "arrive":2.975, "delay":0.435 }, { "type":"site_delay", "pin0": { "log_name":"", "phy_name":"" }, "pin1": { "log_name":"", "phy_name":"" }, "arrive":2.975, "delay":0.000 } ] } Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- -------------- ---------------- --------- --------------------- ------ CNT2_e3_e3_e3_20__i3.ff_inst/CLK->CNT2_e3_e3_e3_20__i3.ff_inst/Q SLICE REG_DEL 0.304 2.540 2 CNT2[3] NET DELAY 0.435 2.975 2 CNT2_d_i4.ff_inst/DF ENDPOINT 0.000 2.975 1 Destination Clock Path { "path_begin": { "type":"port", "log_name":"Clk", "phy_name":"Clk" }, "path_end": { "type":"pin", "log_name":"CNT2_d_i4.ff_inst/CLK", "phy_name":"CNT2_d_i4.SLICE_11/CLK" }, "path_sections":[ { "type":"site_delay", "pin0": { "log_name":"", "phy_name":"" }, "pin1": { "log_name":"", "phy_name":"" }, "arrive":5.000, "delay":0.000 }, { "type":"net_delay", "net": { "log_name":"Clk", "phy_name":"Clk" }, "arrive":5.000, "delay":0.000 }, { "type":"site_delay", "pin0": { "log_name":"Clk_pad.bb_inst/B", "phy_name":"Clk_pad.bb_inst/IOPAD" }, "pin1": { "log_name":"Clk_pad.bb_inst/O", "phy_name":"Clk_pad.bb_inst/PADDI" }, "arrive":6.259, "delay":1.259 }, { "type":"net_delay", "net": { "log_name":"Clk_c", "phy_name":"Clk_c" }, "arrive":6.694, "delay":0.435 }, { "type":"site_delay", "pin0": { "log_name":"MyDCC/CLKI", "phy_name":"MyDCC/CLKI" }, "pin1": { "log_name":"MyDCC/CLKO", "phy_name":"MyDCC/CLKO" }, "arrive":6.694, "delay":0.000 }, { "type":"net_delay", "net": { "log_name":"clk2", "phy_name":"clk2" }, "arrive":7.129, "delay":0.435 }, { "type":"site_delay", "pin0": { "log_name":"", "phy_name":"" }, "pin1": { "log_name":"", "phy_name":"" }, "arrive":7.129, "delay":0.000 } ] } Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- -------------- ---------------- --------- --------------------- ------ CONSTRAINT 0.000 5.000 1 Clk top CLOCK LATENCY 0.000 5.000 1 Clk NET DELAY 0.000 5.000 1 Clk_pad.bb_inst/B->Clk_pad.bb_inst/O SEIO33_CORE PADI_DEL 1.259 6.259 3 Clk_c NET DELAY 0.435 6.694 3 MyDCC/CLKI->MyDCC/CLKO DCC DCC_DEL 0.000 6.694 13 clk2 NET DELAY 0.435 7.129 13 CNT2_d_i4.ff_inst/CLK CLOCK PIN 0.000 7.129 1 Uncertainty -(0.000) 7.129 Common Path Skew 0.000 7.129 Setup time -(-0.035) 7.164 ---------------------------------------- -------------- ---------------- --------- --------------------- ------ Required Time 7.164 Arrival Time -(2.975) ---------------------------------------- -------------- ---------------- --------- --------------------- ------ Path Slack (Passed) 4.189 ++++ Path 7 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Path Begin : CNT2_e3_e3_e3_20__i5.ff_inst/Q (SLICE) Path End : CNT2_d_i6.ff_inst/DF (SLICE) Source Clock : CLK2 (R) Destination Clock: CLK2 (F) Logic Level : 1 Delay Ratio : 58.9% (route), 41.1% (logic) Clock Skew : -0.107 ns Setup Constraint : 5.000 ns Common Path Skew : 0.000 ns Path Slack : 4.189 ns (Passed) Source Clock Path { "path_begin": { "type":"port", "log_name":"Clk", "phy_name":"Clk" }, "path_end": { "type":"pin", "log_name":"CNT2_e3_e3_e3_20__i5.ff_inst/CLK", "phy_name":"SLICE_3/CLK" }, "path_sections":[ { "type":"net_delay", "net": { "log_name":"Clk", "phy_name":"Clk" }, "arrive":0.000, "delay":0.000 }, { "type":"site_delay", "pin0": { "log_name":"Clk_pad.bb_inst/B", "phy_name":"Clk_pad.bb_inst/IOPAD" }, "pin1": { "log_name":"Clk_pad.bb_inst/O", "phy_name":"Clk_pad.bb_inst/PADDI" }, "arrive":1.366, "delay":1.366 }, { "type":"net_delay", "net": { "log_name":"Clk_c", "phy_name":"Clk_c" }, "arrive":1.801, "delay":0.435 }, { "type":"site_delay", "pin0": { "log_name":"MyDCC/CLKI", "phy_name":"MyDCC/CLKI" }, "pin1": { "log_name":"MyDCC/CLKO", "phy_name":"MyDCC/CLKO" }, "arrive":1.801, "delay":0.000 }, { "type":"net_delay", "net": { "log_name":"clk2", "phy_name":"clk2" }, "arrive":2.236, "delay":0.435 }, { "type":"site_delay", "pin0": { "log_name":"", "phy_name":"" }, "pin1": { "log_name":"", "phy_name":"" }, "arrive":2.236, "delay":0.000 } ] } Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- -------------- ---------------- --------- --------------------- ------ Clk top CLOCK LATENCY 0.000 0.000 1 Clk NET DELAY 0.000 0.000 1 Clk_pad.bb_inst/B->Clk_pad.bb_inst/O SEIO33_CORE PADI_DEL 1.366 1.366 3 Clk_c NET DELAY 0.435 1.801 3 MyDCC/CLKI->MyDCC/CLKO DCC DCC_DEL 0.000 1.801 13 clk2 NET DELAY 0.435 2.236 13 {CNT2_e3_e3_e3_20__i5.ff_inst/CLK CNT2_e3_e3_e3_20__i6.ff_inst/CLK} CLOCK PIN 0.000 2.236 1 Data Path { "path_begin": { "type":"pin", "log_name":"CNT2_e3_e3_e3_20__i5.ff_inst/Q", "phy_name":"SLICE_3/Q0" }, "path_end": { "type":"pin", "log_name":"CNT2_d_i6.ff_inst/DF", "phy_name":"CNT2_d_i6.SLICE_9/M0" }, "path_sections":[ { "type":"site_delay", "pin0": { "log_name":"CNT2_e3_e3_e3_20__i5.ff_inst/CLK", "phy_name":"SLICE_3/CLK" }, "pin1": { "log_name":"CNT2_e3_e3_e3_20__i5.ff_inst/Q", "phy_name":"SLICE_3/Q0" }, "arrive":2.540, "delay":0.304 }, { "type":"net_delay", "net": { "log_name":"CNT2[5]", "phy_name":"CNT2[5]" }, "arrive":2.975, "delay":0.435 }, { "type":"site_delay", "pin0": { "log_name":"", "phy_name":"" }, "pin1": { "log_name":"", "phy_name":"" }, "arrive":2.975, "delay":0.000 } ] } Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- -------------- ---------------- --------- --------------------- ------ CNT2_e3_e3_e3_20__i5.ff_inst/CLK->CNT2_e3_e3_e3_20__i5.ff_inst/Q SLICE REG_DEL 0.304 2.540 2 CNT2[5] NET DELAY 0.435 2.975 2 CNT2_d_i6.ff_inst/DF ENDPOINT 0.000 2.975 1 Destination Clock Path { "path_begin": { "type":"port", "log_name":"Clk", "phy_name":"Clk" }, "path_end": { "type":"pin", "log_name":"CNT2_d_i6.ff_inst/CLK", "phy_name":"CNT2_d_i6.SLICE_9/CLK" }, "path_sections":[ { "type":"site_delay", "pin0": { "log_name":"", "phy_name":"" }, "pin1": { "log_name":"", "phy_name":"" }, "arrive":5.000, "delay":0.000 }, { "type":"net_delay", "net": { "log_name":"Clk", "phy_name":"Clk" }, "arrive":5.000, "delay":0.000 }, { "type":"site_delay", "pin0": { "log_name":"Clk_pad.bb_inst/B", "phy_name":"Clk_pad.bb_inst/IOPAD" }, "pin1": { "log_name":"Clk_pad.bb_inst/O", "phy_name":"Clk_pad.bb_inst/PADDI" }, "arrive":6.259, "delay":1.259 }, { "type":"net_delay", "net": { "log_name":"Clk_c", "phy_name":"Clk_c" }, "arrive":6.694, "delay":0.435 }, { "type":"site_delay", "pin0": { "log_name":"MyDCC/CLKI", "phy_name":"MyDCC/CLKI" }, "pin1": { "log_name":"MyDCC/CLKO", "phy_name":"MyDCC/CLKO" }, "arrive":6.694, "delay":0.000 }, { "type":"net_delay", "net": { "log_name":"clk2", "phy_name":"clk2" }, "arrive":7.129, "delay":0.435 }, { "type":"site_delay", "pin0": { "log_name":"", "phy_name":"" }, "pin1": { "log_name":"", "phy_name":"" }, "arrive":7.129, "delay":0.000 } ] } Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- -------------- ---------------- --------- --------------------- ------ CONSTRAINT 0.000 5.000 1 Clk top CLOCK LATENCY 0.000 5.000 1 Clk NET DELAY 0.000 5.000 1 Clk_pad.bb_inst/B->Clk_pad.bb_inst/O SEIO33_CORE PADI_DEL 1.259 6.259 3 Clk_c NET DELAY 0.435 6.694 3 MyDCC/CLKI->MyDCC/CLKO DCC DCC_DEL 0.000 6.694 13 clk2 NET DELAY 0.435 7.129 13 CNT2_d_i6.ff_inst/CLK CLOCK PIN 0.000 7.129 1 Uncertainty -(0.000) 7.129 Common Path Skew 0.000 7.129 Setup time -(-0.035) 7.164 ---------------------------------------- -------------- ---------------- --------- --------------------- ------ Required Time 7.164 Arrival Time -(2.975) ---------------------------------------- -------------- ---------------- --------- --------------------- ------ Path Slack (Passed) 4.189 ++++ Path 8 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Path Begin : CNT2_e3_e3_e3_20__i7.ff_inst/Q (SLICE) Path End : CNT2_d_i8.ff_inst/DF (SLICE) Source Clock : CLK2 (R) Destination Clock: CLK2 (F) Logic Level : 1 Delay Ratio : 58.9% (route), 41.1% (logic) Clock Skew : -0.107 ns Setup Constraint : 5.000 ns Common Path Skew : 0.000 ns Path Slack : 4.189 ns (Passed) Source Clock Path { "path_begin": { "type":"port", "log_name":"Clk", "phy_name":"Clk" }, "path_end": { "type":"pin", "log_name":"CNT2_e3_e3_e3_20__i7.ff_inst/CLK", "phy_name":"SLICE_4/CLK" }, "path_sections":[ { "type":"net_delay", "net": { "log_name":"Clk", "phy_name":"Clk" }, "arrive":0.000, "delay":0.000 }, { "type":"site_delay", "pin0": { "log_name":"Clk_pad.bb_inst/B", "phy_name":"Clk_pad.bb_inst/IOPAD" }, "pin1": { "log_name":"Clk_pad.bb_inst/O", "phy_name":"Clk_pad.bb_inst/PADDI" }, "arrive":1.366, "delay":1.366 }, { "type":"net_delay", "net": { "log_name":"Clk_c", "phy_name":"Clk_c" }, "arrive":1.801, "delay":0.435 }, { "type":"site_delay", "pin0": { "log_name":"MyDCC/CLKI", "phy_name":"MyDCC/CLKI" }, "pin1": { "log_name":"MyDCC/CLKO", "phy_name":"MyDCC/CLKO" }, "arrive":1.801, "delay":0.000 }, { "type":"net_delay", "net": { "log_name":"clk2", "phy_name":"clk2" }, "arrive":2.236, "delay":0.435 }, { "type":"site_delay", "pin0": { "log_name":"", "phy_name":"" }, "pin1": { "log_name":"", "phy_name":"" }, "arrive":2.236, "delay":0.000 } ] } Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- -------------- ---------------- --------- --------------------- ------ Clk top CLOCK LATENCY 0.000 0.000 1 Clk NET DELAY 0.000 0.000 1 Clk_pad.bb_inst/B->Clk_pad.bb_inst/O SEIO33_CORE PADI_DEL 1.366 1.366 3 Clk_c NET DELAY 0.435 1.801 3 MyDCC/CLKI->MyDCC/CLKO DCC DCC_DEL 0.000 1.801 13 clk2 NET DELAY 0.435 2.236 13 CNT2_e3_e3_e3_20__i7.ff_inst/CLK CLOCK PIN 0.000 2.236 1 Data Path { "path_begin": { "type":"pin", "log_name":"CNT2_e3_e3_e3_20__i7.ff_inst/Q", "phy_name":"SLICE_4/Q0" }, "path_end": { "type":"pin", "log_name":"CNT2_d_i8.ff_inst/DF", "phy_name":"CNT2_d_i8.SLICE_6/M0" }, "path_sections":[ { "type":"site_delay", "pin0": { "log_name":"CNT2_e3_e3_e3_20__i7.ff_inst/CLK", "phy_name":"SLICE_4/CLK" }, "pin1": { "log_name":"CNT2_e3_e3_e3_20__i7.ff_inst/Q", "phy_name":"SLICE_4/Q0" }, "arrive":2.540, "delay":0.304 }, { "type":"net_delay", "net": { "log_name":"CNT2[7]", "phy_name":"CNT2[7]" }, "arrive":2.975, "delay":0.435 }, { "type":"site_delay", "pin0": { "log_name":"", "phy_name":"" }, "pin1": { "log_name":"", "phy_name":"" }, "arrive":2.975, "delay":0.000 } ] } Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- -------------- ---------------- --------- --------------------- ------ CNT2_e3_e3_e3_20__i7.ff_inst/CLK->CNT2_e3_e3_e3_20__i7.ff_inst/Q SLICE REG_DEL 0.304 2.540 2 CNT2[7] NET DELAY 0.435 2.975 2 CNT2_d_i8.ff_inst/DF ENDPOINT 0.000 2.975 1 Destination Clock Path { "path_begin": { "type":"port", "log_name":"Clk", "phy_name":"Clk" }, "path_end": { "type":"pin", "log_name":"CNT2_d_i8.ff_inst/CLK", "phy_name":"CNT2_d_i8.SLICE_6/CLK" }, "path_sections":[ { "type":"site_delay", "pin0": { "log_name":"", "phy_name":"" }, "pin1": { "log_name":"", "phy_name":"" }, "arrive":5.000, "delay":0.000 }, { "type":"net_delay", "net": { "log_name":"Clk", "phy_name":"Clk" }, "arrive":5.000, "delay":0.000 }, { "type":"site_delay", "pin0": { "log_name":"Clk_pad.bb_inst/B", "phy_name":"Clk_pad.bb_inst/IOPAD" }, "pin1": { "log_name":"Clk_pad.bb_inst/O", "phy_name":"Clk_pad.bb_inst/PADDI" }, "arrive":6.259, "delay":1.259 }, { "type":"net_delay", "net": { "log_name":"Clk_c", "phy_name":"Clk_c" }, "arrive":6.694, "delay":0.435 }, { "type":"site_delay", "pin0": { "log_name":"MyDCC/CLKI", "phy_name":"MyDCC/CLKI" }, "pin1": { "log_name":"MyDCC/CLKO", "phy_name":"MyDCC/CLKO" }, "arrive":6.694, "delay":0.000 }, { "type":"net_delay", "net": { "log_name":"clk2", "phy_name":"clk2" }, "arrive":7.129, "delay":0.435 }, { "type":"site_delay", "pin0": { "log_name":"", "phy_name":"" }, "pin1": { "log_name":"", "phy_name":"" }, "arrive":7.129, "delay":0.000 } ] } Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- -------------- ---------------- --------- --------------------- ------ CONSTRAINT 0.000 5.000 1 Clk top CLOCK LATENCY 0.000 5.000 1 Clk NET DELAY 0.000 5.000 1 Clk_pad.bb_inst/B->Clk_pad.bb_inst/O SEIO33_CORE PADI_DEL 1.259 6.259 3 Clk_c NET DELAY 0.435 6.694 3 MyDCC/CLKI->MyDCC/CLKO DCC DCC_DEL 0.000 6.694 13 clk2 NET DELAY 0.435 7.129 13 CNT2_d_i8.ff_inst/CLK CLOCK PIN 0.000 7.129 1 Uncertainty -(0.000) 7.129 Common Path Skew 0.000 7.129 Setup time -(-0.035) 7.164 ---------------------------------------- -------------- ---------------- --------- --------------------- ------ Required Time 7.164 Arrival Time -(2.975) ---------------------------------------- -------------- ---------------- --------- --------------------- ------ Path Slack (Passed) 4.189 ++++ Path 9 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Path Begin : CNT1_e3_e3_e3_21__i0.ff_inst/Q (SLICE) Path End : MyDCC/CE (DCC) Source Clock : CLK1 (R) Destination Clock: CLK1 (R) Logic Level : 2 Delay Ratio : 62.7% (route), 37.3% (logic) Clock Skew : 0.000 ns Setup Constraint : 10.000 ns Common Path Skew : 0.000 ns Path Slack : 8.613 ns (Passed) Source Clock Path { "path_begin": { "type":"port", "log_name":"Clk", "phy_name":"Clk" }, "path_end": { "type":"pin", "log_name":"CNT1_e3_e3_e3_21__i0.ff_inst/CLK", "phy_name":"SLICE_8/CLK" }, "path_sections":[ { "type":"net_delay", "net": { "log_name":"Clk", "phy_name":"Clk" }, "arrive":0.000, "delay":0.000 }, { "type":"site_delay", "pin0": { "log_name":"Clk_pad.bb_inst/B", "phy_name":"Clk_pad.bb_inst/IOPAD" }, "pin1": { "log_name":"Clk_pad.bb_inst/O", "phy_name":"Clk_pad.bb_inst/PADDI" }, "arrive":1.366, "delay":1.366 }, { "type":"net_delay", "net": { "log_name":"Clk_c", "phy_name":"Clk_c" }, "arrive":1.801, "delay":0.435 }, { "type":"site_delay", "pin0": { "log_name":"", "phy_name":"" }, "pin1": { "log_name":"", "phy_name":"" }, "arrive":1.801, "delay":0.000 } ] } Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- -------------- ---------------- -------- --------------------- ------ Clk top CLOCK LATENCY 0.000 0.000 1 Clk NET DELAY 0.000 0.000 1 Clk_pad.bb_inst/B->Clk_pad.bb_inst/O SEIO33_CORE PADI_DEL 1.366 1.366 3 Clk_c NET DELAY 0.435 1.801 3 CNT1_e3_e3_e3_21__i0.ff_inst/CLK CLOCK PIN 0.000 1.801 1 Data Path { "path_begin": { "type":"pin", "log_name":"CNT1_e3_e3_e3_21__i0.ff_inst/Q", "phy_name":"SLICE_8/Q0" }, "path_end": { "type":"pin", "log_name":"MyDCC/CE", "phy_name":"MyDCC/CE" }, "path_sections":[ { "type":"site_delay", "pin0": { "log_name":"CNT1_e3_e3_e3_21__i0.ff_inst/CLK", "phy_name":"SLICE_8/CLK" }, "pin1": { "log_name":"CNT1_e3_e3_e3_21__i0.ff_inst/Q", "phy_name":"SLICE_8/Q0" }, "arrive":2.105, "delay":0.304 }, { "type":"net_delay", "net": { "log_name":"CNT1[0]", "phy_name":"CNT1[0]" }, "arrive":2.540, "delay":0.435 }, { "type":"site_delay", "pin0": { "log_name":"i25_2_lut/A", "phy_name":"SLICE_15/A0" }, "pin1": { "log_name":"i25_2_lut/Z", "phy_name":"SLICE_15/F0" }, "arrive":2.753, "delay":0.213 }, { "type":"net_delay", "net": { "log_name":"Enable", "phy_name":"Enable" }, "arrive":3.188, "delay":0.435 }, { "type":"site_delay", "pin0": { "log_name":"", "phy_name":"" }, "pin1": { "log_name":"", "phy_name":"" }, "arrive":3.188, "delay":0.000 } ] } Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- -------------- ---------------- -------- --------------------- ------ CNT1_e3_e3_e3_21__i0.ff_inst/CLK->CNT1_e3_e3_e3_21__i0.ff_inst/Q SLICE REG_DEL 0.304 2.105 3 CNT1[0] NET DELAY 0.435 2.540 3 i25_2_lut/A->i25_2_lut/Z SLICE CTOF_DEL 0.213 2.753 1 Enable NET DELAY 0.435 3.188 1 MyDCC/CE ENDPOINT 0.000 3.188 1 Destination Clock Path { "path_begin": { "type":"port", "log_name":"Clk", "phy_name":"Clk" }, "path_end": { "type":"pin", "log_name":"MyDCC/CLKI", "phy_name":"MyDCC/CLKI" }, "path_sections":[ { "type":"site_delay", "pin0": { "log_name":"", "phy_name":"" }, "pin1": { "log_name":"", "phy_name":"" }, "arrive":10.000, "delay":0.000 }, { "type":"net_delay", "net": { "log_name":"Clk", "phy_name":"Clk" }, "arrive":10.000, "delay":0.000 }, { "type":"site_delay", "pin0": { "log_name":"Clk_pad.bb_inst/B", "phy_name":"Clk_pad.bb_inst/IOPAD" }, "pin1": { "log_name":"Clk_pad.bb_inst/O", "phy_name":"Clk_pad.bb_inst/PADDI" }, "arrive":11.366, "delay":1.366 }, { "type":"net_delay", "net": { "log_name":"Clk_c", "phy_name":"Clk_c" }, "arrive":11.801, "delay":0.435 }, { "type":"site_delay", "pin0": { "log_name":"", "phy_name":"" }, "pin1": { "log_name":"", "phy_name":"" }, "arrive":11.801, "delay":0.000 } ] } Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- -------------- ---------------- -------- --------------------- ------ CONSTRAINT 0.000 10.000 1 Clk top CLOCK LATENCY 0.000 10.000 1 Clk NET DELAY 0.000 10.000 1 Clk_pad.bb_inst/B->Clk_pad.bb_inst/O SEIO33_CORE PADI_DEL 1.366 11.366 3 Clk_c NET DELAY 0.435 11.801 3 MyDCC/CLKI CLOCK PIN 0.000 11.801 1 Uncertainty -(0.000) 11.801 Common Path Skew 0.000 11.801 Setup time -(0.000) 11.801 ---------------------------------------- -------------- ---------------- -------- --------------------- ------ Required Time 11.801 Arrival Time -(3.188) ---------------------------------------- -------------- ---------------- -------- --------------------- ------ Path Slack (Passed) 8.613 ++++ Path 10 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Path Begin : CNT1_e3_e3_e3_21__i0.ff_inst/Q (SLICE) Path End : CNT1_e3_e3_e3_21__i1.ff_inst/DF (SLICE) Source Clock : CLK1 (R) Destination Clock: CLK1 (R) Logic Level : 2 Delay Ratio : 45.7% (route), 54.3% (logic) Clock Skew : 0.000 ns Setup Constraint : 10.000 ns Common Path Skew : 0.000 ns Path Slack : 9.106 ns (Passed) Source Clock Path { "path_begin": { "type":"port", "log_name":"Clk", "phy_name":"Clk" }, "path_end": { "type":"pin", "log_name":"CNT1_e3_e3_e3_21__i0.ff_inst/CLK", "phy_name":"SLICE_8/CLK" }, "path_sections":[ { "type":"net_delay", "net": { "log_name":"Clk", "phy_name":"Clk" }, "arrive":0.000, "delay":0.000 }, { "type":"site_delay", "pin0": { "log_name":"Clk_pad.bb_inst/B", "phy_name":"Clk_pad.bb_inst/IOPAD" }, "pin1": { "log_name":"Clk_pad.bb_inst/O", "phy_name":"Clk_pad.bb_inst/PADDI" }, "arrive":1.366, "delay":1.366 }, { "type":"net_delay", "net": { "log_name":"Clk_c", "phy_name":"Clk_c" }, "arrive":1.801, "delay":0.435 }, { "type":"site_delay", "pin0": { "log_name":"", "phy_name":"" }, "pin1": { "log_name":"", "phy_name":"" }, "arrive":1.801, "delay":0.000 } ] } Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- -------------- ---------------- --------- --------------------- ------ Clk top CLOCK LATENCY 0.000 0.000 1 Clk NET DELAY 0.000 0.000 1 Clk_pad.bb_inst/B->Clk_pad.bb_inst/O SEIO33_CORE PADI_DEL 1.366 1.366 3 Clk_c NET DELAY 0.435 1.801 3 CNT1_e3_e3_e3_21__i0.ff_inst/CLK CLOCK PIN 0.000 1.801 1 Data Path { "path_begin": { "type":"pin", "log_name":"CNT1_e3_e3_e3_21__i0.ff_inst/Q", "phy_name":"SLICE_8/Q0" }, "path_end": { "type":"pin", "log_name":"CNT1_e3_e3_e3_21__i1.ff_inst/DF", "phy_name":"SLICE_5/DI0" }, "path_sections":[ { "type":"site_delay", "pin0": { "log_name":"CNT1_e3_e3_e3_21__i0.ff_inst/CLK", "phy_name":"SLICE_8/CLK" }, "pin1": { "log_name":"CNT1_e3_e3_e3_21__i0.ff_inst/Q", "phy_name":"SLICE_8/Q0" }, "arrive":2.105, "delay":0.304 }, { "type":"net_delay", "net": { "log_name":"CNT1[0]", "phy_name":"CNT1[0]" }, "arrive":2.540, "delay":0.435 }, { "type":"site_delay", "pin0": { "log_name":"i36_2_lut/B", "phy_name":"SLICE_5/B0" }, "pin1": { "log_name":"i36_2_lut/Z", "phy_name":"SLICE_5/F0" }, "arrive":2.753, "delay":0.213 }, { "type":"net_delay", "net": { "log_name":"n14", "phy_name":"n14" }, "arrive":2.753, "delay":0.000 }, { "type":"site_delay", "pin0": { "log_name":"", "phy_name":"" }, "pin1": { "log_name":"", "phy_name":"" }, "arrive":2.753, "delay":0.000 } ] } Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- -------------- ---------------- --------- --------------------- ------ CNT1_e3_e3_e3_21__i0.ff_inst/CLK->CNT1_e3_e3_e3_21__i0.ff_inst/Q SLICE REG_DEL 0.304 2.105 3 CNT1[0] NET DELAY 0.435 2.540 3 i36_2_lut/B->i36_2_lut/Z SLICE CTOF_DEL 0.213 2.753 1 n14 NET DELAY 0.000 2.753 1 CNT1_e3_e3_e3_21__i1.ff_inst/DF ENDPOINT 0.000 2.753 1 Destination Clock Path { "path_begin": { "type":"port", "log_name":"Clk", "phy_name":"Clk" }, "path_end": { "type":"pin", "log_name":"CNT1_e3_e3_e3_21__i1.ff_inst/CLK", "phy_name":"SLICE_5/CLK" }, "path_sections":[ { "type":"site_delay", "pin0": { "log_name":"", "phy_name":"" }, "pin1": { "log_name":"", "phy_name":"" }, "arrive":10.000, "delay":0.000 }, { "type":"net_delay", "net": { "log_name":"Clk", "phy_name":"Clk" }, "arrive":10.000, "delay":0.000 }, { "type":"site_delay", "pin0": { "log_name":"Clk_pad.bb_inst/B", "phy_name":"Clk_pad.bb_inst/IOPAD" }, "pin1": { "log_name":"Clk_pad.bb_inst/O", "phy_name":"Clk_pad.bb_inst/PADDI" }, "arrive":11.366, "delay":1.366 }, { "type":"net_delay", "net": { "log_name":"Clk_c", "phy_name":"Clk_c" }, "arrive":11.801, "delay":0.435 }, { "type":"site_delay", "pin0": { "log_name":"", "phy_name":"" }, "pin1": { "log_name":"", "phy_name":"" }, "arrive":11.801, "delay":0.000 } ] } Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- -------------- ---------------- --------- --------------------- ------ CONSTRAINT 0.000 10.000 1 Clk top CLOCK LATENCY 0.000 10.000 1 Clk NET DELAY 0.000 10.000 1 Clk_pad.bb_inst/B->Clk_pad.bb_inst/O SEIO33_CORE PADI_DEL 1.366 11.366 3 Clk_c NET DELAY 0.435 11.801 3 CNT1_e3_e3_e3_21__i1.ff_inst/CLK CLOCK PIN 0.000 11.801 1 Uncertainty -(0.000) 11.801 Common Path Skew 0.000 11.801 Setup time -(-0.058) 11.859 ---------------------------------------- -------------- ---------------- --------- --------------------- ------ Required Time 11.859 Arrival Time -(2.753) ---------------------------------------- -------------- ---------------- --------- --------------------- ------ Path Slack (Passed) 9.106 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ End of Detailed Report for timing paths +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ ########################################################## 3 Setup at Speed Grade 9_High-Performance_1.0V Corner at 0 Degrees 3.1 Clock Summary 3.1.1 Clock "CLK1" create_clock -name {CLK1} -period 10 [get_ports Clk] Single Clock Domain ------------------------------------------------------------------------------------------------------- Clock CLK1 | | Period | Frequency ------------------------------------------------------------------------------------------------------- From CLK1 | Target | 10.000 ns | 100.000 MHz | Actual (all paths) | 5.000 ns | 200.000 MHz Clk_pad.bb_inst/B (MPW) | (50% duty cycle) | 5.000 ns | 200.000 MHz ------------------------------------------------------------------------------------------------------- Clock Domain Crossing ------------------------------------------------------------------------------------------------------ Clock CLK1 | Worst Time Between Edges | Comment ------------------------------------------------------------------------------------------------------ From CLK2 | ---- | No path ------------------------------------------------------------------------------------------------------ 3.1.2 Clock "CLK2" create_generated_clock -name {CLK2} -source [get_pins Clk_pad.bb_inst/O] -edges {1 2 9} [get_pins MyDCC/CLKO] Single Clock Domain ------------------------------------------------------------------------------------------------------- Clock CLK2 | | Period | Frequency ------------------------------------------------------------------------------------------------------- From CLK2 | Target | 40.000 ns | 25.000 MHz | Actual (all paths) | 2.000 ns | 500.000 MHz CNT2_d_i8.ff_inst/CLK (MPW) | (50% duty cycle) | 2.000 ns | 500.000 MHz ------------------------------------------------------------------------------------------------------- Clock Domain Crossing ------------------------------------------------------------------------------------------------------ Clock CLK2 | Worst Time Between Edges | Comment ------------------------------------------------------------------------------------------------------ From CLK1 | ---- | No path ------------------------------------------------------------------------------------------------------ 3.2 Endpoint slacks ------------------------------------------------------- Listing 10 End Points | Slack ------------------------------------------------------- CNT2_d_i1.ff_inst/DF | 4.213 ns CNT2_d_i3.ff_inst/DF | 4.213 ns CNT2_d_i5.ff_inst/DF | 4.213 ns CNT2_d_i7.ff_inst/DF | 4.213 ns CNT2_d_i2.ff_inst/DF | 4.216 ns CNT2_d_i4.ff_inst/DF | 4.216 ns CNT2_d_i6.ff_inst/DF | 4.216 ns CNT2_d_i8.ff_inst/DF | 4.216 ns MyDCC/CE | 8.612 ns CNT1_e3_e3_e3_21__i1.ff_inst/DF | 9.105 ns ------------------------------------------------------- | Setup # of endpoints with negative slack:| 0 | ------------------------------------------------------- 3.3 Detailed Report XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX Detail report of critical paths XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Detailed Report for timing paths +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ ++++Path 1 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Path Begin : CNT2_e3_e3_e3_20__i0.ff_inst/Q (SLICE) Path End : CNT2_d_i1.ff_inst/DF (SLICE) Source Clock : CLK2 (R) Destination Clock: CLK2 (F) Logic Level : 1 Delay Ratio : 58.5% (route), 41.5% (logic) Clock Skew : -0.079 ns Setup Constraint : 5.000 ns Common Path Skew : 0.000 ns Path Slack : 4.213 ns (Passed) Source Clock Path { "path_begin": { "type":"port", "log_name":"Clk", "phy_name":"Clk" }, "path_end": { "type":"pin", "log_name":"CNT2_e3_e3_e3_20__i0.ff_inst/CLK", "phy_name":"SLICE_1/CLK" }, "path_sections":[ { "type":"net_delay", "net": { "log_name":"Clk", "phy_name":"Clk" }, "arrive":0.000, "delay":0.000 }, { "type":"site_delay", "pin0": { "log_name":"Clk_pad.bb_inst/B", "phy_name":"Clk_pad.bb_inst/IOPAD" }, "pin1": { "log_name":"Clk_pad.bb_inst/O", "phy_name":"Clk_pad.bb_inst/PADDI" }, "arrive":1.238, "delay":1.238 }, { "type":"net_delay", "net": { "log_name":"Clk_c", "phy_name":"Clk_c" }, "arrive":1.673, "delay":0.435 }, { "type":"site_delay", "pin0": { "log_name":"MyDCC/CLKI", "phy_name":"MyDCC/CLKI" }, "pin1": { "log_name":"MyDCC/CLKO", "phy_name":"MyDCC/CLKO" }, "arrive":1.673, "delay":0.000 }, { "type":"net_delay", "net": { "log_name":"clk2", "phy_name":"clk2" }, "arrive":2.108, "delay":0.435 }, { "type":"site_delay", "pin0": { "log_name":"", "phy_name":"" }, "pin1": { "log_name":"", "phy_name":"" }, "arrive":2.108, "delay":0.000 } ] } Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- -------------- ---------------- --------- --------------------- ------ Clk top CLOCK LATENCY 0.000 0.000 1 Clk NET DELAY 0.000 0.000 1 Clk_pad.bb_inst/B->Clk_pad.bb_inst/O SEIO33_CORE PADI_DEL 1.238 1.238 3 Clk_c NET DELAY 0.435 1.673 3 MyDCC/CLKI->MyDCC/CLKO DCC DCC_DEL 0.000 1.673 13 clk2 NET DELAY 0.435 2.108 13 CNT2_e3_e3_e3_20__i0.ff_inst/CLK CLOCK PIN 0.000 2.108 1 Data Path { "path_begin": { "type":"pin", "log_name":"CNT2_e3_e3_e3_20__i0.ff_inst/Q", "phy_name":"SLICE_1/Q1" }, "path_end": { "type":"pin", "log_name":"CNT2_d_i1.ff_inst/DF", "phy_name":"CNT2_d_i1.SLICE_14/M0" }, "path_sections":[ { "type":"site_delay", "pin0": { "log_name":"CNT2_e3_e3_e3_20__i0.ff_inst/CLK", "phy_name":"SLICE_1/CLK" }, "pin1": { "log_name":"CNT2_e3_e3_e3_20__i0.ff_inst/Q", "phy_name":"SLICE_1/Q1" }, "arrive":2.416, "delay":0.308 }, { "type":"net_delay", "net": { "log_name":"CNT2[0]", "phy_name":"CNT2[0]" }, "arrive":2.851, "delay":0.435 }, { "type":"site_delay", "pin0": { "log_name":"", "phy_name":"" }, "pin1": { "log_name":"", "phy_name":"" }, "arrive":2.851, "delay":0.000 } ] } Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- -------------- ---------------- --------- --------------------- ------ CNT2_e3_e3_e3_20__i0.ff_inst/CLK->CNT2_e3_e3_e3_20__i0.ff_inst/Q SLICE REG_DEL 0.308 2.416 2 CNT2[0] NET DELAY 0.435 2.851 2 CNT2_d_i1.ff_inst/DF ENDPOINT 0.000 2.851 1 Destination Clock Path { "path_begin": { "type":"port", "log_name":"Clk", "phy_name":"Clk" }, "path_end": { "type":"pin", "log_name":"CNT2_d_i1.ff_inst/CLK", "phy_name":"CNT2_d_i1.SLICE_14/CLK" }, "path_sections":[ { "type":"site_delay", "pin0": { "log_name":"", "phy_name":"" }, "pin1": { "log_name":"", "phy_name":"" }, "arrive":5.000, "delay":0.000 }, { "type":"net_delay", "net": { "log_name":"Clk", "phy_name":"Clk" }, "arrive":5.000, "delay":0.000 }, { "type":"site_delay", "pin0": { "log_name":"Clk_pad.bb_inst/B", "phy_name":"Clk_pad.bb_inst/IOPAD" }, "pin1": { "log_name":"Clk_pad.bb_inst/O", "phy_name":"Clk_pad.bb_inst/PADDI" }, "arrive":6.159, "delay":1.159 }, { "type":"net_delay", "net": { "log_name":"Clk_c", "phy_name":"Clk_c" }, "arrive":6.594, "delay":0.435 }, { "type":"site_delay", "pin0": { "log_name":"MyDCC/CLKI", "phy_name":"MyDCC/CLKI" }, "pin1": { "log_name":"MyDCC/CLKO", "phy_name":"MyDCC/CLKO" }, "arrive":6.594, "delay":0.000 }, { "type":"net_delay", "net": { "log_name":"clk2", "phy_name":"clk2" }, "arrive":7.029, "delay":0.435 }, { "type":"site_delay", "pin0": { "log_name":"", "phy_name":"" }, "pin1": { "log_name":"", "phy_name":"" }, "arrive":7.029, "delay":0.000 } ] } Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- -------------- ---------------- --------- --------------------- ------ CONSTRAINT 0.000 5.000 1 Clk top CLOCK LATENCY 0.000 5.000 1 Clk NET DELAY 0.000 5.000 1 Clk_pad.bb_inst/B->Clk_pad.bb_inst/O SEIO33_CORE PADI_DEL 1.159 6.159 3 Clk_c NET DELAY 0.435 6.594 3 MyDCC/CLKI->MyDCC/CLKO DCC DCC_DEL 0.000 6.594 13 clk2 NET DELAY 0.435 7.029 13 CNT2_d_i1.ff_inst/CLK CLOCK PIN 0.000 7.029 1 Uncertainty -(0.000) 7.029 Common Path Skew 0.000 7.029 Setup time -(-0.035) 7.064 ---------------------------------------- -------------- ---------------- --------- --------------------- ------ Required Time 7.064 Arrival Time -(2.851) ---------------------------------------- -------------- ---------------- --------- --------------------- ------ Path Slack (Passed) 4.213 ++++ Path 2 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Path Begin : CNT2_e3_e3_e3_20__i2.ff_inst/Q (SLICE) Path End : CNT2_d_i3.ff_inst/DF (SLICE) Source Clock : CLK2 (R) Destination Clock: CLK2 (F) Logic Level : 1 Delay Ratio : 58.5% (route), 41.5% (logic) Clock Skew : -0.079 ns Setup Constraint : 5.000 ns Common Path Skew : 0.000 ns Path Slack : 4.213 ns (Passed) Source Clock Path { "path_begin": { "type":"port", "log_name":"Clk", "phy_name":"Clk" }, "path_end": { "type":"pin", "log_name":"CNT2_e3_e3_e3_20__i1.ff_inst/CLK", "phy_name":"SLICE_2/CLK" }, "path_sections":[ { "type":"net_delay", "net": { "log_name":"Clk", "phy_name":"Clk" }, "arrive":0.000, "delay":0.000 }, { "type":"site_delay", "pin0": { "log_name":"Clk_pad.bb_inst/B", "phy_name":"Clk_pad.bb_inst/IOPAD" }, "pin1": { "log_name":"Clk_pad.bb_inst/O", "phy_name":"Clk_pad.bb_inst/PADDI" }, "arrive":1.238, "delay":1.238 }, { "type":"net_delay", "net": { "log_name":"Clk_c", "phy_name":"Clk_c" }, "arrive":1.673, "delay":0.435 }, { "type":"site_delay", "pin0": { "log_name":"MyDCC/CLKI", "phy_name":"MyDCC/CLKI" }, "pin1": { "log_name":"MyDCC/CLKO", "phy_name":"MyDCC/CLKO" }, "arrive":1.673, "delay":0.000 }, { "type":"net_delay", "net": { "log_name":"clk2", "phy_name":"clk2" }, "arrive":2.108, "delay":0.435 }, { "type":"site_delay", "pin0": { "log_name":"", "phy_name":"" }, "pin1": { "log_name":"", "phy_name":"" }, "arrive":2.108, "delay":0.000 } ] } Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- -------------- ---------------- --------- --------------------- ------ Clk top CLOCK LATENCY 0.000 0.000 1 Clk NET DELAY 0.000 0.000 1 Clk_pad.bb_inst/B->Clk_pad.bb_inst/O SEIO33_CORE PADI_DEL 1.238 1.238 3 Clk_c NET DELAY 0.435 1.673 3 MyDCC/CLKI->MyDCC/CLKO DCC DCC_DEL 0.000 1.673 13 clk2 NET DELAY 0.435 2.108 13 {CNT2_e3_e3_e3_20__i1.ff_inst/CLK CNT2_e3_e3_e3_20__i2.ff_inst/CLK} CLOCK PIN 0.000 2.108 1 Data Path { "path_begin": { "type":"pin", "log_name":"CNT2_e3_e3_e3_20__i2.ff_inst/Q", "phy_name":"SLICE_2/Q1" }, "path_end": { "type":"pin", "log_name":"CNT2_d_i3.ff_inst/DF", "phy_name":"CNT2_d_i3.SLICE_12/M0" }, "path_sections":[ { "type":"site_delay", "pin0": { "log_name":"CNT2_e3_e3_e3_20__i2.ff_inst/CLK", "phy_name":"SLICE_2/CLK" }, "pin1": { "log_name":"CNT2_e3_e3_e3_20__i2.ff_inst/Q", "phy_name":"SLICE_2/Q1" }, "arrive":2.416, "delay":0.308 }, { "type":"net_delay", "net": { "log_name":"CNT2[2]", "phy_name":"CNT2[2]" }, "arrive":2.851, "delay":0.435 }, { "type":"site_delay", "pin0": { "log_name":"", "phy_name":"" }, "pin1": { "log_name":"", "phy_name":"" }, "arrive":2.851, "delay":0.000 } ] } Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- -------------- ---------------- --------- --------------------- ------ CNT2_e3_e3_e3_20__i2.ff_inst/CLK->CNT2_e3_e3_e3_20__i2.ff_inst/Q SLICE REG_DEL 0.308 2.416 2 CNT2[2] NET DELAY 0.435 2.851 2 CNT2_d_i3.ff_inst/DF ENDPOINT 0.000 2.851 1 Destination Clock Path { "path_begin": { "type":"port", "log_name":"Clk", "phy_name":"Clk" }, "path_end": { "type":"pin", "log_name":"CNT2_d_i3.ff_inst/CLK", "phy_name":"CNT2_d_i3.SLICE_12/CLK" }, "path_sections":[ { "type":"site_delay", "pin0": { "log_name":"", "phy_name":"" }, "pin1": { "log_name":"", "phy_name":"" }, "arrive":5.000, "delay":0.000 }, { "type":"net_delay", "net": { "log_name":"Clk", "phy_name":"Clk" }, "arrive":5.000, "delay":0.000 }, { "type":"site_delay", "pin0": { "log_name":"Clk_pad.bb_inst/B", "phy_name":"Clk_pad.bb_inst/IOPAD" }, "pin1": { "log_name":"Clk_pad.bb_inst/O", "phy_name":"Clk_pad.bb_inst/PADDI" }, "arrive":6.159, "delay":1.159 }, { "type":"net_delay", "net": { "log_name":"Clk_c", "phy_name":"Clk_c" }, "arrive":6.594, "delay":0.435 }, { "type":"site_delay", "pin0": { "log_name":"MyDCC/CLKI", "phy_name":"MyDCC/CLKI" }, "pin1": { "log_name":"MyDCC/CLKO", "phy_name":"MyDCC/CLKO" }, "arrive":6.594, "delay":0.000 }, { "type":"net_delay", "net": { "log_name":"clk2", "phy_name":"clk2" }, "arrive":7.029, "delay":0.435 }, { "type":"site_delay", "pin0": { "log_name":"", "phy_name":"" }, "pin1": { "log_name":"", "phy_name":"" }, "arrive":7.029, "delay":0.000 } ] } Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- -------------- ---------------- --------- --------------------- ------ CONSTRAINT 0.000 5.000 1 Clk top CLOCK LATENCY 0.000 5.000 1 Clk NET DELAY 0.000 5.000 1 Clk_pad.bb_inst/B->Clk_pad.bb_inst/O SEIO33_CORE PADI_DEL 1.159 6.159 3 Clk_c NET DELAY 0.435 6.594 3 MyDCC/CLKI->MyDCC/CLKO DCC DCC_DEL 0.000 6.594 13 clk2 NET DELAY 0.435 7.029 13 CNT2_d_i3.ff_inst/CLK CLOCK PIN 0.000 7.029 1 Uncertainty -(0.000) 7.029 Common Path Skew 0.000 7.029 Setup time -(-0.035) 7.064 ---------------------------------------- -------------- ---------------- --------- --------------------- ------ Required Time 7.064 Arrival Time -(2.851) ---------------------------------------- -------------- ---------------- --------- --------------------- ------ Path Slack (Passed) 4.213 ++++ Path 3 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Path Begin : CNT2_e3_e3_e3_20__i4.ff_inst/Q (SLICE) Path End : CNT2_d_i5.ff_inst/DF (SLICE) Source Clock : CLK2 (R) Destination Clock: CLK2 (F) Logic Level : 1 Delay Ratio : 58.5% (route), 41.5% (logic) Clock Skew : -0.079 ns Setup Constraint : 5.000 ns Common Path Skew : 0.000 ns Path Slack : 4.213 ns (Passed) Source Clock Path { "path_begin": { "type":"port", "log_name":"Clk", "phy_name":"Clk" }, "path_end": { "type":"pin", "log_name":"CNT2_e3_e3_e3_20__i3.ff_inst/CLK", "phy_name":"SLICE_0/CLK" }, "path_sections":[ { "type":"net_delay", "net": { "log_name":"Clk", "phy_name":"Clk" }, "arrive":0.000, "delay":0.000 }, { "type":"site_delay", "pin0": { "log_name":"Clk_pad.bb_inst/B", "phy_name":"Clk_pad.bb_inst/IOPAD" }, "pin1": { "log_name":"Clk_pad.bb_inst/O", "phy_name":"Clk_pad.bb_inst/PADDI" }, "arrive":1.238, "delay":1.238 }, { "type":"net_delay", "net": { "log_name":"Clk_c", "phy_name":"Clk_c" }, "arrive":1.673, "delay":0.435 }, { "type":"site_delay", "pin0": { "log_name":"MyDCC/CLKI", "phy_name":"MyDCC/CLKI" }, "pin1": { "log_name":"MyDCC/CLKO", "phy_name":"MyDCC/CLKO" }, "arrive":1.673, "delay":0.000 }, { "type":"net_delay", "net": { "log_name":"clk2", "phy_name":"clk2" }, "arrive":2.108, "delay":0.435 }, { "type":"site_delay", "pin0": { "log_name":"", "phy_name":"" }, "pin1": { "log_name":"", "phy_name":"" }, "arrive":2.108, "delay":0.000 } ] } Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- -------------- ---------------- --------- --------------------- ------ Clk top CLOCK LATENCY 0.000 0.000 1 Clk NET DELAY 0.000 0.000 1 Clk_pad.bb_inst/B->Clk_pad.bb_inst/O SEIO33_CORE PADI_DEL 1.238 1.238 3 Clk_c NET DELAY 0.435 1.673 3 MyDCC/CLKI->MyDCC/CLKO DCC DCC_DEL 0.000 1.673 13 clk2 NET DELAY 0.435 2.108 13 {CNT2_e3_e3_e3_20__i3.ff_inst/CLK CNT2_e3_e3_e3_20__i4.ff_inst/CLK} CLOCK PIN 0.000 2.108 1 Data Path { "path_begin": { "type":"pin", "log_name":"CNT2_e3_e3_e3_20__i4.ff_inst/Q", "phy_name":"SLICE_0/Q1" }, "path_end": { "type":"pin", "log_name":"CNT2_d_i5.ff_inst/DF", "phy_name":"CNT2_d_i5.SLICE_10/M0" }, "path_sections":[ { "type":"site_delay", "pin0": { "log_name":"CNT2_e3_e3_e3_20__i4.ff_inst/CLK", "phy_name":"SLICE_0/CLK" }, "pin1": { "log_name":"CNT2_e3_e3_e3_20__i4.ff_inst/Q", "phy_name":"SLICE_0/Q1" }, "arrive":2.416, "delay":0.308 }, { "type":"net_delay", "net": { "log_name":"CNT2[4]", "phy_name":"CNT2[4]" }, "arrive":2.851, "delay":0.435 }, { "type":"site_delay", "pin0": { "log_name":"", "phy_name":"" }, "pin1": { "log_name":"", "phy_name":"" }, "arrive":2.851, "delay":0.000 } ] } Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- -------------- ---------------- --------- --------------------- ------ CNT2_e3_e3_e3_20__i4.ff_inst/CLK->CNT2_e3_e3_e3_20__i4.ff_inst/Q SLICE REG_DEL 0.308 2.416 2 CNT2[4] NET DELAY 0.435 2.851 2 CNT2_d_i5.ff_inst/DF ENDPOINT 0.000 2.851 1 Destination Clock Path { "path_begin": { "type":"port", "log_name":"Clk", "phy_name":"Clk" }, "path_end": { "type":"pin", "log_name":"CNT2_d_i5.ff_inst/CLK", "phy_name":"CNT2_d_i5.SLICE_10/CLK" }, "path_sections":[ { "type":"site_delay", "pin0": { "log_name":"", "phy_name":"" }, "pin1": { "log_name":"", "phy_name":"" }, "arrive":5.000, "delay":0.000 }, { "type":"net_delay", "net": { "log_name":"Clk", "phy_name":"Clk" }, "arrive":5.000, "delay":0.000 }, { "type":"site_delay", "pin0": { "log_name":"Clk_pad.bb_inst/B", "phy_name":"Clk_pad.bb_inst/IOPAD" }, "pin1": { "log_name":"Clk_pad.bb_inst/O", "phy_name":"Clk_pad.bb_inst/PADDI" }, "arrive":6.159, "delay":1.159 }, { "type":"net_delay", "net": { "log_name":"Clk_c", "phy_name":"Clk_c" }, "arrive":6.594, "delay":0.435 }, { "type":"site_delay", "pin0": { "log_name":"MyDCC/CLKI", "phy_name":"MyDCC/CLKI" }, "pin1": { "log_name":"MyDCC/CLKO", "phy_name":"MyDCC/CLKO" }, "arrive":6.594, "delay":0.000 }, { "type":"net_delay", "net": { "log_name":"clk2", "phy_name":"clk2" }, "arrive":7.029, "delay":0.435 }, { "type":"site_delay", "pin0": { "log_name":"", "phy_name":"" }, "pin1": { "log_name":"", "phy_name":"" }, "arrive":7.029, "delay":0.000 } ] } Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- -------------- ---------------- --------- --------------------- ------ CONSTRAINT 0.000 5.000 1 Clk top CLOCK LATENCY 0.000 5.000 1 Clk NET DELAY 0.000 5.000 1 Clk_pad.bb_inst/B->Clk_pad.bb_inst/O SEIO33_CORE PADI_DEL 1.159 6.159 3 Clk_c NET DELAY 0.435 6.594 3 MyDCC/CLKI->MyDCC/CLKO DCC DCC_DEL 0.000 6.594 13 clk2 NET DELAY 0.435 7.029 13 CNT2_d_i5.ff_inst/CLK CLOCK PIN 0.000 7.029 1 Uncertainty -(0.000) 7.029 Common Path Skew 0.000 7.029 Setup time -(-0.035) 7.064 ---------------------------------------- -------------- ---------------- --------- --------------------- ------ Required Time 7.064 Arrival Time -(2.851) ---------------------------------------- -------------- ---------------- --------- --------------------- ------ Path Slack (Passed) 4.213 ++++ Path 4 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Path Begin : CNT2_e3_e3_e3_20__i6.ff_inst/Q (SLICE) Path End : CNT2_d_i7.ff_inst/DF (SLICE) Source Clock : CLK2 (R) Destination Clock: CLK2 (F) Logic Level : 1 Delay Ratio : 58.5% (route), 41.5% (logic) Clock Skew : -0.079 ns Setup Constraint : 5.000 ns Common Path Skew : 0.000 ns Path Slack : 4.213 ns (Passed) Source Clock Path { "path_begin": { "type":"port", "log_name":"Clk", "phy_name":"Clk" }, "path_end": { "type":"pin", "log_name":"CNT2_e3_e3_e3_20__i5.ff_inst/CLK", "phy_name":"SLICE_3/CLK" }, "path_sections":[ { "type":"net_delay", "net": { "log_name":"Clk", "phy_name":"Clk" }, "arrive":0.000, "delay":0.000 }, { "type":"site_delay", "pin0": { "log_name":"Clk_pad.bb_inst/B", "phy_name":"Clk_pad.bb_inst/IOPAD" }, "pin1": { "log_name":"Clk_pad.bb_inst/O", "phy_name":"Clk_pad.bb_inst/PADDI" }, "arrive":1.238, "delay":1.238 }, { "type":"net_delay", "net": { "log_name":"Clk_c", "phy_name":"Clk_c" }, "arrive":1.673, "delay":0.435 }, { "type":"site_delay", "pin0": { "log_name":"MyDCC/CLKI", "phy_name":"MyDCC/CLKI" }, "pin1": { "log_name":"MyDCC/CLKO", "phy_name":"MyDCC/CLKO" }, "arrive":1.673, "delay":0.000 }, { "type":"net_delay", "net": { "log_name":"clk2", "phy_name":"clk2" }, "arrive":2.108, "delay":0.435 }, { "type":"site_delay", "pin0": { "log_name":"", "phy_name":"" }, "pin1": { "log_name":"", "phy_name":"" }, "arrive":2.108, "delay":0.000 } ] } Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- -------------- ---------------- --------- --------------------- ------ Clk top CLOCK LATENCY 0.000 0.000 1 Clk NET DELAY 0.000 0.000 1 Clk_pad.bb_inst/B->Clk_pad.bb_inst/O SEIO33_CORE PADI_DEL 1.238 1.238 3 Clk_c NET DELAY 0.435 1.673 3 MyDCC/CLKI->MyDCC/CLKO DCC DCC_DEL 0.000 1.673 13 clk2 NET DELAY 0.435 2.108 13 {CNT2_e3_e3_e3_20__i5.ff_inst/CLK CNT2_e3_e3_e3_20__i6.ff_inst/CLK} CLOCK PIN 0.000 2.108 1 Data Path { "path_begin": { "type":"pin", "log_name":"CNT2_e3_e3_e3_20__i6.ff_inst/Q", "phy_name":"SLICE_3/Q1" }, "path_end": { "type":"pin", "log_name":"CNT2_d_i7.ff_inst/DF", "phy_name":"CNT2_d_i7.SLICE_7/M0" }, "path_sections":[ { "type":"site_delay", "pin0": { "log_name":"CNT2_e3_e3_e3_20__i6.ff_inst/CLK", "phy_name":"SLICE_3/CLK" }, "pin1": { "log_name":"CNT2_e3_e3_e3_20__i6.ff_inst/Q", "phy_name":"SLICE_3/Q1" }, "arrive":2.416, "delay":0.308 }, { "type":"net_delay", "net": { "log_name":"CNT2[6]", "phy_name":"CNT2[6]" }, "arrive":2.851, "delay":0.435 }, { "type":"site_delay", "pin0": { "log_name":"", "phy_name":"" }, "pin1": { "log_name":"", "phy_name":"" }, "arrive":2.851, "delay":0.000 } ] } Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- -------------- ---------------- --------- --------------------- ------ CNT2_e3_e3_e3_20__i6.ff_inst/CLK->CNT2_e3_e3_e3_20__i6.ff_inst/Q SLICE REG_DEL 0.308 2.416 2 CNT2[6] NET DELAY 0.435 2.851 2 CNT2_d_i7.ff_inst/DF ENDPOINT 0.000 2.851 1 Destination Clock Path { "path_begin": { "type":"port", "log_name":"Clk", "phy_name":"Clk" }, "path_end": { "type":"pin", "log_name":"CNT2_d_i7.ff_inst/CLK", "phy_name":"CNT2_d_i7.SLICE_7/CLK" }, "path_sections":[ { "type":"site_delay", "pin0": { "log_name":"", "phy_name":"" }, "pin1": { "log_name":"", "phy_name":"" }, "arrive":5.000, "delay":0.000 }, { "type":"net_delay", "net": { "log_name":"Clk", "phy_name":"Clk" }, "arrive":5.000, "delay":0.000 }, { "type":"site_delay", "pin0": { "log_name":"Clk_pad.bb_inst/B", "phy_name":"Clk_pad.bb_inst/IOPAD" }, "pin1": { "log_name":"Clk_pad.bb_inst/O", "phy_name":"Clk_pad.bb_inst/PADDI" }, "arrive":6.159, "delay":1.159 }, { "type":"net_delay", "net": { "log_name":"Clk_c", "phy_name":"Clk_c" }, "arrive":6.594, "delay":0.435 }, { "type":"site_delay", "pin0": { "log_name":"MyDCC/CLKI", "phy_name":"MyDCC/CLKI" }, "pin1": { "log_name":"MyDCC/CLKO", "phy_name":"MyDCC/CLKO" }, "arrive":6.594, "delay":0.000 }, { "type":"net_delay", "net": { "log_name":"clk2", "phy_name":"clk2" }, "arrive":7.029, "delay":0.435 }, { "type":"site_delay", "pin0": { "log_name":"", "phy_name":"" }, "pin1": { "log_name":"", "phy_name":"" }, "arrive":7.029, "delay":0.000 } ] } Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- -------------- ---------------- --------- --------------------- ------ CONSTRAINT 0.000 5.000 1 Clk top CLOCK LATENCY 0.000 5.000 1 Clk NET DELAY 0.000 5.000 1 Clk_pad.bb_inst/B->Clk_pad.bb_inst/O SEIO33_CORE PADI_DEL 1.159 6.159 3 Clk_c NET DELAY 0.435 6.594 3 MyDCC/CLKI->MyDCC/CLKO DCC DCC_DEL 0.000 6.594 13 clk2 NET DELAY 0.435 7.029 13 CNT2_d_i7.ff_inst/CLK CLOCK PIN 0.000 7.029 1 Uncertainty -(0.000) 7.029 Common Path Skew 0.000 7.029 Setup time -(-0.035) 7.064 ---------------------------------------- -------------- ---------------- --------- --------------------- ------ Required Time 7.064 Arrival Time -(2.851) ---------------------------------------- -------------- ---------------- --------- --------------------- ------ Path Slack (Passed) 4.213 ++++ Path 5 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Path Begin : CNT2_e3_e3_e3_20__i1.ff_inst/Q (SLICE) Path End : CNT2_d_i2.ff_inst/DF (SLICE) Source Clock : CLK2 (R) Destination Clock: CLK2 (F) Logic Level : 1 Delay Ratio : 58.8% (route), 41.2% (logic) Clock Skew : -0.079 ns Setup Constraint : 5.000 ns Common Path Skew : 0.000 ns Path Slack : 4.216 ns (Passed) Source Clock Path { "path_begin": { "type":"port", "log_name":"Clk", "phy_name":"Clk" }, "path_end": { "type":"pin", "log_name":"CNT2_e3_e3_e3_20__i1.ff_inst/CLK", "phy_name":"SLICE_2/CLK" }, "path_sections":[ { "type":"net_delay", "net": { "log_name":"Clk", "phy_name":"Clk" }, "arrive":0.000, "delay":0.000 }, { "type":"site_delay", "pin0": { "log_name":"Clk_pad.bb_inst/B", "phy_name":"Clk_pad.bb_inst/IOPAD" }, "pin1": { "log_name":"Clk_pad.bb_inst/O", "phy_name":"Clk_pad.bb_inst/PADDI" }, "arrive":1.238, "delay":1.238 }, { "type":"net_delay", "net": { "log_name":"Clk_c", "phy_name":"Clk_c" }, "arrive":1.673, "delay":0.435 }, { "type":"site_delay", "pin0": { "log_name":"MyDCC/CLKI", "phy_name":"MyDCC/CLKI" }, "pin1": { "log_name":"MyDCC/CLKO", "phy_name":"MyDCC/CLKO" }, "arrive":1.673, "delay":0.000 }, { "type":"net_delay", "net": { "log_name":"clk2", "phy_name":"clk2" }, "arrive":2.108, "delay":0.435 }, { "type":"site_delay", "pin0": { "log_name":"", "phy_name":"" }, "pin1": { "log_name":"", "phy_name":"" }, "arrive":2.108, "delay":0.000 } ] } Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- -------------- ---------------- --------- --------------------- ------ Clk top CLOCK LATENCY 0.000 0.000 1 Clk NET DELAY 0.000 0.000 1 Clk_pad.bb_inst/B->Clk_pad.bb_inst/O SEIO33_CORE PADI_DEL 1.238 1.238 3 Clk_c NET DELAY 0.435 1.673 3 MyDCC/CLKI->MyDCC/CLKO DCC DCC_DEL 0.000 1.673 13 clk2 NET DELAY 0.435 2.108 13 {CNT2_e3_e3_e3_20__i1.ff_inst/CLK CNT2_e3_e3_e3_20__i2.ff_inst/CLK} CLOCK PIN 0.000 2.108 1 Data Path { "path_begin": { "type":"pin", "log_name":"CNT2_e3_e3_e3_20__i1.ff_inst/Q", "phy_name":"SLICE_2/Q0" }, "path_end": { "type":"pin", "log_name":"CNT2_d_i2.ff_inst/DF", "phy_name":"CNT2_d_i2.SLICE_13/M0" }, "path_sections":[ { "type":"site_delay", "pin0": { "log_name":"CNT2_e3_e3_e3_20__i1.ff_inst/CLK", "phy_name":"SLICE_2/CLK" }, "pin1": { "log_name":"CNT2_e3_e3_e3_20__i1.ff_inst/Q", "phy_name":"SLICE_2/Q0" }, "arrive":2.413, "delay":0.305 }, { "type":"net_delay", "net": { "log_name":"CNT2[1]", "phy_name":"CNT2[1]" }, "arrive":2.848, "delay":0.435 }, { "type":"site_delay", "pin0": { "log_name":"", "phy_name":"" }, "pin1": { "log_name":"", "phy_name":"" }, "arrive":2.848, "delay":0.000 } ] } Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- -------------- ---------------- --------- --------------------- ------ CNT2_e3_e3_e3_20__i1.ff_inst/CLK->CNT2_e3_e3_e3_20__i1.ff_inst/Q SLICE REG_DEL 0.305 2.413 2 CNT2[1] NET DELAY 0.435 2.848 2 CNT2_d_i2.ff_inst/DF ENDPOINT 0.000 2.848 1 Destination Clock Path { "path_begin": { "type":"port", "log_name":"Clk", "phy_name":"Clk" }, "path_end": { "type":"pin", "log_name":"CNT2_d_i2.ff_inst/CLK", "phy_name":"CNT2_d_i2.SLICE_13/CLK" }, "path_sections":[ { "type":"site_delay", "pin0": { "log_name":"", "phy_name":"" }, "pin1": { "log_name":"", "phy_name":"" }, "arrive":5.000, "delay":0.000 }, { "type":"net_delay", "net": { "log_name":"Clk", "phy_name":"Clk" }, "arrive":5.000, "delay":0.000 }, { "type":"site_delay", "pin0": { "log_name":"Clk_pad.bb_inst/B", "phy_name":"Clk_pad.bb_inst/IOPAD" }, "pin1": { "log_name":"Clk_pad.bb_inst/O", "phy_name":"Clk_pad.bb_inst/PADDI" }, "arrive":6.159, "delay":1.159 }, { "type":"net_delay", "net": { "log_name":"Clk_c", "phy_name":"Clk_c" }, "arrive":6.594, "delay":0.435 }, { "type":"site_delay", "pin0": { "log_name":"MyDCC/CLKI", "phy_name":"MyDCC/CLKI" }, "pin1": { "log_name":"MyDCC/CLKO", "phy_name":"MyDCC/CLKO" }, "arrive":6.594, "delay":0.000 }, { "type":"net_delay", "net": { "log_name":"clk2", "phy_name":"clk2" }, "arrive":7.029, "delay":0.435 }, { "type":"site_delay", "pin0": { "log_name":"", "phy_name":"" }, "pin1": { "log_name":"", "phy_name":"" }, "arrive":7.029, "delay":0.000 } ] } Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- -------------- ---------------- --------- --------------------- ------ CONSTRAINT 0.000 5.000 1 Clk top CLOCK LATENCY 0.000 5.000 1 Clk NET DELAY 0.000 5.000 1 Clk_pad.bb_inst/B->Clk_pad.bb_inst/O SEIO33_CORE PADI_DEL 1.159 6.159 3 Clk_c NET DELAY 0.435 6.594 3 MyDCC/CLKI->MyDCC/CLKO DCC DCC_DEL 0.000 6.594 13 clk2 NET DELAY 0.435 7.029 13 CNT2_d_i2.ff_inst/CLK CLOCK PIN 0.000 7.029 1 Uncertainty -(0.000) 7.029 Common Path Skew 0.000 7.029 Setup time -(-0.035) 7.064 ---------------------------------------- -------------- ---------------- --------- --------------------- ------ Required Time 7.064 Arrival Time -(2.848) ---------------------------------------- -------------- ---------------- --------- --------------------- ------ Path Slack (Passed) 4.216 ++++ Path 6 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Path Begin : CNT2_e3_e3_e3_20__i3.ff_inst/Q (SLICE) Path End : CNT2_d_i4.ff_inst/DF (SLICE) Source Clock : CLK2 (R) Destination Clock: CLK2 (F) Logic Level : 1 Delay Ratio : 58.8% (route), 41.2% (logic) Clock Skew : -0.079 ns Setup Constraint : 5.000 ns Common Path Skew : 0.000 ns Path Slack : 4.216 ns (Passed) Source Clock Path { "path_begin": { "type":"port", "log_name":"Clk", "phy_name":"Clk" }, "path_end": { "type":"pin", "log_name":"CNT2_e3_e3_e3_20__i3.ff_inst/CLK", "phy_name":"SLICE_0/CLK" }, "path_sections":[ { "type":"net_delay", "net": { "log_name":"Clk", "phy_name":"Clk" }, "arrive":0.000, "delay":0.000 }, { "type":"site_delay", "pin0": { "log_name":"Clk_pad.bb_inst/B", "phy_name":"Clk_pad.bb_inst/IOPAD" }, "pin1": { "log_name":"Clk_pad.bb_inst/O", "phy_name":"Clk_pad.bb_inst/PADDI" }, "arrive":1.238, "delay":1.238 }, { "type":"net_delay", "net": { "log_name":"Clk_c", "phy_name":"Clk_c" }, "arrive":1.673, "delay":0.435 }, { "type":"site_delay", "pin0": { "log_name":"MyDCC/CLKI", "phy_name":"MyDCC/CLKI" }, "pin1": { "log_name":"MyDCC/CLKO", "phy_name":"MyDCC/CLKO" }, "arrive":1.673, "delay":0.000 }, { "type":"net_delay", "net": { "log_name":"clk2", "phy_name":"clk2" }, "arrive":2.108, "delay":0.435 }, { "type":"site_delay", "pin0": { "log_name":"", "phy_name":"" }, "pin1": { "log_name":"", "phy_name":"" }, "arrive":2.108, "delay":0.000 } ] } Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- -------------- ---------------- --------- --------------------- ------ Clk top CLOCK LATENCY 0.000 0.000 1 Clk NET DELAY 0.000 0.000 1 Clk_pad.bb_inst/B->Clk_pad.bb_inst/O SEIO33_CORE PADI_DEL 1.238 1.238 3 Clk_c NET DELAY 0.435 1.673 3 MyDCC/CLKI->MyDCC/CLKO DCC DCC_DEL 0.000 1.673 13 clk2 NET DELAY 0.435 2.108 13 {CNT2_e3_e3_e3_20__i3.ff_inst/CLK CNT2_e3_e3_e3_20__i4.ff_inst/CLK} CLOCK PIN 0.000 2.108 1 Data Path { "path_begin": { "type":"pin", "log_name":"CNT2_e3_e3_e3_20__i3.ff_inst/Q", "phy_name":"SLICE_0/Q0" }, "path_end": { "type":"pin", "log_name":"CNT2_d_i4.ff_inst/DF", "phy_name":"CNT2_d_i4.SLICE_11/M0" }, "path_sections":[ { "type":"site_delay", "pin0": { "log_name":"CNT2_e3_e3_e3_20__i3.ff_inst/CLK", "phy_name":"SLICE_0/CLK" }, "pin1": { "log_name":"CNT2_e3_e3_e3_20__i3.ff_inst/Q", "phy_name":"SLICE_0/Q0" }, "arrive":2.413, "delay":0.305 }, { "type":"net_delay", "net": { "log_name":"CNT2[3]", "phy_name":"CNT2[3]" }, "arrive":2.848, "delay":0.435 }, { "type":"site_delay", "pin0": { "log_name":"", "phy_name":"" }, "pin1": { "log_name":"", "phy_name":"" }, "arrive":2.848, "delay":0.000 } ] } Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- -------------- ---------------- --------- --------------------- ------ CNT2_e3_e3_e3_20__i3.ff_inst/CLK->CNT2_e3_e3_e3_20__i3.ff_inst/Q SLICE REG_DEL 0.305 2.413 2 CNT2[3] NET DELAY 0.435 2.848 2 CNT2_d_i4.ff_inst/DF ENDPOINT 0.000 2.848 1 Destination Clock Path { "path_begin": { "type":"port", "log_name":"Clk", "phy_name":"Clk" }, "path_end": { "type":"pin", "log_name":"CNT2_d_i4.ff_inst/CLK", "phy_name":"CNT2_d_i4.SLICE_11/CLK" }, "path_sections":[ { "type":"site_delay", "pin0": { "log_name":"", "phy_name":"" }, "pin1": { "log_name":"", "phy_name":"" }, "arrive":5.000, "delay":0.000 }, { "type":"net_delay", "net": { "log_name":"Clk", "phy_name":"Clk" }, "arrive":5.000, "delay":0.000 }, { "type":"site_delay", "pin0": { "log_name":"Clk_pad.bb_inst/B", "phy_name":"Clk_pad.bb_inst/IOPAD" }, "pin1": { "log_name":"Clk_pad.bb_inst/O", "phy_name":"Clk_pad.bb_inst/PADDI" }, "arrive":6.159, "delay":1.159 }, { "type":"net_delay", "net": { "log_name":"Clk_c", "phy_name":"Clk_c" }, "arrive":6.594, "delay":0.435 }, { "type":"site_delay", "pin0": { "log_name":"MyDCC/CLKI", "phy_name":"MyDCC/CLKI" }, "pin1": { "log_name":"MyDCC/CLKO", "phy_name":"MyDCC/CLKO" }, "arrive":6.594, "delay":0.000 }, { "type":"net_delay", "net": { "log_name":"clk2", "phy_name":"clk2" }, "arrive":7.029, "delay":0.435 }, { "type":"site_delay", "pin0": { "log_name":"", "phy_name":"" }, "pin1": { "log_name":"", "phy_name":"" }, "arrive":7.029, "delay":0.000 } ] } Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- -------------- ---------------- --------- --------------------- ------ CONSTRAINT 0.000 5.000 1 Clk top CLOCK LATENCY 0.000 5.000 1 Clk NET DELAY 0.000 5.000 1 Clk_pad.bb_inst/B->Clk_pad.bb_inst/O SEIO33_CORE PADI_DEL 1.159 6.159 3 Clk_c NET DELAY 0.435 6.594 3 MyDCC/CLKI->MyDCC/CLKO DCC DCC_DEL 0.000 6.594 13 clk2 NET DELAY 0.435 7.029 13 CNT2_d_i4.ff_inst/CLK CLOCK PIN 0.000 7.029 1 Uncertainty -(0.000) 7.029 Common Path Skew 0.000 7.029 Setup time -(-0.035) 7.064 ---------------------------------------- -------------- ---------------- --------- --------------------- ------ Required Time 7.064 Arrival Time -(2.848) ---------------------------------------- -------------- ---------------- --------- --------------------- ------ Path Slack (Passed) 4.216 ++++ Path 7 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Path Begin : CNT2_e3_e3_e3_20__i5.ff_inst/Q (SLICE) Path End : CNT2_d_i6.ff_inst/DF (SLICE) Source Clock : CLK2 (R) Destination Clock: CLK2 (F) Logic Level : 1 Delay Ratio : 58.8% (route), 41.2% (logic) Clock Skew : -0.079 ns Setup Constraint : 5.000 ns Common Path Skew : 0.000 ns Path Slack : 4.216 ns (Passed) Source Clock Path { "path_begin": { "type":"port", "log_name":"Clk", "phy_name":"Clk" }, "path_end": { "type":"pin", "log_name":"CNT2_e3_e3_e3_20__i5.ff_inst/CLK", "phy_name":"SLICE_3/CLK" }, "path_sections":[ { "type":"net_delay", "net": { "log_name":"Clk", "phy_name":"Clk" }, "arrive":0.000, "delay":0.000 }, { "type":"site_delay", "pin0": { "log_name":"Clk_pad.bb_inst/B", "phy_name":"Clk_pad.bb_inst/IOPAD" }, "pin1": { "log_name":"Clk_pad.bb_inst/O", "phy_name":"Clk_pad.bb_inst/PADDI" }, "arrive":1.238, "delay":1.238 }, { "type":"net_delay", "net": { "log_name":"Clk_c", "phy_name":"Clk_c" }, "arrive":1.673, "delay":0.435 }, { "type":"site_delay", "pin0": { "log_name":"MyDCC/CLKI", "phy_name":"MyDCC/CLKI" }, "pin1": { "log_name":"MyDCC/CLKO", "phy_name":"MyDCC/CLKO" }, "arrive":1.673, "delay":0.000 }, { "type":"net_delay", "net": { "log_name":"clk2", "phy_name":"clk2" }, "arrive":2.108, "delay":0.435 }, { "type":"site_delay", "pin0": { "log_name":"", "phy_name":"" }, "pin1": { "log_name":"", "phy_name":"" }, "arrive":2.108, "delay":0.000 } ] } Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- -------------- ---------------- --------- --------------------- ------ Clk top CLOCK LATENCY 0.000 0.000 1 Clk NET DELAY 0.000 0.000 1 Clk_pad.bb_inst/B->Clk_pad.bb_inst/O SEIO33_CORE PADI_DEL 1.238 1.238 3 Clk_c NET DELAY 0.435 1.673 3 MyDCC/CLKI->MyDCC/CLKO DCC DCC_DEL 0.000 1.673 13 clk2 NET DELAY 0.435 2.108 13 {CNT2_e3_e3_e3_20__i5.ff_inst/CLK CNT2_e3_e3_e3_20__i6.ff_inst/CLK} CLOCK PIN 0.000 2.108 1 Data Path { "path_begin": { "type":"pin", "log_name":"CNT2_e3_e3_e3_20__i5.ff_inst/Q", "phy_name":"SLICE_3/Q0" }, "path_end": { "type":"pin", "log_name":"CNT2_d_i6.ff_inst/DF", "phy_name":"CNT2_d_i6.SLICE_9/M0" }, "path_sections":[ { "type":"site_delay", "pin0": { "log_name":"CNT2_e3_e3_e3_20__i5.ff_inst/CLK", "phy_name":"SLICE_3/CLK" }, "pin1": { "log_name":"CNT2_e3_e3_e3_20__i5.ff_inst/Q", "phy_name":"SLICE_3/Q0" }, "arrive":2.413, "delay":0.305 }, { "type":"net_delay", "net": { "log_name":"CNT2[5]", "phy_name":"CNT2[5]" }, "arrive":2.848, "delay":0.435 }, { "type":"site_delay", "pin0": { "log_name":"", "phy_name":"" }, "pin1": { "log_name":"", "phy_name":"" }, "arrive":2.848, "delay":0.000 } ] } Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- -------------- ---------------- --------- --------------------- ------ CNT2_e3_e3_e3_20__i5.ff_inst/CLK->CNT2_e3_e3_e3_20__i5.ff_inst/Q SLICE REG_DEL 0.305 2.413 2 CNT2[5] NET DELAY 0.435 2.848 2 CNT2_d_i6.ff_inst/DF ENDPOINT 0.000 2.848 1 Destination Clock Path { "path_begin": { "type":"port", "log_name":"Clk", "phy_name":"Clk" }, "path_end": { "type":"pin", "log_name":"CNT2_d_i6.ff_inst/CLK", "phy_name":"CNT2_d_i6.SLICE_9/CLK" }, "path_sections":[ { "type":"site_delay", "pin0": { "log_name":"", "phy_name":"" }, "pin1": { "log_name":"", "phy_name":"" }, "arrive":5.000, "delay":0.000 }, { "type":"net_delay", "net": { "log_name":"Clk", "phy_name":"Clk" }, "arrive":5.000, "delay":0.000 }, { "type":"site_delay", "pin0": { "log_name":"Clk_pad.bb_inst/B", "phy_name":"Clk_pad.bb_inst/IOPAD" }, "pin1": { "log_name":"Clk_pad.bb_inst/O", "phy_name":"Clk_pad.bb_inst/PADDI" }, "arrive":6.159, "delay":1.159 }, { "type":"net_delay", "net": { "log_name":"Clk_c", "phy_name":"Clk_c" }, "arrive":6.594, "delay":0.435 }, { "type":"site_delay", "pin0": { "log_name":"MyDCC/CLKI", "phy_name":"MyDCC/CLKI" }, "pin1": { "log_name":"MyDCC/CLKO", "phy_name":"MyDCC/CLKO" }, "arrive":6.594, "delay":0.000 }, { "type":"net_delay", "net": { "log_name":"clk2", "phy_name":"clk2" }, "arrive":7.029, "delay":0.435 }, { "type":"site_delay", "pin0": { "log_name":"", "phy_name":"" }, "pin1": { "log_name":"", "phy_name":"" }, "arrive":7.029, "delay":0.000 } ] } Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- -------------- ---------------- --------- --------------------- ------ CONSTRAINT 0.000 5.000 1 Clk top CLOCK LATENCY 0.000 5.000 1 Clk NET DELAY 0.000 5.000 1 Clk_pad.bb_inst/B->Clk_pad.bb_inst/O SEIO33_CORE PADI_DEL 1.159 6.159 3 Clk_c NET DELAY 0.435 6.594 3 MyDCC/CLKI->MyDCC/CLKO DCC DCC_DEL 0.000 6.594 13 clk2 NET DELAY 0.435 7.029 13 CNT2_d_i6.ff_inst/CLK CLOCK PIN 0.000 7.029 1 Uncertainty -(0.000) 7.029 Common Path Skew 0.000 7.029 Setup time -(-0.035) 7.064 ---------------------------------------- -------------- ---------------- --------- --------------------- ------ Required Time 7.064 Arrival Time -(2.848) ---------------------------------------- -------------- ---------------- --------- --------------------- ------ Path Slack (Passed) 4.216 ++++ Path 8 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Path Begin : CNT2_e3_e3_e3_20__i7.ff_inst/Q (SLICE) Path End : CNT2_d_i8.ff_inst/DF (SLICE) Source Clock : CLK2 (R) Destination Clock: CLK2 (F) Logic Level : 1 Delay Ratio : 58.8% (route), 41.2% (logic) Clock Skew : -0.079 ns Setup Constraint : 5.000 ns Common Path Skew : 0.000 ns Path Slack : 4.216 ns (Passed) Source Clock Path { "path_begin": { "type":"port", "log_name":"Clk", "phy_name":"Clk" }, "path_end": { "type":"pin", "log_name":"CNT2_e3_e3_e3_20__i7.ff_inst/CLK", "phy_name":"SLICE_4/CLK" }, "path_sections":[ { "type":"net_delay", "net": { "log_name":"Clk", "phy_name":"Clk" }, "arrive":0.000, "delay":0.000 }, { "type":"site_delay", "pin0": { "log_name":"Clk_pad.bb_inst/B", "phy_name":"Clk_pad.bb_inst/IOPAD" }, "pin1": { "log_name":"Clk_pad.bb_inst/O", "phy_name":"Clk_pad.bb_inst/PADDI" }, "arrive":1.238, "delay":1.238 }, { "type":"net_delay", "net": { "log_name":"Clk_c", "phy_name":"Clk_c" }, "arrive":1.673, "delay":0.435 }, { "type":"site_delay", "pin0": { "log_name":"MyDCC/CLKI", "phy_name":"MyDCC/CLKI" }, "pin1": { "log_name":"MyDCC/CLKO", "phy_name":"MyDCC/CLKO" }, "arrive":1.673, "delay":0.000 }, { "type":"net_delay", "net": { "log_name":"clk2", "phy_name":"clk2" }, "arrive":2.108, "delay":0.435 }, { "type":"site_delay", "pin0": { "log_name":"", "phy_name":"" }, "pin1": { "log_name":"", "phy_name":"" }, "arrive":2.108, "delay":0.000 } ] } Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- -------------- ---------------- --------- --------------------- ------ Clk top CLOCK LATENCY 0.000 0.000 1 Clk NET DELAY 0.000 0.000 1 Clk_pad.bb_inst/B->Clk_pad.bb_inst/O SEIO33_CORE PADI_DEL 1.238 1.238 3 Clk_c NET DELAY 0.435 1.673 3 MyDCC/CLKI->MyDCC/CLKO DCC DCC_DEL 0.000 1.673 13 clk2 NET DELAY 0.435 2.108 13 CNT2_e3_e3_e3_20__i7.ff_inst/CLK CLOCK PIN 0.000 2.108 1 Data Path { "path_begin": { "type":"pin", "log_name":"CNT2_e3_e3_e3_20__i7.ff_inst/Q", "phy_name":"SLICE_4/Q0" }, "path_end": { "type":"pin", "log_name":"CNT2_d_i8.ff_inst/DF", "phy_name":"CNT2_d_i8.SLICE_6/M0" }, "path_sections":[ { "type":"site_delay", "pin0": { "log_name":"CNT2_e3_e3_e3_20__i7.ff_inst/CLK", "phy_name":"SLICE_4/CLK" }, "pin1": { "log_name":"CNT2_e3_e3_e3_20__i7.ff_inst/Q", "phy_name":"SLICE_4/Q0" }, "arrive":2.413, "delay":0.305 }, { "type":"net_delay", "net": { "log_name":"CNT2[7]", "phy_name":"CNT2[7]" }, "arrive":2.848, "delay":0.435 }, { "type":"site_delay", "pin0": { "log_name":"", "phy_name":"" }, "pin1": { "log_name":"", "phy_name":"" }, "arrive":2.848, "delay":0.000 } ] } Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- -------------- ---------------- --------- --------------------- ------ CNT2_e3_e3_e3_20__i7.ff_inst/CLK->CNT2_e3_e3_e3_20__i7.ff_inst/Q SLICE REG_DEL 0.305 2.413 2 CNT2[7] NET DELAY 0.435 2.848 2 CNT2_d_i8.ff_inst/DF ENDPOINT 0.000 2.848 1 Destination Clock Path { "path_begin": { "type":"port", "log_name":"Clk", "phy_name":"Clk" }, "path_end": { "type":"pin", "log_name":"CNT2_d_i8.ff_inst/CLK", "phy_name":"CNT2_d_i8.SLICE_6/CLK" }, "path_sections":[ { "type":"site_delay", "pin0": { "log_name":"", "phy_name":"" }, "pin1": { "log_name":"", "phy_name":"" }, "arrive":5.000, "delay":0.000 }, { "type":"net_delay", "net": { "log_name":"Clk", "phy_name":"Clk" }, "arrive":5.000, "delay":0.000 }, { "type":"site_delay", "pin0": { "log_name":"Clk_pad.bb_inst/B", "phy_name":"Clk_pad.bb_inst/IOPAD" }, "pin1": { "log_name":"Clk_pad.bb_inst/O", "phy_name":"Clk_pad.bb_inst/PADDI" }, "arrive":6.159, "delay":1.159 }, { "type":"net_delay", "net": { "log_name":"Clk_c", "phy_name":"Clk_c" }, "arrive":6.594, "delay":0.435 }, { "type":"site_delay", "pin0": { "log_name":"MyDCC/CLKI", "phy_name":"MyDCC/CLKI" }, "pin1": { "log_name":"MyDCC/CLKO", "phy_name":"MyDCC/CLKO" }, "arrive":6.594, "delay":0.000 }, { "type":"net_delay", "net": { "log_name":"clk2", "phy_name":"clk2" }, "arrive":7.029, "delay":0.435 }, { "type":"site_delay", "pin0": { "log_name":"", "phy_name":"" }, "pin1": { "log_name":"", "phy_name":"" }, "arrive":7.029, "delay":0.000 } ] } Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- -------------- ---------------- --------- --------------------- ------ CONSTRAINT 0.000 5.000 1 Clk top CLOCK LATENCY 0.000 5.000 1 Clk NET DELAY 0.000 5.000 1 Clk_pad.bb_inst/B->Clk_pad.bb_inst/O SEIO33_CORE PADI_DEL 1.159 6.159 3 Clk_c NET DELAY 0.435 6.594 3 MyDCC/CLKI->MyDCC/CLKO DCC DCC_DEL 0.000 6.594 13 clk2 NET DELAY 0.435 7.029 13 CNT2_d_i8.ff_inst/CLK CLOCK PIN 0.000 7.029 1 Uncertainty -(0.000) 7.029 Common Path Skew 0.000 7.029 Setup time -(-0.035) 7.064 ---------------------------------------- -------------- ---------------- --------- --------------------- ------ Required Time 7.064 Arrival Time -(2.848) ---------------------------------------- -------------- ---------------- --------- --------------------- ------ Path Slack (Passed) 4.216 ++++ Path 9 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Path Begin : CNT1_e3_e3_e3_21__i0.ff_inst/Q (SLICE) Path End : MyDCC/CE (DCC) Source Clock : CLK1 (R) Destination Clock: CLK1 (R) Logic Level : 2 Delay Ratio : 62.7% (route), 37.3% (logic) Clock Skew : 0.000 ns Setup Constraint : 10.000 ns Common Path Skew : 0.000 ns Path Slack : 8.612 ns (Passed) Source Clock Path { "path_begin": { "type":"port", "log_name":"Clk", "phy_name":"Clk" }, "path_end": { "type":"pin", "log_name":"CNT1_e3_e3_e3_21__i0.ff_inst/CLK", "phy_name":"SLICE_8/CLK" }, "path_sections":[ { "type":"net_delay", "net": { "log_name":"Clk", "phy_name":"Clk" }, "arrive":0.000, "delay":0.000 }, { "type":"site_delay", "pin0": { "log_name":"Clk_pad.bb_inst/B", "phy_name":"Clk_pad.bb_inst/IOPAD" }, "pin1": { "log_name":"Clk_pad.bb_inst/O", "phy_name":"Clk_pad.bb_inst/PADDI" }, "arrive":1.238, "delay":1.238 }, { "type":"net_delay", "net": { "log_name":"Clk_c", "phy_name":"Clk_c" }, "arrive":1.673, "delay":0.435 }, { "type":"site_delay", "pin0": { "log_name":"", "phy_name":"" }, "pin1": { "log_name":"", "phy_name":"" }, "arrive":1.673, "delay":0.000 } ] } Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- -------------- ---------------- -------- --------------------- ------ Clk top CLOCK LATENCY 0.000 0.000 1 Clk NET DELAY 0.000 0.000 1 Clk_pad.bb_inst/B->Clk_pad.bb_inst/O SEIO33_CORE PADI_DEL 1.238 1.238 3 Clk_c NET DELAY 0.435 1.673 3 CNT1_e3_e3_e3_21__i0.ff_inst/CLK CLOCK PIN 0.000 1.673 1 Data Path { "path_begin": { "type":"pin", "log_name":"CNT1_e3_e3_e3_21__i0.ff_inst/Q", "phy_name":"SLICE_8/Q0" }, "path_end": { "type":"pin", "log_name":"MyDCC/CE", "phy_name":"MyDCC/CE" }, "path_sections":[ { "type":"site_delay", "pin0": { "log_name":"CNT1_e3_e3_e3_21__i0.ff_inst/CLK", "phy_name":"SLICE_8/CLK" }, "pin1": { "log_name":"CNT1_e3_e3_e3_21__i0.ff_inst/Q", "phy_name":"SLICE_8/Q0" }, "arrive":1.978, "delay":0.305 }, { "type":"net_delay", "net": { "log_name":"CNT1[0]", "phy_name":"CNT1[0]" }, "arrive":2.413, "delay":0.435 }, { "type":"site_delay", "pin0": { "log_name":"i25_2_lut/A", "phy_name":"SLICE_15/A0" }, "pin1": { "log_name":"i25_2_lut/Z", "phy_name":"SLICE_15/F0" }, "arrive":2.626, "delay":0.213 }, { "type":"net_delay", "net": { "log_name":"Enable", "phy_name":"Enable" }, "arrive":3.061, "delay":0.435 }, { "type":"site_delay", "pin0": { "log_name":"", "phy_name":"" }, "pin1": { "log_name":"", "phy_name":"" }, "arrive":3.061, "delay":0.000 } ] } Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- -------------- ---------------- -------- --------------------- ------ CNT1_e3_e3_e3_21__i0.ff_inst/CLK->CNT1_e3_e3_e3_21__i0.ff_inst/Q SLICE REG_DEL 0.305 1.978 3 CNT1[0] NET DELAY 0.435 2.413 3 i25_2_lut/A->i25_2_lut/Z SLICE CTOF_DEL 0.213 2.626 1 Enable NET DELAY 0.435 3.061 1 MyDCC/CE ENDPOINT 0.000 3.061 1 Destination Clock Path { "path_begin": { "type":"port", "log_name":"Clk", "phy_name":"Clk" }, "path_end": { "type":"pin", "log_name":"MyDCC/CLKI", "phy_name":"MyDCC/CLKI" }, "path_sections":[ { "type":"site_delay", "pin0": { "log_name":"", "phy_name":"" }, "pin1": { "log_name":"", "phy_name":"" }, "arrive":10.000, "delay":0.000 }, { "type":"net_delay", "net": { "log_name":"Clk", "phy_name":"Clk" }, "arrive":10.000, "delay":0.000 }, { "type":"site_delay", "pin0": { "log_name":"Clk_pad.bb_inst/B", "phy_name":"Clk_pad.bb_inst/IOPAD" }, "pin1": { "log_name":"Clk_pad.bb_inst/O", "phy_name":"Clk_pad.bb_inst/PADDI" }, "arrive":11.238, "delay":1.238 }, { "type":"net_delay", "net": { "log_name":"Clk_c", "phy_name":"Clk_c" }, "arrive":11.673, "delay":0.435 }, { "type":"site_delay", "pin0": { "log_name":"", "phy_name":"" }, "pin1": { "log_name":"", "phy_name":"" }, "arrive":11.673, "delay":0.000 } ] } Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- -------------- ---------------- -------- --------------------- ------ CONSTRAINT 0.000 10.000 1 Clk top CLOCK LATENCY 0.000 10.000 1 Clk NET DELAY 0.000 10.000 1 Clk_pad.bb_inst/B->Clk_pad.bb_inst/O SEIO33_CORE PADI_DEL 1.238 11.238 3 Clk_c NET DELAY 0.435 11.673 3 MyDCC/CLKI CLOCK PIN 0.000 11.673 1 Uncertainty -(0.000) 11.673 Common Path Skew 0.000 11.673 Setup time -(0.000) 11.673 ---------------------------------------- -------------- ---------------- -------- --------------------- ------ Required Time 11.673 Arrival Time -(3.061) ---------------------------------------- -------------- ---------------- -------- --------------------- ------ Path Slack (Passed) 8.612 ++++ Path 10 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Path Begin : CNT1_e3_e3_e3_21__i0.ff_inst/Q (SLICE) Path End : CNT1_e3_e3_e3_21__i1.ff_inst/DF (SLICE) Source Clock : CLK1 (R) Destination Clock: CLK1 (R) Logic Level : 2 Delay Ratio : 45.6% (route), 54.4% (logic) Clock Skew : 0.000 ns Setup Constraint : 10.000 ns Common Path Skew : 0.000 ns Path Slack : 9.105 ns (Passed) Source Clock Path { "path_begin": { "type":"port", "log_name":"Clk", "phy_name":"Clk" }, "path_end": { "type":"pin", "log_name":"CNT1_e3_e3_e3_21__i0.ff_inst/CLK", "phy_name":"SLICE_8/CLK" }, "path_sections":[ { "type":"net_delay", "net": { "log_name":"Clk", "phy_name":"Clk" }, "arrive":0.000, "delay":0.000 }, { "type":"site_delay", "pin0": { "log_name":"Clk_pad.bb_inst/B", "phy_name":"Clk_pad.bb_inst/IOPAD" }, "pin1": { "log_name":"Clk_pad.bb_inst/O", "phy_name":"Clk_pad.bb_inst/PADDI" }, "arrive":1.238, "delay":1.238 }, { "type":"net_delay", "net": { "log_name":"Clk_c", "phy_name":"Clk_c" }, "arrive":1.673, "delay":0.435 }, { "type":"site_delay", "pin0": { "log_name":"", "phy_name":"" }, "pin1": { "log_name":"", "phy_name":"" }, "arrive":1.673, "delay":0.000 } ] } Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- -------------- ---------------- --------- --------------------- ------ Clk top CLOCK LATENCY 0.000 0.000 1 Clk NET DELAY 0.000 0.000 1 Clk_pad.bb_inst/B->Clk_pad.bb_inst/O SEIO33_CORE PADI_DEL 1.238 1.238 3 Clk_c NET DELAY 0.435 1.673 3 CNT1_e3_e3_e3_21__i0.ff_inst/CLK CLOCK PIN 0.000 1.673 1 Data Path { "path_begin": { "type":"pin", "log_name":"CNT1_e3_e3_e3_21__i0.ff_inst/Q", "phy_name":"SLICE_8/Q0" }, "path_end": { "type":"pin", "log_name":"CNT1_e3_e3_e3_21__i1.ff_inst/DF", "phy_name":"SLICE_5/DI0" }, "path_sections":[ { "type":"site_delay", "pin0": { "log_name":"CNT1_e3_e3_e3_21__i0.ff_inst/CLK", "phy_name":"SLICE_8/CLK" }, "pin1": { "log_name":"CNT1_e3_e3_e3_21__i0.ff_inst/Q", "phy_name":"SLICE_8/Q0" }, "arrive":1.978, "delay":0.305 }, { "type":"net_delay", "net": { "log_name":"CNT1[0]", "phy_name":"CNT1[0]" }, "arrive":2.413, "delay":0.435 }, { "type":"site_delay", "pin0": { "log_name":"i36_2_lut/B", "phy_name":"SLICE_5/B0" }, "pin1": { "log_name":"i36_2_lut/Z", "phy_name":"SLICE_5/F0" }, "arrive":2.626, "delay":0.213 }, { "type":"net_delay", "net": { "log_name":"n14", "phy_name":"n14" }, "arrive":2.626, "delay":0.000 }, { "type":"site_delay", "pin0": { "log_name":"", "phy_name":"" }, "pin1": { "log_name":"", "phy_name":"" }, "arrive":2.626, "delay":0.000 } ] } Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- -------------- ---------------- --------- --------------------- ------ CNT1_e3_e3_e3_21__i0.ff_inst/CLK->CNT1_e3_e3_e3_21__i0.ff_inst/Q SLICE REG_DEL 0.305 1.978 3 CNT1[0] NET DELAY 0.435 2.413 3 i36_2_lut/B->i36_2_lut/Z SLICE CTOF_DEL 0.213 2.626 1 n14 NET DELAY 0.000 2.626 1 CNT1_e3_e3_e3_21__i1.ff_inst/DF ENDPOINT 0.000 2.626 1 Destination Clock Path { "path_begin": { "type":"port", "log_name":"Clk", "phy_name":"Clk" }, "path_end": { "type":"pin", "log_name":"CNT1_e3_e3_e3_21__i1.ff_inst/CLK", "phy_name":"SLICE_5/CLK" }, "path_sections":[ { "type":"site_delay", "pin0": { "log_name":"", "phy_name":"" }, "pin1": { "log_name":"", "phy_name":"" }, "arrive":10.000, "delay":0.000 }, { "type":"net_delay", "net": { "log_name":"Clk", "phy_name":"Clk" }, "arrive":10.000, "delay":0.000 }, { "type":"site_delay", "pin0": { "log_name":"Clk_pad.bb_inst/B", "phy_name":"Clk_pad.bb_inst/IOPAD" }, "pin1": { "log_name":"Clk_pad.bb_inst/O", "phy_name":"Clk_pad.bb_inst/PADDI" }, "arrive":11.238, "delay":1.238 }, { "type":"net_delay", "net": { "log_name":"Clk_c", "phy_name":"Clk_c" }, "arrive":11.673, "delay":0.435 }, { "type":"site_delay", "pin0": { "log_name":"", "phy_name":"" }, "pin1": { "log_name":"", "phy_name":"" }, "arrive":11.673, "delay":0.000 } ] } Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- -------------- ---------------- --------- --------------------- ------ CONSTRAINT 0.000 10.000 1 Clk top CLOCK LATENCY 0.000 10.000 1 Clk NET DELAY 0.000 10.000 1 Clk_pad.bb_inst/B->Clk_pad.bb_inst/O SEIO33_CORE PADI_DEL 1.238 11.238 3 Clk_c NET DELAY 0.435 11.673 3 CNT1_e3_e3_e3_21__i1.ff_inst/CLK CLOCK PIN 0.000 11.673 1 Uncertainty -(0.000) 11.673 Common Path Skew 0.000 11.673 Setup time -(-0.058) 11.731 ---------------------------------------- -------------- ---------------- --------- --------------------- ------ Required Time 11.731 Arrival Time -(2.626) ---------------------------------------- -------------- ---------------- --------- --------------------- ------ Path Slack (Passed) 9.105 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ End of Detailed Report for timing paths +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ ########################################################## 4 Hold at Speed Grade m Corner at 0 Degrees 4.1 Endpoint slacks ------------------------------------------------------- Listing 10 End Points | Slack ------------------------------------------------------- CNT1_e3_e3_e3_21__i0.ff_inst/DF | 0.610 ns CNT1_e3_e3_e3_21__i1.ff_inst/DF | 0.610 ns CNT2_e3_e3_e3_20__i7.ff_inst/DF | 0.610 ns CNT2_e3_e3_e3_20__i5.ff_inst/DF | 0.610 ns CNT2_e3_e3_e3_20__i1.ff_inst/DF | 0.610 ns CNT2_e3_e3_e3_20__i3.ff_inst/DF | 0.610 ns CNT2_e3_e3_e3_20__i6.ff_inst/DF | 0.611 ns CNT2_e3_e3_e3_20__i2.ff_inst/DF | 0.611 ns CNT2_e3_e3_e3_20__i0.ff_inst/DF | 0.611 ns CNT2_e3_e3_e3_20__i4.ff_inst/DF | 0.611 ns ------------------------------------------------------- | Hold # of endpoints with negative slack: | 0 | ------------------------------------------------------- 4.2 Detailed Report XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX Detail report of critical paths XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Detailed Report for timing paths +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ ++++Path 1 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Path Begin : CNT1_e3_e3_e3_21__i0.ff_inst/Q (SLICE) Path End : CNT1_e3_e3_e3_21__i0.ff_inst/DF (SLICE) Source Clock : CLK1 (R) Destination Clock: CLK1 (R) Logic Level : 2 Delay Ratio : 60.1% (route), 39.9% (logic) Clock Skew : 0.000 ns Hold Constraint : 0.000 ns Common Path Skew : 0.000 ns Path Slack : 0.610 ns (Passed) Source Clock Path { "path_begin": { "type":"port", "log_name":"Clk", "phy_name":"Clk" }, "path_end": { "type":"pin", "log_name":"CNT1_e3_e3_e3_21__i0.ff_inst/CLK", "phy_name":"SLICE_8/CLK" }, "path_sections":[ { "type":"net_delay", "net": { "log_name":"Clk", "phy_name":"Clk" }, "arrive":0.000, "delay":0.000 }, { "type":"site_delay", "pin0": { "log_name":"Clk_pad.bb_inst/B", "phy_name":"Clk_pad.bb_inst/IOPAD" }, "pin1": { "log_name":"Clk_pad.bb_inst/O", "phy_name":"Clk_pad.bb_inst/PADDI" }, "arrive":1.000, "delay":1.000 }, { "type":"net_delay", "net": { "log_name":"Clk_c", "phy_name":"Clk_c" }, "arrive":1.435, "delay":0.435 }, { "type":"site_delay", "pin0": { "log_name":"", "phy_name":"" }, "pin1": { "log_name":"", "phy_name":"" }, "arrive":1.435, "delay":0.000 } ] } Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- -------------- ---------------- ----- --------------------- ------ Clk top CLOCK LATENCY 0.000 0.000 1 Clk NET DELAY 0.000 0.000 1 Clk_pad.bb_inst/B->Clk_pad.bb_inst/O SEIO33_CORE PADI_DEL 1.000 1.000 3 Clk_c NET DELAY 0.435 1.435 3 CNT1_e3_e3_e3_21__i0.ff_inst/CLK CLOCK PIN 0.000 1.435 1 Data Path { "path_begin": { "type":"pin", "log_name":"CNT1_e3_e3_e3_21__i0.ff_inst/Q", "phy_name":"SLICE_8/Q0" }, "path_end": { "type":"pin", "log_name":"CNT1_e3_e3_e3_21__i0.ff_inst/DF", "phy_name":"SLICE_8/DI0" }, "path_sections":[ { "type":"site_delay", "pin0": { "log_name":"CNT1_e3_e3_e3_21__i0.ff_inst/CLK", "phy_name":"SLICE_8/CLK" }, "pin1": { "log_name":"CNT1_e3_e3_e3_21__i0.ff_inst/Q", "phy_name":"SLICE_8/Q0" }, "arrive":1.608, "delay":0.173 }, { "type":"net_delay", "net": { "log_name":"CNT1[0]", "phy_name":"CNT1[0]" }, "arrive":2.043, "delay":0.435 }, { "type":"site_delay", "pin0": { "log_name":"i34_1_lut/A", "phy_name":"SLICE_8/A0" }, "pin1": { "log_name":"i34_1_lut/Z", "phy_name":"SLICE_8/F0" }, "arrive":2.159, "delay":0.116 }, { "type":"net_delay", "net": { "log_name":"n15", "phy_name":"n15" }, "arrive":2.159, "delay":0.000 }, { "type":"site_delay", "pin0": { "log_name":"", "phy_name":"" }, "pin1": { "log_name":"", "phy_name":"" }, "arrive":2.159, "delay":0.000 } ] } Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- -------------- ---------------- ----- --------------------- ------ CNT1_e3_e3_e3_21__i0.ff_inst/CLK->CNT1_e3_e3_e3_21__i0.ff_inst/Q SLICE REG_DEL 0.173 1.608 3 CNT1[0] NET DELAY 0.435 2.043 3 i34_1_lut/A->i34_1_lut/Z SLICE CTOF_DEL 0.116 2.159 1 n15 NET DELAY 0.000 2.159 1 CNT1_e3_e3_e3_21__i0.ff_inst/DF ENDPOINT 0.000 2.159 1 Destination Clock Path { "path_begin": { "type":"port", "log_name":"Clk", "phy_name":"Clk" }, "path_end": { "type":"pin", "log_name":"CNT1_e3_e3_e3_21__i0.ff_inst/CLK", "phy_name":"SLICE_8/CLK" }, "path_sections":[ { "type":"site_delay", "pin0": { "log_name":"", "phy_name":"" }, "pin1": { "log_name":"", "phy_name":"" }, "arrive":0.000, "delay":0.000 }, { "type":"net_delay", "net": { "log_name":"Clk", "phy_name":"Clk" }, "arrive":0.000, "delay":0.000 }, { "type":"site_delay", "pin0": { "log_name":"Clk_pad.bb_inst/B", "phy_name":"Clk_pad.bb_inst/IOPAD" }, "pin1": { "log_name":"Clk_pad.bb_inst/O", "phy_name":"Clk_pad.bb_inst/PADDI" }, "arrive":1.000, "delay":1.000 }, { "type":"net_delay", "net": { "log_name":"Clk_c", "phy_name":"Clk_c" }, "arrive":1.435, "delay":0.435 }, { "type":"site_delay", "pin0": { "log_name":"", "phy_name":"" }, "pin1": { "log_name":"", "phy_name":"" }, "arrive":1.435, "delay":0.000 } ] } Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- -------------- ---------------- ----- --------------------- ------ CONSTRAINT 0.000 0.000 1 Clk top CLOCK LATENCY 0.000 0.000 1 Clk NET DELAY 0.000 0.000 1 Clk_pad.bb_inst/B->Clk_pad.bb_inst/O SEIO33_CORE PADI_DEL 1.000 1.000 3 Clk_c NET DELAY 0.435 1.435 3 CNT1_e3_e3_e3_21__i0.ff_inst/CLK CLOCK PIN 0.000 1.435 1 Uncertainty 0.000 1.435 Common Path Skew 0.000 1.435 Hold time 0.114 1.549 ---------------------------------------- -------------- ---------------- ----- --------------------- ------ Required Time -1.549 Arrival Time 2.159 ---------------------------------------- -------------- ---------------- ----- --------------------- ------ Path Slack (Passed) 0.610 ++++ Path 2 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Path Begin : CNT1_e3_e3_e3_21__i0.ff_inst/Q (SLICE) Path End : CNT1_e3_e3_e3_21__i1.ff_inst/DF (SLICE) Source Clock : CLK1 (R) Destination Clock: CLK1 (R) Logic Level : 2 Delay Ratio : 60.1% (route), 39.9% (logic) Clock Skew : 0.000 ns Hold Constraint : 0.000 ns Common Path Skew : 0.000 ns Path Slack : 0.610 ns (Passed) Source Clock Path { "path_begin": { "type":"port", "log_name":"Clk", "phy_name":"Clk" }, "path_end": { "type":"pin", "log_name":"CNT1_e3_e3_e3_21__i0.ff_inst/CLK", "phy_name":"SLICE_8/CLK" }, "path_sections":[ { "type":"net_delay", "net": { "log_name":"Clk", "phy_name":"Clk" }, "arrive":0.000, "delay":0.000 }, { "type":"site_delay", "pin0": { "log_name":"Clk_pad.bb_inst/B", "phy_name":"Clk_pad.bb_inst/IOPAD" }, "pin1": { "log_name":"Clk_pad.bb_inst/O", "phy_name":"Clk_pad.bb_inst/PADDI" }, "arrive":1.000, "delay":1.000 }, { "type":"net_delay", "net": { "log_name":"Clk_c", "phy_name":"Clk_c" }, "arrive":1.435, "delay":0.435 }, { "type":"site_delay", "pin0": { "log_name":"", "phy_name":"" }, "pin1": { "log_name":"", "phy_name":"" }, "arrive":1.435, "delay":0.000 } ] } Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- -------------- ---------------- ----- --------------------- ------ Clk top CLOCK LATENCY 0.000 0.000 1 Clk NET DELAY 0.000 0.000 1 Clk_pad.bb_inst/B->Clk_pad.bb_inst/O SEIO33_CORE PADI_DEL 1.000 1.000 3 Clk_c NET DELAY 0.435 1.435 3 CNT1_e3_e3_e3_21__i0.ff_inst/CLK CLOCK PIN 0.000 1.435 1 Data Path { "path_begin": { "type":"pin", "log_name":"CNT1_e3_e3_e3_21__i0.ff_inst/Q", "phy_name":"SLICE_8/Q0" }, "path_end": { "type":"pin", "log_name":"CNT1_e3_e3_e3_21__i1.ff_inst/DF", "phy_name":"SLICE_5/DI0" }, "path_sections":[ { "type":"site_delay", "pin0": { "log_name":"CNT1_e3_e3_e3_21__i0.ff_inst/CLK", "phy_name":"SLICE_8/CLK" }, "pin1": { "log_name":"CNT1_e3_e3_e3_21__i0.ff_inst/Q", "phy_name":"SLICE_8/Q0" }, "arrive":1.608, "delay":0.173 }, { "type":"net_delay", "net": { "log_name":"CNT1[0]", "phy_name":"CNT1[0]" }, "arrive":2.043, "delay":0.435 }, { "type":"site_delay", "pin0": { "log_name":"i36_2_lut/B", "phy_name":"SLICE_5/B0" }, "pin1": { "log_name":"i36_2_lut/Z", "phy_name":"SLICE_5/F0" }, "arrive":2.159, "delay":0.116 }, { "type":"net_delay", "net": { "log_name":"n14", "phy_name":"n14" }, "arrive":2.159, "delay":0.000 }, { "type":"site_delay", "pin0": { "log_name":"", "phy_name":"" }, "pin1": { "log_name":"", "phy_name":"" }, "arrive":2.159, "delay":0.000 } ] } Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- -------------- ---------------- ----- --------------------- ------ CNT1_e3_e3_e3_21__i0.ff_inst/CLK->CNT1_e3_e3_e3_21__i0.ff_inst/Q SLICE REG_DEL 0.173 1.608 3 CNT1[0] NET DELAY 0.435 2.043 3 i36_2_lut/B->i36_2_lut/Z SLICE CTOF_DEL 0.116 2.159 1 n14 NET DELAY 0.000 2.159 1 CNT1_e3_e3_e3_21__i1.ff_inst/DF ENDPOINT 0.000 2.159 1 Destination Clock Path { "path_begin": { "type":"port", "log_name":"Clk", "phy_name":"Clk" }, "path_end": { "type":"pin", "log_name":"CNT1_e3_e3_e3_21__i1.ff_inst/CLK", "phy_name":"SLICE_5/CLK" }, "path_sections":[ { "type":"site_delay", "pin0": { "log_name":"", "phy_name":"" }, "pin1": { "log_name":"", "phy_name":"" }, "arrive":0.000, "delay":0.000 }, { "type":"net_delay", "net": { "log_name":"Clk", "phy_name":"Clk" }, "arrive":0.000, "delay":0.000 }, { "type":"site_delay", "pin0": { "log_name":"Clk_pad.bb_inst/B", "phy_name":"Clk_pad.bb_inst/IOPAD" }, "pin1": { "log_name":"Clk_pad.bb_inst/O", "phy_name":"Clk_pad.bb_inst/PADDI" }, "arrive":1.000, "delay":1.000 }, { "type":"net_delay", "net": { "log_name":"Clk_c", "phy_name":"Clk_c" }, "arrive":1.435, "delay":0.435 }, { "type":"site_delay", "pin0": { "log_name":"", "phy_name":"" }, "pin1": { "log_name":"", "phy_name":"" }, "arrive":1.435, "delay":0.000 } ] } Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- -------------- ---------------- ----- --------------------- ------ CONSTRAINT 0.000 0.000 1 Clk top CLOCK LATENCY 0.000 0.000 1 Clk NET DELAY 0.000 0.000 1 Clk_pad.bb_inst/B->Clk_pad.bb_inst/O SEIO33_CORE PADI_DEL 1.000 1.000 3 Clk_c NET DELAY 0.435 1.435 3 CNT1_e3_e3_e3_21__i1.ff_inst/CLK CLOCK PIN 0.000 1.435 1 Uncertainty 0.000 1.435 Common Path Skew 0.000 1.435 Hold time 0.114 1.549 ---------------------------------------- -------------- ---------------- ----- --------------------- ------ Required Time -1.549 Arrival Time 2.159 ---------------------------------------- -------------- ---------------- ----- --------------------- ------ Path Slack (Passed) 0.610 ++++ Path 3 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Path Begin : CNT2_e3_e3_e3_20__i7.ff_inst/Q (SLICE) Path End : CNT2_e3_e3_e3_20__i7.ff_inst/DF (SLICE) Source Clock : CLK2 (R) Destination Clock: CLK2 (R) Logic Level : 2 Delay Ratio : 60.1% (route), 39.9% (logic) Clock Skew : 0.000 ns Hold Constraint : 0.000 ns Common Path Skew : 0.000 ns Path Slack : 0.610 ns (Passed) Source Clock Path { "path_begin": { "type":"port", "log_name":"Clk", "phy_name":"Clk" }, "path_end": { "type":"pin", "log_name":"CNT2_e3_e3_e3_20__i7.ff_inst/CLK", "phy_name":"SLICE_4/CLK" }, "path_sections":[ { "type":"net_delay", "net": { "log_name":"Clk", "phy_name":"Clk" }, "arrive":0.000, "delay":0.000 }, { "type":"site_delay", "pin0": { "log_name":"Clk_pad.bb_inst/B", "phy_name":"Clk_pad.bb_inst/IOPAD" }, "pin1": { "log_name":"Clk_pad.bb_inst/O", "phy_name":"Clk_pad.bb_inst/PADDI" }, "arrive":1.000, "delay":1.000 }, { "type":"net_delay", "net": { "log_name":"Clk_c", "phy_name":"Clk_c" }, "arrive":1.435, "delay":0.435 }, { "type":"site_delay", "pin0": { "log_name":"MyDCC/CLKI", "phy_name":"MyDCC/CLKI" }, "pin1": { "log_name":"MyDCC/CLKO", "phy_name":"MyDCC/CLKO" }, "arrive":1.435, "delay":0.000 }, { "type":"net_delay", "net": { "log_name":"clk2", "phy_name":"clk2" }, "arrive":1.870, "delay":0.435 }, { "type":"site_delay", "pin0": { "log_name":"", "phy_name":"" }, "pin1": { "log_name":"", "phy_name":"" }, "arrive":1.870, "delay":0.000 } ] } Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- -------------- ---------------- ----- --------------------- ------ Clk top CLOCK LATENCY 0.000 0.000 1 Clk NET DELAY 0.000 0.000 1 Clk_pad.bb_inst/B->Clk_pad.bb_inst/O SEIO33_CORE PADI_DEL 1.000 1.000 3 Clk_c NET DELAY 0.435 1.435 3 MyDCC/CLKI->MyDCC/CLKO DCC DCC_DEL 0.000 1.435 13 clk2 NET DELAY 0.435 1.870 13 CNT2_e3_e3_e3_20__i7.ff_inst/CLK CLOCK PIN 0.000 1.870 1 Data Path { "path_begin": { "type":"pin", "log_name":"CNT2_e3_e3_e3_20__i7.ff_inst/Q", "phy_name":"SLICE_4/Q0" }, "path_end": { "type":"pin", "log_name":"CNT2_e3_e3_e3_20__i7.ff_inst/DF", "phy_name":"SLICE_4/DI0" }, "path_sections":[ { "type":"site_delay", "pin0": { "log_name":"CNT2_e3_e3_e3_20__i7.ff_inst/CLK", "phy_name":"SLICE_4/CLK" }, "pin1": { "log_name":"CNT2_e3_e3_e3_20__i7.ff_inst/Q", "phy_name":"SLICE_4/Q0" }, "arrive":2.043, "delay":0.173 }, { "type":"net_delay", "net": { "log_name":"CNT2[7]", "phy_name":"CNT2[7]" }, "arrive":2.478, "delay":0.435 }, { "type":"site_delay", "pin0": { "log_name":"CNT2_e3_e3_e3_20_add_4_9/B0", "phy_name":"SLICE_4/B0" }, "pin1": { "log_name":"CNT2_e3_e3_e3_20_add_4_9/S0", "phy_name":"SLICE_4/F0" }, "arrive":2.594, "delay":0.116 }, { "type":"net_delay", "net": { "log_name":"CNT2_7__N_3[7]", "phy_name":"CNT2_7__N_3[7]" }, "arrive":2.594, "delay":0.000 }, { "type":"site_delay", "pin0": { "log_name":"", "phy_name":"" }, "pin1": { "log_name":"", "phy_name":"" }, "arrive":2.594, "delay":0.000 } ] } Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- -------------- ---------------- ----- --------------------- ------ CNT2_e3_e3_e3_20__i7.ff_inst/CLK->CNT2_e3_e3_e3_20__i7.ff_inst/Q SLICE REG_DEL 0.173 2.043 2 CNT2[7] NET DELAY 0.435 2.478 2 CNT2_e3_e3_e3_20_add_4_9/B0->CNT2_e3_e3_e3_20_add_4_9/S0 SLICE CTOF_DEL 0.116 2.594 1 CNT2_7__N_3[7] NET DELAY 0.000 2.594 1 CNT2_e3_e3_e3_20__i7.ff_inst/DF ENDPOINT 0.000 2.594 1 Destination Clock Path { "path_begin": { "type":"port", "log_name":"Clk", "phy_name":"Clk" }, "path_end": { "type":"pin", "log_name":"CNT2_e3_e3_e3_20__i7.ff_inst/CLK", "phy_name":"SLICE_4/CLK" }, "path_sections":[ { "type":"site_delay", "pin0": { "log_name":"", "phy_name":"" }, "pin1": { "log_name":"", "phy_name":"" }, "arrive":0.000, "delay":0.000 }, { "type":"net_delay", "net": { "log_name":"Clk", "phy_name":"Clk" }, "arrive":0.000, "delay":0.000 }, { "type":"site_delay", "pin0": { "log_name":"Clk_pad.bb_inst/B", "phy_name":"Clk_pad.bb_inst/IOPAD" }, "pin1": { "log_name":"Clk_pad.bb_inst/O", "phy_name":"Clk_pad.bb_inst/PADDI" }, "arrive":1.000, "delay":1.000 }, { "type":"net_delay", "net": { "log_name":"Clk_c", "phy_name":"Clk_c" }, "arrive":1.435, "delay":0.435 }, { "type":"site_delay", "pin0": { "log_name":"MyDCC/CLKI", "phy_name":"MyDCC/CLKI" }, "pin1": { "log_name":"MyDCC/CLKO", "phy_name":"MyDCC/CLKO" }, "arrive":1.435, "delay":0.000 }, { "type":"net_delay", "net": { "log_name":"clk2", "phy_name":"clk2" }, "arrive":1.870, "delay":0.435 }, { "type":"site_delay", "pin0": { "log_name":"", "phy_name":"" }, "pin1": { "log_name":"", "phy_name":"" }, "arrive":1.870, "delay":0.000 } ] } Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- -------------- ---------------- ----- --------------------- ------ CONSTRAINT 0.000 0.000 1 Clk top CLOCK LATENCY 0.000 0.000 1 Clk NET DELAY 0.000 0.000 1 Clk_pad.bb_inst/B->Clk_pad.bb_inst/O SEIO33_CORE PADI_DEL 1.000 1.000 3 Clk_c NET DELAY 0.435 1.435 3 MyDCC/CLKI->MyDCC/CLKO DCC DCC_DEL 0.000 1.435 13 clk2 NET DELAY 0.435 1.870 13 CNT2_e3_e3_e3_20__i7.ff_inst/CLK CLOCK PIN 0.000 1.870 1 Uncertainty 0.000 1.870 Common Path Skew 0.000 1.870 Hold time 0.114 1.984 ---------------------------------------- -------------- ---------------- ----- --------------------- ------ Required Time -1.984 Arrival Time 2.594 ---------------------------------------- -------------- ---------------- ----- --------------------- ------ Path Slack (Passed) 0.610 ++++ Path 4 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Path Begin : CNT2_e3_e3_e3_20__i5.ff_inst/Q (SLICE) Path End : CNT2_e3_e3_e3_20__i5.ff_inst/DF (SLICE) Source Clock : CLK2 (R) Destination Clock: CLK2 (R) Logic Level : 2 Delay Ratio : 60.1% (route), 39.9% (logic) Clock Skew : 0.000 ns Hold Constraint : 0.000 ns Common Path Skew : 0.000 ns Path Slack : 0.610 ns (Passed) Source Clock Path { "path_begin": { "type":"port", "log_name":"Clk", "phy_name":"Clk" }, "path_end": { "type":"pin", "log_name":"CNT2_e3_e3_e3_20__i5.ff_inst/CLK", "phy_name":"SLICE_3/CLK" }, "path_sections":[ { "type":"net_delay", "net": { "log_name":"Clk", "phy_name":"Clk" }, "arrive":0.000, "delay":0.000 }, { "type":"site_delay", "pin0": { "log_name":"Clk_pad.bb_inst/B", "phy_name":"Clk_pad.bb_inst/IOPAD" }, "pin1": { "log_name":"Clk_pad.bb_inst/O", "phy_name":"Clk_pad.bb_inst/PADDI" }, "arrive":1.000, "delay":1.000 }, { "type":"net_delay", "net": { "log_name":"Clk_c", "phy_name":"Clk_c" }, "arrive":1.435, "delay":0.435 }, { "type":"site_delay", "pin0": { "log_name":"MyDCC/CLKI", "phy_name":"MyDCC/CLKI" }, "pin1": { "log_name":"MyDCC/CLKO", "phy_name":"MyDCC/CLKO" }, "arrive":1.435, "delay":0.000 }, { "type":"net_delay", "net": { "log_name":"clk2", "phy_name":"clk2" }, "arrive":1.870, "delay":0.435 }, { "type":"site_delay", "pin0": { "log_name":"", "phy_name":"" }, "pin1": { "log_name":"", "phy_name":"" }, "arrive":1.870, "delay":0.000 } ] } Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- -------------- ---------------- ----- --------------------- ------ Clk top CLOCK LATENCY 0.000 0.000 1 Clk NET DELAY 0.000 0.000 1 Clk_pad.bb_inst/B->Clk_pad.bb_inst/O SEIO33_CORE PADI_DEL 1.000 1.000 3 Clk_c NET DELAY 0.435 1.435 3 MyDCC/CLKI->MyDCC/CLKO DCC DCC_DEL 0.000 1.435 13 clk2 NET DELAY 0.435 1.870 13 {CNT2_e3_e3_e3_20__i5.ff_inst/CLK CNT2_e3_e3_e3_20__i6.ff_inst/CLK} CLOCK PIN 0.000 1.870 1 Data Path { "path_begin": { "type":"pin", "log_name":"CNT2_e3_e3_e3_20__i5.ff_inst/Q", "phy_name":"SLICE_3/Q0" }, "path_end": { "type":"pin", "log_name":"CNT2_e3_e3_e3_20__i5.ff_inst/DF", "phy_name":"SLICE_3/DI0" }, "path_sections":[ { "type":"site_delay", "pin0": { "log_name":"CNT2_e3_e3_e3_20__i5.ff_inst/CLK", "phy_name":"SLICE_3/CLK" }, "pin1": { "log_name":"CNT2_e3_e3_e3_20__i5.ff_inst/Q", "phy_name":"SLICE_3/Q0" }, "arrive":2.043, "delay":0.173 }, { "type":"net_delay", "net": { "log_name":"CNT2[5]", "phy_name":"CNT2[5]" }, "arrive":2.478, "delay":0.435 }, { "type":"site_delay", "pin0": { "log_name":"CNT2_e3_e3_e3_20_add_4_7/B0", "phy_name":"SLICE_3/B0" }, "pin1": { "log_name":"CNT2_e3_e3_e3_20_add_4_7/S0", "phy_name":"SLICE_3/F0" }, "arrive":2.594, "delay":0.116 }, { "type":"net_delay", "net": { "log_name":"CNT2_7__N_3[5]", "phy_name":"CNT2_7__N_3[5]" }, "arrive":2.594, "delay":0.000 }, { "type":"site_delay", "pin0": { "log_name":"", "phy_name":"" }, "pin1": { "log_name":"", "phy_name":"" }, "arrive":2.594, "delay":0.000 } ] } Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- -------------- ---------------- ----- --------------------- ------ CNT2_e3_e3_e3_20__i5.ff_inst/CLK->CNT2_e3_e3_e3_20__i5.ff_inst/Q SLICE REG_DEL 0.173 2.043 2 CNT2[5] NET DELAY 0.435 2.478 2 CNT2_e3_e3_e3_20_add_4_7/B0->CNT2_e3_e3_e3_20_add_4_7/S0 SLICE CTOF_DEL 0.116 2.594 1 CNT2_7__N_3[5] NET DELAY 0.000 2.594 1 CNT2_e3_e3_e3_20__i5.ff_inst/DF ENDPOINT 0.000 2.594 1 Destination Clock Path { "path_begin": { "type":"port", "log_name":"Clk", "phy_name":"Clk" }, "path_end": { "type":"pin", "log_name":"CNT2_e3_e3_e3_20__i5.ff_inst/CLK", "phy_name":"SLICE_3/CLK" }, "path_sections":[ { "type":"site_delay", "pin0": { "log_name":"", "phy_name":"" }, "pin1": { "log_name":"", "phy_name":"" }, "arrive":0.000, "delay":0.000 }, { "type":"net_delay", "net": { "log_name":"Clk", "phy_name":"Clk" }, "arrive":0.000, "delay":0.000 }, { "type":"site_delay", "pin0": { "log_name":"Clk_pad.bb_inst/B", "phy_name":"Clk_pad.bb_inst/IOPAD" }, "pin1": { "log_name":"Clk_pad.bb_inst/O", "phy_name":"Clk_pad.bb_inst/PADDI" }, "arrive":1.000, "delay":1.000 }, { "type":"net_delay", "net": { "log_name":"Clk_c", "phy_name":"Clk_c" }, "arrive":1.435, "delay":0.435 }, { "type":"site_delay", "pin0": { "log_name":"MyDCC/CLKI", "phy_name":"MyDCC/CLKI" }, "pin1": { "log_name":"MyDCC/CLKO", "phy_name":"MyDCC/CLKO" }, "arrive":1.435, "delay":0.000 }, { "type":"net_delay", "net": { "log_name":"clk2", "phy_name":"clk2" }, "arrive":1.870, "delay":0.435 }, { "type":"site_delay", "pin0": { "log_name":"", "phy_name":"" }, "pin1": { "log_name":"", "phy_name":"" }, "arrive":1.870, "delay":0.000 } ] } Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- -------------- ---------------- ----- --------------------- ------ CONSTRAINT 0.000 0.000 1 Clk top CLOCK LATENCY 0.000 0.000 1 Clk NET DELAY 0.000 0.000 1 Clk_pad.bb_inst/B->Clk_pad.bb_inst/O SEIO33_CORE PADI_DEL 1.000 1.000 3 Clk_c NET DELAY 0.435 1.435 3 MyDCC/CLKI->MyDCC/CLKO DCC DCC_DEL 0.000 1.435 13 clk2 NET DELAY 0.435 1.870 13 {CNT2_e3_e3_e3_20__i5.ff_inst/CLK CNT2_e3_e3_e3_20__i6.ff_inst/CLK} CLOCK PIN 0.000 1.870 1 Uncertainty 0.000 1.870 Common Path Skew 0.000 1.870 Hold time 0.114 1.984 ---------------------------------------- -------------- ---------------- ----- --------------------- ------ Required Time -1.984 Arrival Time 2.594 ---------------------------------------- -------------- ---------------- ----- --------------------- ------ Path Slack (Passed) 0.610 ++++ Path 5 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Path Begin : CNT2_e3_e3_e3_20__i1.ff_inst/Q (SLICE) Path End : CNT2_e3_e3_e3_20__i1.ff_inst/DF (SLICE) Source Clock : CLK2 (R) Destination Clock: CLK2 (R) Logic Level : 2 Delay Ratio : 60.1% (route), 39.9% (logic) Clock Skew : 0.000 ns Hold Constraint : 0.000 ns Common Path Skew : 0.000 ns Path Slack : 0.610 ns (Passed) Source Clock Path { "path_begin": { "type":"port", "log_name":"Clk", "phy_name":"Clk" }, "path_end": { "type":"pin", "log_name":"CNT2_e3_e3_e3_20__i1.ff_inst/CLK", "phy_name":"SLICE_2/CLK" }, "path_sections":[ { "type":"net_delay", "net": { "log_name":"Clk", "phy_name":"Clk" }, "arrive":0.000, "delay":0.000 }, { "type":"site_delay", "pin0": { "log_name":"Clk_pad.bb_inst/B", "phy_name":"Clk_pad.bb_inst/IOPAD" }, "pin1": { "log_name":"Clk_pad.bb_inst/O", "phy_name":"Clk_pad.bb_inst/PADDI" }, "arrive":1.000, "delay":1.000 }, { "type":"net_delay", "net": { "log_name":"Clk_c", "phy_name":"Clk_c" }, "arrive":1.435, "delay":0.435 }, { "type":"site_delay", "pin0": { "log_name":"MyDCC/CLKI", "phy_name":"MyDCC/CLKI" }, "pin1": { "log_name":"MyDCC/CLKO", "phy_name":"MyDCC/CLKO" }, "arrive":1.435, "delay":0.000 }, { "type":"net_delay", "net": { "log_name":"clk2", "phy_name":"clk2" }, "arrive":1.870, "delay":0.435 }, { "type":"site_delay", "pin0": { "log_name":"", "phy_name":"" }, "pin1": { "log_name":"", "phy_name":"" }, "arrive":1.870, "delay":0.000 } ] } Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- -------------- ---------------- ----- --------------------- ------ Clk top CLOCK LATENCY 0.000 0.000 1 Clk NET DELAY 0.000 0.000 1 Clk_pad.bb_inst/B->Clk_pad.bb_inst/O SEIO33_CORE PADI_DEL 1.000 1.000 3 Clk_c NET DELAY 0.435 1.435 3 MyDCC/CLKI->MyDCC/CLKO DCC DCC_DEL 0.000 1.435 13 clk2 NET DELAY 0.435 1.870 13 {CNT2_e3_e3_e3_20__i1.ff_inst/CLK CNT2_e3_e3_e3_20__i2.ff_inst/CLK} CLOCK PIN 0.000 1.870 1 Data Path { "path_begin": { "type":"pin", "log_name":"CNT2_e3_e3_e3_20__i1.ff_inst/Q", "phy_name":"SLICE_2/Q0" }, "path_end": { "type":"pin", "log_name":"CNT2_e3_e3_e3_20__i1.ff_inst/DF", "phy_name":"SLICE_2/DI0" }, "path_sections":[ { "type":"site_delay", "pin0": { "log_name":"CNT2_e3_e3_e3_20__i1.ff_inst/CLK", "phy_name":"SLICE_2/CLK" }, "pin1": { "log_name":"CNT2_e3_e3_e3_20__i1.ff_inst/Q", "phy_name":"SLICE_2/Q0" }, "arrive":2.043, "delay":0.173 }, { "type":"net_delay", "net": { "log_name":"CNT2[1]", "phy_name":"CNT2[1]" }, "arrive":2.478, "delay":0.435 }, { "type":"site_delay", "pin0": { "log_name":"CNT2_e3_e3_e3_20_add_4_3/B0", "phy_name":"SLICE_2/B0" }, "pin1": { "log_name":"CNT2_e3_e3_e3_20_add_4_3/S0", "phy_name":"SLICE_2/F0" }, "arrive":2.594, "delay":0.116 }, { "type":"net_delay", "net": { "log_name":"CNT2_7__N_3[1]", "phy_name":"CNT2_7__N_3[1]" }, "arrive":2.594, "delay":0.000 }, { "type":"site_delay", "pin0": { "log_name":"", "phy_name":"" }, "pin1": { "log_name":"", "phy_name":"" }, "arrive":2.594, "delay":0.000 } ] } Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- -------------- ---------------- ----- --------------------- ------ CNT2_e3_e3_e3_20__i1.ff_inst/CLK->CNT2_e3_e3_e3_20__i1.ff_inst/Q SLICE REG_DEL 0.173 2.043 2 CNT2[1] NET DELAY 0.435 2.478 2 CNT2_e3_e3_e3_20_add_4_3/B0->CNT2_e3_e3_e3_20_add_4_3/S0 SLICE CTOF_DEL 0.116 2.594 1 CNT2_7__N_3[1] NET DELAY 0.000 2.594 1 CNT2_e3_e3_e3_20__i1.ff_inst/DF ENDPOINT 0.000 2.594 1 Destination Clock Path { "path_begin": { "type":"port", "log_name":"Clk", "phy_name":"Clk" }, "path_end": { "type":"pin", "log_name":"CNT2_e3_e3_e3_20__i1.ff_inst/CLK", "phy_name":"SLICE_2/CLK" }, "path_sections":[ { "type":"site_delay", "pin0": { "log_name":"", "phy_name":"" }, "pin1": { "log_name":"", "phy_name":"" }, "arrive":0.000, "delay":0.000 }, { "type":"net_delay", "net": { "log_name":"Clk", "phy_name":"Clk" }, "arrive":0.000, "delay":0.000 }, { "type":"site_delay", "pin0": { "log_name":"Clk_pad.bb_inst/B", "phy_name":"Clk_pad.bb_inst/IOPAD" }, "pin1": { "log_name":"Clk_pad.bb_inst/O", "phy_name":"Clk_pad.bb_inst/PADDI" }, "arrive":1.000, "delay":1.000 }, { "type":"net_delay", "net": { "log_name":"Clk_c", "phy_name":"Clk_c" }, "arrive":1.435, "delay":0.435 }, { "type":"site_delay", "pin0": { "log_name":"MyDCC/CLKI", "phy_name":"MyDCC/CLKI" }, "pin1": { "log_name":"MyDCC/CLKO", "phy_name":"MyDCC/CLKO" }, "arrive":1.435, "delay":0.000 }, { "type":"net_delay", "net": { "log_name":"clk2", "phy_name":"clk2" }, "arrive":1.870, "delay":0.435 }, { "type":"site_delay", "pin0": { "log_name":"", "phy_name":"" }, "pin1": { "log_name":"", "phy_name":"" }, "arrive":1.870, "delay":0.000 } ] } Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- -------------- ---------------- ----- --------------------- ------ CONSTRAINT 0.000 0.000 1 Clk top CLOCK LATENCY 0.000 0.000 1 Clk NET DELAY 0.000 0.000 1 Clk_pad.bb_inst/B->Clk_pad.bb_inst/O SEIO33_CORE PADI_DEL 1.000 1.000 3 Clk_c NET DELAY 0.435 1.435 3 MyDCC/CLKI->MyDCC/CLKO DCC DCC_DEL 0.000 1.435 13 clk2 NET DELAY 0.435 1.870 13 {CNT2_e3_e3_e3_20__i1.ff_inst/CLK CNT2_e3_e3_e3_20__i2.ff_inst/CLK} CLOCK PIN 0.000 1.870 1 Uncertainty 0.000 1.870 Common Path Skew 0.000 1.870 Hold time 0.114 1.984 ---------------------------------------- -------------- ---------------- ----- --------------------- ------ Required Time -1.984 Arrival Time 2.594 ---------------------------------------- -------------- ---------------- ----- --------------------- ------ Path Slack (Passed) 0.610 ++++ Path 6 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Path Begin : CNT2_e3_e3_e3_20__i3.ff_inst/Q (SLICE) Path End : CNT2_e3_e3_e3_20__i3.ff_inst/DF (SLICE) Source Clock : CLK2 (R) Destination Clock: CLK2 (R) Logic Level : 2 Delay Ratio : 60.1% (route), 39.9% (logic) Clock Skew : 0.000 ns Hold Constraint : 0.000 ns Common Path Skew : 0.000 ns Path Slack : 0.610 ns (Passed) Source Clock Path { "path_begin": { "type":"port", "log_name":"Clk", "phy_name":"Clk" }, "path_end": { "type":"pin", "log_name":"CNT2_e3_e3_e3_20__i3.ff_inst/CLK", "phy_name":"SLICE_0/CLK" }, "path_sections":[ { "type":"net_delay", "net": { "log_name":"Clk", "phy_name":"Clk" }, "arrive":0.000, "delay":0.000 }, { "type":"site_delay", "pin0": { "log_name":"Clk_pad.bb_inst/B", "phy_name":"Clk_pad.bb_inst/IOPAD" }, "pin1": { "log_name":"Clk_pad.bb_inst/O", "phy_name":"Clk_pad.bb_inst/PADDI" }, "arrive":1.000, "delay":1.000 }, { "type":"net_delay", "net": { "log_name":"Clk_c", "phy_name":"Clk_c" }, "arrive":1.435, "delay":0.435 }, { "type":"site_delay", "pin0": { "log_name":"MyDCC/CLKI", "phy_name":"MyDCC/CLKI" }, "pin1": { "log_name":"MyDCC/CLKO", "phy_name":"MyDCC/CLKO" }, "arrive":1.435, "delay":0.000 }, { "type":"net_delay", "net": { "log_name":"clk2", "phy_name":"clk2" }, "arrive":1.870, "delay":0.435 }, { "type":"site_delay", "pin0": { "log_name":"", "phy_name":"" }, "pin1": { "log_name":"", "phy_name":"" }, "arrive":1.870, "delay":0.000 } ] } Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- -------------- ---------------- ----- --------------------- ------ Clk top CLOCK LATENCY 0.000 0.000 1 Clk NET DELAY 0.000 0.000 1 Clk_pad.bb_inst/B->Clk_pad.bb_inst/O SEIO33_CORE PADI_DEL 1.000 1.000 3 Clk_c NET DELAY 0.435 1.435 3 MyDCC/CLKI->MyDCC/CLKO DCC DCC_DEL 0.000 1.435 13 clk2 NET DELAY 0.435 1.870 13 {CNT2_e3_e3_e3_20__i3.ff_inst/CLK CNT2_e3_e3_e3_20__i4.ff_inst/CLK} CLOCK PIN 0.000 1.870 1 Data Path { "path_begin": { "type":"pin", "log_name":"CNT2_e3_e3_e3_20__i3.ff_inst/Q", "phy_name":"SLICE_0/Q0" }, "path_end": { "type":"pin", "log_name":"CNT2_e3_e3_e3_20__i3.ff_inst/DF", "phy_name":"SLICE_0/DI0" }, "path_sections":[ { "type":"site_delay", "pin0": { "log_name":"CNT2_e3_e3_e3_20__i3.ff_inst/CLK", "phy_name":"SLICE_0/CLK" }, "pin1": { "log_name":"CNT2_e3_e3_e3_20__i3.ff_inst/Q", "phy_name":"SLICE_0/Q0" }, "arrive":2.043, "delay":0.173 }, { "type":"net_delay", "net": { "log_name":"CNT2[3]", "phy_name":"CNT2[3]" }, "arrive":2.478, "delay":0.435 }, { "type":"site_delay", "pin0": { "log_name":"CNT2_e3_e3_e3_20_add_4_5/B0", "phy_name":"SLICE_0/B0" }, "pin1": { "log_name":"CNT2_e3_e3_e3_20_add_4_5/S0", "phy_name":"SLICE_0/F0" }, "arrive":2.594, "delay":0.116 }, { "type":"net_delay", "net": { "log_name":"CNT2_7__N_3[3]", "phy_name":"CNT2_7__N_3[3]" }, "arrive":2.594, "delay":0.000 }, { "type":"site_delay", "pin0": { "log_name":"", "phy_name":"" }, "pin1": { "log_name":"", "phy_name":"" }, "arrive":2.594, "delay":0.000 } ] } Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- -------------- ---------------- ----- --------------------- ------ CNT2_e3_e3_e3_20__i3.ff_inst/CLK->CNT2_e3_e3_e3_20__i3.ff_inst/Q SLICE REG_DEL 0.173 2.043 2 CNT2[3] NET DELAY 0.435 2.478 2 CNT2_e3_e3_e3_20_add_4_5/B0->CNT2_e3_e3_e3_20_add_4_5/S0 SLICE CTOF_DEL 0.116 2.594 1 CNT2_7__N_3[3] NET DELAY 0.000 2.594 1 CNT2_e3_e3_e3_20__i3.ff_inst/DF ENDPOINT 0.000 2.594 1 Destination Clock Path { "path_begin": { "type":"port", "log_name":"Clk", "phy_name":"Clk" }, "path_end": { "type":"pin", "log_name":"CNT2_e3_e3_e3_20__i3.ff_inst/CLK", "phy_name":"SLICE_0/CLK" }, "path_sections":[ { "type":"site_delay", "pin0": { "log_name":"", "phy_name":"" }, "pin1": { "log_name":"", "phy_name":"" }, "arrive":0.000, "delay":0.000 }, { "type":"net_delay", "net": { "log_name":"Clk", "phy_name":"Clk" }, "arrive":0.000, "delay":0.000 }, { "type":"site_delay", "pin0": { "log_name":"Clk_pad.bb_inst/B", "phy_name":"Clk_pad.bb_inst/IOPAD" }, "pin1": { "log_name":"Clk_pad.bb_inst/O", "phy_name":"Clk_pad.bb_inst/PADDI" }, "arrive":1.000, "delay":1.000 }, { "type":"net_delay", "net": { "log_name":"Clk_c", "phy_name":"Clk_c" }, "arrive":1.435, "delay":0.435 }, { "type":"site_delay", "pin0": { "log_name":"MyDCC/CLKI", "phy_name":"MyDCC/CLKI" }, "pin1": { "log_name":"MyDCC/CLKO", "phy_name":"MyDCC/CLKO" }, "arrive":1.435, "delay":0.000 }, { "type":"net_delay", "net": { "log_name":"clk2", "phy_name":"clk2" }, "arrive":1.870, "delay":0.435 }, { "type":"site_delay", "pin0": { "log_name":"", "phy_name":"" }, "pin1": { "log_name":"", "phy_name":"" }, "arrive":1.870, "delay":0.000 } ] } Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- -------------- ---------------- ----- --------------------- ------ CONSTRAINT 0.000 0.000 1 Clk top CLOCK LATENCY 0.000 0.000 1 Clk NET DELAY 0.000 0.000 1 Clk_pad.bb_inst/B->Clk_pad.bb_inst/O SEIO33_CORE PADI_DEL 1.000 1.000 3 Clk_c NET DELAY 0.435 1.435 3 MyDCC/CLKI->MyDCC/CLKO DCC DCC_DEL 0.000 1.435 13 clk2 NET DELAY 0.435 1.870 13 {CNT2_e3_e3_e3_20__i3.ff_inst/CLK CNT2_e3_e3_e3_20__i4.ff_inst/CLK} CLOCK PIN 0.000 1.870 1 Uncertainty 0.000 1.870 Common Path Skew 0.000 1.870 Hold time 0.114 1.984 ---------------------------------------- -------------- ---------------- ----- --------------------- ------ Required Time -1.984 Arrival Time 2.594 ---------------------------------------- -------------- ---------------- ----- --------------------- ------ Path Slack (Passed) 0.610 ++++ Path 7 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Path Begin : CNT2_e3_e3_e3_20__i6.ff_inst/Q (SLICE) Path End : CNT2_e3_e3_e3_20__i6.ff_inst/DF (SLICE) Source Clock : CLK2 (R) Destination Clock: CLK2 (R) Logic Level : 2 Delay Ratio : 60.0% (route), 40.0% (logic) Clock Skew : 0.000 ns Hold Constraint : 0.000 ns Common Path Skew : 0.000 ns Path Slack : 0.611 ns (Passed) Source Clock Path { "path_begin": { "type":"port", "log_name":"Clk", "phy_name":"Clk" }, "path_end": { "type":"pin", "log_name":"CNT2_e3_e3_e3_20__i5.ff_inst/CLK", "phy_name":"SLICE_3/CLK" }, "path_sections":[ { "type":"net_delay", "net": { "log_name":"Clk", "phy_name":"Clk" }, "arrive":0.000, "delay":0.000 }, { "type":"site_delay", "pin0": { "log_name":"Clk_pad.bb_inst/B", "phy_name":"Clk_pad.bb_inst/IOPAD" }, "pin1": { "log_name":"Clk_pad.bb_inst/O", "phy_name":"Clk_pad.bb_inst/PADDI" }, "arrive":1.000, "delay":1.000 }, { "type":"net_delay", "net": { "log_name":"Clk_c", "phy_name":"Clk_c" }, "arrive":1.435, "delay":0.435 }, { "type":"site_delay", "pin0": { "log_name":"MyDCC/CLKI", "phy_name":"MyDCC/CLKI" }, "pin1": { "log_name":"MyDCC/CLKO", "phy_name":"MyDCC/CLKO" }, "arrive":1.435, "delay":0.000 }, { "type":"net_delay", "net": { "log_name":"clk2", "phy_name":"clk2" }, "arrive":1.870, "delay":0.435 }, { "type":"site_delay", "pin0": { "log_name":"", "phy_name":"" }, "pin1": { "log_name":"", "phy_name":"" }, "arrive":1.870, "delay":0.000 } ] } Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- -------------- ---------------- ----- --------------------- ------ Clk top CLOCK LATENCY 0.000 0.000 1 Clk NET DELAY 0.000 0.000 1 Clk_pad.bb_inst/B->Clk_pad.bb_inst/O SEIO33_CORE PADI_DEL 1.000 1.000 3 Clk_c NET DELAY 0.435 1.435 3 MyDCC/CLKI->MyDCC/CLKO DCC DCC_DEL 0.000 1.435 13 clk2 NET DELAY 0.435 1.870 13 {CNT2_e3_e3_e3_20__i5.ff_inst/CLK CNT2_e3_e3_e3_20__i6.ff_inst/CLK} CLOCK PIN 0.000 1.870 1 Data Path { "path_begin": { "type":"pin", "log_name":"CNT2_e3_e3_e3_20__i6.ff_inst/Q", "phy_name":"SLICE_3/Q1" }, "path_end": { "type":"pin", "log_name":"CNT2_e3_e3_e3_20__i6.ff_inst/DF", "phy_name":"SLICE_3/DI1" }, "path_sections":[ { "type":"site_delay", "pin0": { "log_name":"CNT2_e3_e3_e3_20__i6.ff_inst/CLK", "phy_name":"SLICE_3/CLK" }, "pin1": { "log_name":"CNT2_e3_e3_e3_20__i6.ff_inst/Q", "phy_name":"SLICE_3/Q1" }, "arrive":2.044, "delay":0.174 }, { "type":"net_delay", "net": { "log_name":"CNT2[6]", "phy_name":"CNT2[6]" }, "arrive":2.479, "delay":0.435 }, { "type":"site_delay", "pin0": { "log_name":"CNT2_e3_e3_e3_20_add_4_7/B1", "phy_name":"SLICE_3/B1" }, "pin1": { "log_name":"CNT2_e3_e3_e3_20_add_4_7/S1", "phy_name":"SLICE_3/F1" }, "arrive":2.595, "delay":0.116 }, { "type":"net_delay", "net": { "log_name":"CNT2_7__N_3[6]", "phy_name":"CNT2_7__N_3[6]" }, "arrive":2.595, "delay":0.000 }, { "type":"site_delay", "pin0": { "log_name":"", "phy_name":"" }, "pin1": { "log_name":"", "phy_name":"" }, "arrive":2.595, "delay":0.000 } ] } Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- -------------- ---------------- ----- --------------------- ------ CNT2_e3_e3_e3_20__i6.ff_inst/CLK->CNT2_e3_e3_e3_20__i6.ff_inst/Q SLICE REG_DEL 0.174 2.044 2 CNT2[6] NET DELAY 0.435 2.479 2 CNT2_e3_e3_e3_20_add_4_7/B1->CNT2_e3_e3_e3_20_add_4_7/S1 SLICE CTOF_DEL 0.116 2.595 1 CNT2_7__N_3[6] NET DELAY 0.000 2.595 1 CNT2_e3_e3_e3_20__i6.ff_inst/DF ENDPOINT 0.000 2.595 1 Destination Clock Path { "path_begin": { "type":"port", "log_name":"Clk", "phy_name":"Clk" }, "path_end": { "type":"pin", "log_name":"CNT2_e3_e3_e3_20__i5.ff_inst/CLK", "phy_name":"SLICE_3/CLK" }, "path_sections":[ { "type":"site_delay", "pin0": { "log_name":"", "phy_name":"" }, "pin1": { "log_name":"", "phy_name":"" }, "arrive":0.000, "delay":0.000 }, { "type":"net_delay", "net": { "log_name":"Clk", "phy_name":"Clk" }, "arrive":0.000, "delay":0.000 }, { "type":"site_delay", "pin0": { "log_name":"Clk_pad.bb_inst/B", "phy_name":"Clk_pad.bb_inst/IOPAD" }, "pin1": { "log_name":"Clk_pad.bb_inst/O", "phy_name":"Clk_pad.bb_inst/PADDI" }, "arrive":1.000, "delay":1.000 }, { "type":"net_delay", "net": { "log_name":"Clk_c", "phy_name":"Clk_c" }, "arrive":1.435, "delay":0.435 }, { "type":"site_delay", "pin0": { "log_name":"MyDCC/CLKI", "phy_name":"MyDCC/CLKI" }, "pin1": { "log_name":"MyDCC/CLKO", "phy_name":"MyDCC/CLKO" }, "arrive":1.435, "delay":0.000 }, { "type":"net_delay", "net": { "log_name":"clk2", "phy_name":"clk2" }, "arrive":1.870, "delay":0.435 }, { "type":"site_delay", "pin0": { "log_name":"", "phy_name":"" }, "pin1": { "log_name":"", "phy_name":"" }, "arrive":1.870, "delay":0.000 } ] } Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- -------------- ---------------- ----- --------------------- ------ CONSTRAINT 0.000 0.000 1 Clk top CLOCK LATENCY 0.000 0.000 1 Clk NET DELAY 0.000 0.000 1 Clk_pad.bb_inst/B->Clk_pad.bb_inst/O SEIO33_CORE PADI_DEL 1.000 1.000 3 Clk_c NET DELAY 0.435 1.435 3 MyDCC/CLKI->MyDCC/CLKO DCC DCC_DEL 0.000 1.435 13 clk2 NET DELAY 0.435 1.870 13 {CNT2_e3_e3_e3_20__i5.ff_inst/CLK CNT2_e3_e3_e3_20__i6.ff_inst/CLK} CLOCK PIN 0.000 1.870 1 Uncertainty 0.000 1.870 Common Path Skew 0.000 1.870 Hold time 0.114 1.984 ---------------------------------------- -------------- ---------------- ----- --------------------- ------ Required Time -1.984 Arrival Time 2.595 ---------------------------------------- -------------- ---------------- ----- --------------------- ------ Path Slack (Passed) 0.611 ++++ Path 8 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Path Begin : CNT2_e3_e3_e3_20__i2.ff_inst/Q (SLICE) Path End : CNT2_e3_e3_e3_20__i2.ff_inst/DF (SLICE) Source Clock : CLK2 (R) Destination Clock: CLK2 (R) Logic Level : 2 Delay Ratio : 60.0% (route), 40.0% (logic) Clock Skew : 0.000 ns Hold Constraint : 0.000 ns Common Path Skew : 0.000 ns Path Slack : 0.611 ns (Passed) Source Clock Path { "path_begin": { "type":"port", "log_name":"Clk", "phy_name":"Clk" }, "path_end": { "type":"pin", "log_name":"CNT2_e3_e3_e3_20__i1.ff_inst/CLK", "phy_name":"SLICE_2/CLK" }, "path_sections":[ { "type":"net_delay", "net": { "log_name":"Clk", "phy_name":"Clk" }, "arrive":0.000, "delay":0.000 }, { "type":"site_delay", "pin0": { "log_name":"Clk_pad.bb_inst/B", "phy_name":"Clk_pad.bb_inst/IOPAD" }, "pin1": { "log_name":"Clk_pad.bb_inst/O", "phy_name":"Clk_pad.bb_inst/PADDI" }, "arrive":1.000, "delay":1.000 }, { "type":"net_delay", "net": { "log_name":"Clk_c", "phy_name":"Clk_c" }, "arrive":1.435, "delay":0.435 }, { "type":"site_delay", "pin0": { "log_name":"MyDCC/CLKI", "phy_name":"MyDCC/CLKI" }, "pin1": { "log_name":"MyDCC/CLKO", "phy_name":"MyDCC/CLKO" }, "arrive":1.435, "delay":0.000 }, { "type":"net_delay", "net": { "log_name":"clk2", "phy_name":"clk2" }, "arrive":1.870, "delay":0.435 }, { "type":"site_delay", "pin0": { "log_name":"", "phy_name":"" }, "pin1": { "log_name":"", "phy_name":"" }, "arrive":1.870, "delay":0.000 } ] } Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- -------------- ---------------- ----- --------------------- ------ Clk top CLOCK LATENCY 0.000 0.000 1 Clk NET DELAY 0.000 0.000 1 Clk_pad.bb_inst/B->Clk_pad.bb_inst/O SEIO33_CORE PADI_DEL 1.000 1.000 3 Clk_c NET DELAY 0.435 1.435 3 MyDCC/CLKI->MyDCC/CLKO DCC DCC_DEL 0.000 1.435 13 clk2 NET DELAY 0.435 1.870 13 {CNT2_e3_e3_e3_20__i1.ff_inst/CLK CNT2_e3_e3_e3_20__i2.ff_inst/CLK} CLOCK PIN 0.000 1.870 1 Data Path { "path_begin": { "type":"pin", "log_name":"CNT2_e3_e3_e3_20__i2.ff_inst/Q", "phy_name":"SLICE_2/Q1" }, "path_end": { "type":"pin", "log_name":"CNT2_e3_e3_e3_20__i2.ff_inst/DF", "phy_name":"SLICE_2/DI1" }, "path_sections":[ { "type":"site_delay", "pin0": { "log_name":"CNT2_e3_e3_e3_20__i2.ff_inst/CLK", "phy_name":"SLICE_2/CLK" }, "pin1": { "log_name":"CNT2_e3_e3_e3_20__i2.ff_inst/Q", "phy_name":"SLICE_2/Q1" }, "arrive":2.044, "delay":0.174 }, { "type":"net_delay", "net": { "log_name":"CNT2[2]", "phy_name":"CNT2[2]" }, "arrive":2.479, "delay":0.435 }, { "type":"site_delay", "pin0": { "log_name":"CNT2_e3_e3_e3_20_add_4_3/B1", "phy_name":"SLICE_2/B1" }, "pin1": { "log_name":"CNT2_e3_e3_e3_20_add_4_3/S1", "phy_name":"SLICE_2/F1" }, "arrive":2.595, "delay":0.116 }, { "type":"net_delay", "net": { "log_name":"CNT2_7__N_3[2]", "phy_name":"CNT2_7__N_3[2]" }, "arrive":2.595, "delay":0.000 }, { "type":"site_delay", "pin0": { "log_name":"", "phy_name":"" }, "pin1": { "log_name":"", "phy_name":"" }, "arrive":2.595, "delay":0.000 } ] } Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- -------------- ---------------- ----- --------------------- ------ CNT2_e3_e3_e3_20__i2.ff_inst/CLK->CNT2_e3_e3_e3_20__i2.ff_inst/Q SLICE REG_DEL 0.174 2.044 2 CNT2[2] NET DELAY 0.435 2.479 2 CNT2_e3_e3_e3_20_add_4_3/B1->CNT2_e3_e3_e3_20_add_4_3/S1 SLICE CTOF_DEL 0.116 2.595 1 CNT2_7__N_3[2] NET DELAY 0.000 2.595 1 CNT2_e3_e3_e3_20__i2.ff_inst/DF ENDPOINT 0.000 2.595 1 Destination Clock Path { "path_begin": { "type":"port", "log_name":"Clk", "phy_name":"Clk" }, "path_end": { "type":"pin", "log_name":"CNT2_e3_e3_e3_20__i1.ff_inst/CLK", "phy_name":"SLICE_2/CLK" }, "path_sections":[ { "type":"site_delay", "pin0": { "log_name":"", "phy_name":"" }, "pin1": { "log_name":"", "phy_name":"" }, "arrive":0.000, "delay":0.000 }, { "type":"net_delay", "net": { "log_name":"Clk", "phy_name":"Clk" }, "arrive":0.000, "delay":0.000 }, { "type":"site_delay", "pin0": { "log_name":"Clk_pad.bb_inst/B", "phy_name":"Clk_pad.bb_inst/IOPAD" }, "pin1": { "log_name":"Clk_pad.bb_inst/O", "phy_name":"Clk_pad.bb_inst/PADDI" }, "arrive":1.000, "delay":1.000 }, { "type":"net_delay", "net": { "log_name":"Clk_c", "phy_name":"Clk_c" }, "arrive":1.435, "delay":0.435 }, { "type":"site_delay", "pin0": { "log_name":"MyDCC/CLKI", "phy_name":"MyDCC/CLKI" }, "pin1": { "log_name":"MyDCC/CLKO", "phy_name":"MyDCC/CLKO" }, "arrive":1.435, "delay":0.000 }, { "type":"net_delay", "net": { "log_name":"clk2", "phy_name":"clk2" }, "arrive":1.870, "delay":0.435 }, { "type":"site_delay", "pin0": { "log_name":"", "phy_name":"" }, "pin1": { "log_name":"", "phy_name":"" }, "arrive":1.870, "delay":0.000 } ] } Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- -------------- ---------------- ----- --------------------- ------ CONSTRAINT 0.000 0.000 1 Clk top CLOCK LATENCY 0.000 0.000 1 Clk NET DELAY 0.000 0.000 1 Clk_pad.bb_inst/B->Clk_pad.bb_inst/O SEIO33_CORE PADI_DEL 1.000 1.000 3 Clk_c NET DELAY 0.435 1.435 3 MyDCC/CLKI->MyDCC/CLKO DCC DCC_DEL 0.000 1.435 13 clk2 NET DELAY 0.435 1.870 13 {CNT2_e3_e3_e3_20__i1.ff_inst/CLK CNT2_e3_e3_e3_20__i2.ff_inst/CLK} CLOCK PIN 0.000 1.870 1 Uncertainty 0.000 1.870 Common Path Skew 0.000 1.870 Hold time 0.114 1.984 ---------------------------------------- -------------- ---------------- ----- --------------------- ------ Required Time -1.984 Arrival Time 2.595 ---------------------------------------- -------------- ---------------- ----- --------------------- ------ Path Slack (Passed) 0.611 ++++ Path 9 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Path Begin : CNT2_e3_e3_e3_20__i0.ff_inst/Q (SLICE) Path End : CNT2_e3_e3_e3_20__i0.ff_inst/DF (SLICE) Source Clock : CLK2 (R) Destination Clock: CLK2 (R) Logic Level : 2 Delay Ratio : 60.0% (route), 40.0% (logic) Clock Skew : 0.000 ns Hold Constraint : 0.000 ns Common Path Skew : 0.000 ns Path Slack : 0.611 ns (Passed) Source Clock Path { "path_begin": { "type":"port", "log_name":"Clk", "phy_name":"Clk" }, "path_end": { "type":"pin", "log_name":"CNT2_e3_e3_e3_20__i0.ff_inst/CLK", "phy_name":"SLICE_1/CLK" }, "path_sections":[ { "type":"net_delay", "net": { "log_name":"Clk", "phy_name":"Clk" }, "arrive":0.000, "delay":0.000 }, { "type":"site_delay", "pin0": { "log_name":"Clk_pad.bb_inst/B", "phy_name":"Clk_pad.bb_inst/IOPAD" }, "pin1": { "log_name":"Clk_pad.bb_inst/O", "phy_name":"Clk_pad.bb_inst/PADDI" }, "arrive":1.000, "delay":1.000 }, { "type":"net_delay", "net": { "log_name":"Clk_c", "phy_name":"Clk_c" }, "arrive":1.435, "delay":0.435 }, { "type":"site_delay", "pin0": { "log_name":"MyDCC/CLKI", "phy_name":"MyDCC/CLKI" }, "pin1": { "log_name":"MyDCC/CLKO", "phy_name":"MyDCC/CLKO" }, "arrive":1.435, "delay":0.000 }, { "type":"net_delay", "net": { "log_name":"clk2", "phy_name":"clk2" }, "arrive":1.870, "delay":0.435 }, { "type":"site_delay", "pin0": { "log_name":"", "phy_name":"" }, "pin1": { "log_name":"", "phy_name":"" }, "arrive":1.870, "delay":0.000 } ] } Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- -------------- ---------------- ----- --------------------- ------ Clk top CLOCK LATENCY 0.000 0.000 1 Clk NET DELAY 0.000 0.000 1 Clk_pad.bb_inst/B->Clk_pad.bb_inst/O SEIO33_CORE PADI_DEL 1.000 1.000 3 Clk_c NET DELAY 0.435 1.435 3 MyDCC/CLKI->MyDCC/CLKO DCC DCC_DEL 0.000 1.435 13 clk2 NET DELAY 0.435 1.870 13 CNT2_e3_e3_e3_20__i0.ff_inst/CLK CLOCK PIN 0.000 1.870 1 Data Path { "path_begin": { "type":"pin", "log_name":"CNT2_e3_e3_e3_20__i0.ff_inst/Q", "phy_name":"SLICE_1/Q1" }, "path_end": { "type":"pin", "log_name":"CNT2_e3_e3_e3_20__i0.ff_inst/DF", "phy_name":"SLICE_1/DI1" }, "path_sections":[ { "type":"site_delay", "pin0": { "log_name":"CNT2_e3_e3_e3_20__i0.ff_inst/CLK", "phy_name":"SLICE_1/CLK" }, "pin1": { "log_name":"CNT2_e3_e3_e3_20__i0.ff_inst/Q", "phy_name":"SLICE_1/Q1" }, "arrive":2.044, "delay":0.174 }, { "type":"net_delay", "net": { "log_name":"CNT2[0]", "phy_name":"CNT2[0]" }, "arrive":2.479, "delay":0.435 }, { "type":"site_delay", "pin0": { "log_name":"CNT2_e3_e3_e3_20_add_4_cin/B1", "phy_name":"SLICE_1/B1" }, "pin1": { "log_name":"CNT2_e3_e3_e3_20_add_4_cin/S1", "phy_name":"SLICE_1/F1" }, "arrive":2.595, "delay":0.116 }, { "type":"net_delay", "net": { "log_name":"CNT2_7__N_3[0]", "phy_name":"CNT2_7__N_3[0]" }, "arrive":2.595, "delay":0.000 }, { "type":"site_delay", "pin0": { "log_name":"", "phy_name":"" }, "pin1": { "log_name":"", "phy_name":"" }, "arrive":2.595, "delay":0.000 } ] } Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- -------------- ---------------- ----- --------------------- ------ CNT2_e3_e3_e3_20__i0.ff_inst/CLK->CNT2_e3_e3_e3_20__i0.ff_inst/Q SLICE REG_DEL 0.174 2.044 2 CNT2[0] NET DELAY 0.435 2.479 2 CNT2_e3_e3_e3_20_add_4_cin/B1->CNT2_e3_e3_e3_20_add_4_cin/S1 SLICE CTOF_DEL 0.116 2.595 1 CNT2_7__N_3[0] NET DELAY 0.000 2.595 1 CNT2_e3_e3_e3_20__i0.ff_inst/DF ENDPOINT 0.000 2.595 1 Destination Clock Path { "path_begin": { "type":"port", "log_name":"Clk", "phy_name":"Clk" }, "path_end": { "type":"pin", "log_name":"CNT2_e3_e3_e3_20__i0.ff_inst/CLK", "phy_name":"SLICE_1/CLK" }, "path_sections":[ { "type":"site_delay", "pin0": { "log_name":"", "phy_name":"" }, "pin1": { "log_name":"", "phy_name":"" }, "arrive":0.000, "delay":0.000 }, { "type":"net_delay", "net": { "log_name":"Clk", "phy_name":"Clk" }, "arrive":0.000, "delay":0.000 }, { "type":"site_delay", "pin0": { "log_name":"Clk_pad.bb_inst/B", "phy_name":"Clk_pad.bb_inst/IOPAD" }, "pin1": { "log_name":"Clk_pad.bb_inst/O", "phy_name":"Clk_pad.bb_inst/PADDI" }, "arrive":1.000, "delay":1.000 }, { "type":"net_delay", "net": { "log_name":"Clk_c", "phy_name":"Clk_c" }, "arrive":1.435, "delay":0.435 }, { "type":"site_delay", "pin0": { "log_name":"MyDCC/CLKI", "phy_name":"MyDCC/CLKI" }, "pin1": { "log_name":"MyDCC/CLKO", "phy_name":"MyDCC/CLKO" }, "arrive":1.435, "delay":0.000 }, { "type":"net_delay", "net": { "log_name":"clk2", "phy_name":"clk2" }, "arrive":1.870, "delay":0.435 }, { "type":"site_delay", "pin0": { "log_name":"", "phy_name":"" }, "pin1": { "log_name":"", "phy_name":"" }, "arrive":1.870, "delay":0.000 } ] } Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- -------------- ---------------- ----- --------------------- ------ CONSTRAINT 0.000 0.000 1 Clk top CLOCK LATENCY 0.000 0.000 1 Clk NET DELAY 0.000 0.000 1 Clk_pad.bb_inst/B->Clk_pad.bb_inst/O SEIO33_CORE PADI_DEL 1.000 1.000 3 Clk_c NET DELAY 0.435 1.435 3 MyDCC/CLKI->MyDCC/CLKO DCC DCC_DEL 0.000 1.435 13 clk2 NET DELAY 0.435 1.870 13 CNT2_e3_e3_e3_20__i0.ff_inst/CLK CLOCK PIN 0.000 1.870 1 Uncertainty 0.000 1.870 Common Path Skew 0.000 1.870 Hold time 0.114 1.984 ---------------------------------------- -------------- ---------------- ----- --------------------- ------ Required Time -1.984 Arrival Time 2.595 ---------------------------------------- -------------- ---------------- ----- --------------------- ------ Path Slack (Passed) 0.611 ++++ Path 10 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Path Begin : CNT2_e3_e3_e3_20__i4.ff_inst/Q (SLICE) Path End : CNT2_e3_e3_e3_20__i4.ff_inst/DF (SLICE) Source Clock : CLK2 (R) Destination Clock: CLK2 (R) Logic Level : 2 Delay Ratio : 60.0% (route), 40.0% (logic) Clock Skew : 0.000 ns Hold Constraint : 0.000 ns Common Path Skew : 0.000 ns Path Slack : 0.611 ns (Passed) Source Clock Path { "path_begin": { "type":"port", "log_name":"Clk", "phy_name":"Clk" }, "path_end": { "type":"pin", "log_name":"CNT2_e3_e3_e3_20__i3.ff_inst/CLK", "phy_name":"SLICE_0/CLK" }, "path_sections":[ { "type":"net_delay", "net": { "log_name":"Clk", "phy_name":"Clk" }, "arrive":0.000, "delay":0.000 }, { "type":"site_delay", "pin0": { "log_name":"Clk_pad.bb_inst/B", "phy_name":"Clk_pad.bb_inst/IOPAD" }, "pin1": { "log_name":"Clk_pad.bb_inst/O", "phy_name":"Clk_pad.bb_inst/PADDI" }, "arrive":1.000, "delay":1.000 }, { "type":"net_delay", "net": { "log_name":"Clk_c", "phy_name":"Clk_c" }, "arrive":1.435, "delay":0.435 }, { "type":"site_delay", "pin0": { "log_name":"MyDCC/CLKI", "phy_name":"MyDCC/CLKI" }, "pin1": { "log_name":"MyDCC/CLKO", "phy_name":"MyDCC/CLKO" }, "arrive":1.435, "delay":0.000 }, { "type":"net_delay", "net": { "log_name":"clk2", "phy_name":"clk2" }, "arrive":1.870, "delay":0.435 }, { "type":"site_delay", "pin0": { "log_name":"", "phy_name":"" }, "pin1": { "log_name":"", "phy_name":"" }, "arrive":1.870, "delay":0.000 } ] } Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- -------------- ---------------- ----- --------------------- ------ Clk top CLOCK LATENCY 0.000 0.000 1 Clk NET DELAY 0.000 0.000 1 Clk_pad.bb_inst/B->Clk_pad.bb_inst/O SEIO33_CORE PADI_DEL 1.000 1.000 3 Clk_c NET DELAY 0.435 1.435 3 MyDCC/CLKI->MyDCC/CLKO DCC DCC_DEL 0.000 1.435 13 clk2 NET DELAY 0.435 1.870 13 {CNT2_e3_e3_e3_20__i3.ff_inst/CLK CNT2_e3_e3_e3_20__i4.ff_inst/CLK} CLOCK PIN 0.000 1.870 1 Data Path { "path_begin": { "type":"pin", "log_name":"CNT2_e3_e3_e3_20__i4.ff_inst/Q", "phy_name":"SLICE_0/Q1" }, "path_end": { "type":"pin", "log_name":"CNT2_e3_e3_e3_20__i4.ff_inst/DF", "phy_name":"SLICE_0/DI1" }, "path_sections":[ { "type":"site_delay", "pin0": { "log_name":"CNT2_e3_e3_e3_20__i4.ff_inst/CLK", "phy_name":"SLICE_0/CLK" }, "pin1": { "log_name":"CNT2_e3_e3_e3_20__i4.ff_inst/Q", "phy_name":"SLICE_0/Q1" }, "arrive":2.044, "delay":0.174 }, { "type":"net_delay", "net": { "log_name":"CNT2[4]", "phy_name":"CNT2[4]" }, "arrive":2.479, "delay":0.435 }, { "type":"site_delay", "pin0": { "log_name":"CNT2_e3_e3_e3_20_add_4_5/B1", "phy_name":"SLICE_0/B1" }, "pin1": { "log_name":"CNT2_e3_e3_e3_20_add_4_5/S1", "phy_name":"SLICE_0/F1" }, "arrive":2.595, "delay":0.116 }, { "type":"net_delay", "net": { "log_name":"CNT2_7__N_3[4]", "phy_name":"CNT2_7__N_3[4]" }, "arrive":2.595, "delay":0.000 }, { "type":"site_delay", "pin0": { "log_name":"", "phy_name":"" }, "pin1": { "log_name":"", "phy_name":"" }, "arrive":2.595, "delay":0.000 } ] } Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- -------------- ---------------- ----- --------------------- ------ CNT2_e3_e3_e3_20__i4.ff_inst/CLK->CNT2_e3_e3_e3_20__i4.ff_inst/Q SLICE REG_DEL 0.174 2.044 2 CNT2[4] NET DELAY 0.435 2.479 2 CNT2_e3_e3_e3_20_add_4_5/B1->CNT2_e3_e3_e3_20_add_4_5/S1 SLICE CTOF_DEL 0.116 2.595 1 CNT2_7__N_3[4] NET DELAY 0.000 2.595 1 CNT2_e3_e3_e3_20__i4.ff_inst/DF ENDPOINT 0.000 2.595 1 Destination Clock Path { "path_begin": { "type":"port", "log_name":"Clk", "phy_name":"Clk" }, "path_end": { "type":"pin", "log_name":"CNT2_e3_e3_e3_20__i3.ff_inst/CLK", "phy_name":"SLICE_0/CLK" }, "path_sections":[ { "type":"site_delay", "pin0": { "log_name":"", "phy_name":"" }, "pin1": { "log_name":"", "phy_name":"" }, "arrive":0.000, "delay":0.000 }, { "type":"net_delay", "net": { "log_name":"Clk", "phy_name":"Clk" }, "arrive":0.000, "delay":0.000 }, { "type":"site_delay", "pin0": { "log_name":"Clk_pad.bb_inst/B", "phy_name":"Clk_pad.bb_inst/IOPAD" }, "pin1": { "log_name":"Clk_pad.bb_inst/O", "phy_name":"Clk_pad.bb_inst/PADDI" }, "arrive":1.000, "delay":1.000 }, { "type":"net_delay", "net": { "log_name":"Clk_c", "phy_name":"Clk_c" }, "arrive":1.435, "delay":0.435 }, { "type":"site_delay", "pin0": { "log_name":"MyDCC/CLKI", "phy_name":"MyDCC/CLKI" }, "pin1": { "log_name":"MyDCC/CLKO", "phy_name":"MyDCC/CLKO" }, "arrive":1.435, "delay":0.000 }, { "type":"net_delay", "net": { "log_name":"clk2", "phy_name":"clk2" }, "arrive":1.870, "delay":0.435 }, { "type":"site_delay", "pin0": { "log_name":"", "phy_name":"" }, "pin1": { "log_name":"", "phy_name":"" }, "arrive":1.870, "delay":0.000 } ] } Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- -------------- ---------------- ----- --------------------- ------ CONSTRAINT 0.000 0.000 1 Clk top CLOCK LATENCY 0.000 0.000 1 Clk NET DELAY 0.000 0.000 1 Clk_pad.bb_inst/B->Clk_pad.bb_inst/O SEIO33_CORE PADI_DEL 1.000 1.000 3 Clk_c NET DELAY 0.435 1.435 3 MyDCC/CLKI->MyDCC/CLKO DCC DCC_DEL 0.000 1.435 13 clk2 NET DELAY 0.435 1.870 13 {CNT2_e3_e3_e3_20__i3.ff_inst/CLK CNT2_e3_e3_e3_20__i4.ff_inst/CLK} CLOCK PIN 0.000 1.870 1 Uncertainty 0.000 1.870 Common Path Skew 0.000 1.870 Hold time 0.114 1.984 ---------------------------------------- -------------- ---------------- ----- --------------------- ------ Required Time -1.984 Arrival Time 2.595 ---------------------------------------- -------------- ---------------- ----- --------------------- ------ Path Slack (Passed) 0.611 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ End of Detailed Report for timing paths +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 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    Contents