POSTSYN: Post Synthesis Process Radiant Software (64-bit) 2023.2.1.288.0
Command Line: postsyn -a LFCPNX -p LFCPNX-50 -t CBG256 -sp 9_High-Performance_1.0V -oc Commercial -top -w -o LAB01_impl_1_syn.udb -ldc C:/Users/ssyahril/OneDrive - Lattice Semiconductor Corp/Documents/Insights/Constraint Deep Dive/Radiant Lab/LAB_01/impl_1/LAB01_impl_1.ldc -gui -msgset C:/Users/ssyahril/OneDrive - Lattice Semiconductor Corp/Documents/Insights/Constraint Deep Dive/Radiant Lab/LAB_01/promote.xml LAB01_impl_1.vm 
   Architecture:     LFCPNX
   Device:           LFCPNX-50
   Package:          CBG256
   Performance:      9_High-Performance_1.0V
Reading input file 'LAB01_impl_1.vm' ...
Reading constraint file 'C:/Users/ssyahril/OneDrive - Lattice Semiconductor Corp/Documents/Insights/Constraint Deep Dive/Radiant Lab/LAB_01/impl_1/LAB01_impl_1.ldc' ...
Merging PCS ...
Removing unused logic ...
INFO <35811146> - Signal GSR_INST.GSROUT undriven or does not drive anything - clipped
Starting design annotation....
WARNING <70009502> - The preferred point for defining clocks is top level ports and driver pins. Pad delays will not be taken into consideration if clocks are defined on nets.
 
Constraint Summary:
   Total number of constraints: 3
   Total number of constraints dropped: 0
 
Writing output file 'LAB01_impl_1_syn.udb'.
POSTSYN finished successfully.
Total CPU Time: 1 secs 
Total REAL Time: 2 secs 
Peak Memory Usage: 229 MB
Checksum -- postsyn: a42acab272353f18c7d90650da46c887b3dc0971