Copyright (c) 2002-2022 Lattice Semiconductor Corporation,  All rights reserved.

Wed Jun  5 12:16:51 2024

Command Line: par -w -n 1 -t 1 -s 1 -cores 1 -hsp m -exp parPathBased=OFF \
	lab03_impl_1_map.udb lab03_impl_1.udb 


Cost Table Summary
Level/       Number       Estimated       Timing       Estimated Worst    Timing          Run      Run
Cost [udb]   Unrouted     Worst Slack     Score        Slack(hold)        Score(hold)     Time     Status
----------   --------     -----------     ------       ---------------    -----------     ----     ------
5_1   *      0            4.282           0            0.240              0               09       Completed
* : Design saved.

Total (real) run time for 1-seed: 9 secs 

par done!

Lattice Place and Route Report for Design "lab03_impl_1_map.udb"
Wed Jun  5 12:16:51 2024


Best Par Run
PAR: Place And Route Radiant Software (64-bit) 2023.2.1.288.0.
Command Line: par -w -t 1 -cores 1 -hsp m -exp parPathBased=OFF \
	lab03_impl_1_map.udb lab03_impl_1_par.dir/5_1.udb 

Loading lab03_impl_1_map.udb ...
Loading device for application GENERIC from file 'je5d15.nph' in environment: C:/lscc/radiant/2023.2/ispfpga.
Package Status:                     Final          Version 23.
Performance Hardware Data Status:   Final          Version 118.1.



Design:  top
Family:  LIFCL
Device:  LIFCL-17
Package: QFN72
Performance Grade:   9_High-Performance_1.0V

Device SLICE utilization summary after final SLICE packing:
   SLICE             16/6912         <1% used

Number of Signals: 36
Number of Connections: 62

Device utilization summary:

   DCC                   1/62            2% used
   SEIO33               10/39           26% used
                        10/17           59% bonded
   SLICE                16/6912         <1% used
     LUT                13/13824        <1% used
     REG                18/13824        <1% used


Pin Constraint Summary:
   0 out of 10 pins locked (0% locked).
INFO: signal 'Clk_c' driving mixed DCC load types requires multi-feedlines.
INFO: signal 'Clk_c' driving mixed DCC load types requires multi-feedlines.
.
Starting Placer Phase 0 (HIER). CPU time: 1 secs , REAL time: 0 secs 
..........
Finished Placer Phase 0 (HIER). CPU time: 1 secs , REAL time: 0 secs 

Starting Placer Phase 1. CPU time: 1 secs , REAL time: 0 secs 
..  ..
....................

Placer score = 6696.
Finished Placer Phase 1. CPU time: 8 secs , REAL time: 8 secs 

Starting Placer Phase 2.
.

Placer score =  6630
Finished Placer Phase 2.  CPU time: 8 secs , REAL time: 8 secs 



Clock Report

Global Clock Resources:
  CLK_PIN    : 1 out of 13 (7%)
  PLL        : 0 out of 2 (0%)
  DCS        : 0 out of 1 (0%)
  DCC        : 1 out of 62 (1%)
  ECLKDIV    : 0 out of 12 (0%)
  PCLKDIV    : 0 out of 1 (0%)
  OSC        : 0 out of 1 (0%)
  DPHY       : 0 out of 2 (0%)

Global Clocks:
  PRIMARY "Clk_c" from comp "Clk" on CLK_PIN site "59 (PT59A)", clk load = 2, ce load = 0, sr load = 0
  PRIMARY DCC "clk2" from comp "MyDCC" on DCC site "DCC_T6", total # of clk loads = 13
     - DCC input "Clk_c" from comp "Clk" on CLK_PIN site "59 (PT59A)"

  PRIMARY  : 2 out of 16 (12%)

Edge Clocks:

  No edge clock selected.





I/O Usage Summary (final):
   10 out of 39 (25.6%) SEIO33 sites used.
   10 out of 17 (58.8%) bonded SEIO33 sites used.
   Number of SEIO33 components: 10; differential: 0
   Number of Vref pins used: 0
   0 out of 48 (0.0%) SEIO18 sites used.
   0 out of 22 (0.0%) bonded SEIO18 sites used.
   Number of SEIO18 components: 0; differential: 0
   0 out of 24 (0.0%) DIFFIO18 sites used.
   0 out of 11 (0.0%) bonded DIFFIO18 sites used.
   Number of DIFFIO18 components: 0; differential: 0

I/O Bank Usage Summary:
+----------+---------------+------------+------------+------------+
| I/O Bank | Usage         | Bank Vccio | Bank Vref1 | Bank Vref2 |
+----------+---------------+------------+------------+------------+
| 0        | 7 / 10 ( 70%) | 3.3V       | -          | -          |
| 1        | 3 / 7 ( 42%)  | 3.3V       | -          | -          |
| 3        | 0 / 12 (  0%) | -          | -          | -          |
| 5        | 0 / 10 (  0%) | -          | -          | -          |
+----------+---------------+------------+------------+------------+

Total Placer CPU time: 8 secs , REAL time: 8 secs 


Checksum -- place: 523003fd60d0788952e2d66a41de78133467722
Writing design to file lab03_impl_1_par.dir/5_1.udb ...


Start NBR router at 12:16:59 06/05/24

*****************************************************************
Info: NBR allows conflicts(one node used by more than one signal)
      in the earlier iterations. In each iteration, it tries to  
      solve the conflicts while keeping the critical connections 
      routed as short as possible. The routing process is said to
      be completed when no conflicts exist and all connections   
      are routed.                                                
Note: NBR uses a different method to calculate timing slacks. The
      worst slack and total negative slack may not be the same as
      that in timing report. You should always run the timing    
      tool to verify your design.                                
*****************************************************************

Starting routing resource preassignment
Preassignment Summary:
--------------------------------------------------------------------------------
15 connections routed with dedicated routing resources
2 global clock signals routed
30 connections routed (of 62 total) (48.39%)
---------------------------------------------------------
Clock routing summary:
Primary clocks (4 used out of 32 available):
    Signal "Clk_c" (4, 20)
       Clock   loads: 2     out of     2 routed (100.00%)
       Data    loads: 1     out of     1 routed (100.00%)
    Signal "clk2" (0, 16)
       Clock   loads: 13    out of    13 routed (100.00%)
---------------------------------------------------------
--------------------------------------------------------------------------------
Completed routing resource preassignment

Start NBR section for initial routing at 12:16:59 06/05/24
Level 4, iteration 1
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Routing in Serial Mode ......
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; 
Estimated worst slack/total negative slack<setup>: 4.282ns/0.000ns; real time: 0 secs 

Info: Initial congestion level at 75.00% usage is 0
Info: Initial congestion area  at 75.00% usage is 0 (0.00%)

Start NBR section for normal routing at 12:16:59 06/05/24
Level 4, iteration 1
0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; 
Estimated worst slack/total negative slack<setup>: 4.282ns/0.000ns; real time: 0 secs 

Start NBR section for setup/hold timing optimization with effort level 3 at 12:16:59 06/05/24

Start NBR section for post-routing at 12:17:00 06/05/24

End NBR router with 0 unrouted connection

Checksum -- route: 53fa837d4b9cab4bf4fc93ffc65c36f3d7cd796b

Total CPU time 1 secs 
Total REAL time: 0 secs 
Completely routed.
End of route.  62 routed (100.00%); 0 unrouted.

Writing design to file lab03_impl_1_par.dir/5_1.udb ...


All signals are completely routed.


PAR_SUMMARY::Run status = Completed
PAR_SUMMARY::Number of unrouted conns = 0
PAR_SUMMARY::Estimated worst slack<setup/<ns>> = 4.282
PAR_SUMMARY::Timing score<setup/<ns>> = 0.000
PAR_SUMMARY::Estimated worst slack<hold/<ns>> = 0.240
PAR_SUMMARY::Timing score<hold/<ns>> = 0.000
PAR_SUMMARY::Number of errors = 0

Note: user must run 'timing' for timing closure signoff.

Total CPU  Time: 9 secs 
Total REAL Time: 9 secs 
Peak Memory Usage: 459.03 MB


par done!

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Copyright (c) 2002-2023 Lattice Semiconductor Corporation,  All rights reserved.





















































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