Synthesis Report synthesis: version Radiant Software (64-bit) 2023.2.1.288.0 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2023 Lattice Semiconductor Corporation, All rights reserved. Wed Jun 5 12:16:22 2024 Command Line: C:\lscc\radiant\2023.2\ispfpga\bin\nt64\synthesis.exe -f lab03_impl_1_lattice.synproj -gui -msgset C:/Users/ssyahril/Downloads/FAE_F2F_Training_Labs_V2/FAE_F2F_Training_Labs_V2/LAB_03/promote.xml Synthesis options: The -a option is LIFCL. The -t option is QFN72. The -sp option is 9_High-Performance_1.0V. The -p option is LIFCL-17. ########################################################## ### Lattice Family : LIFCL ### Device : LIFCL-17 ### Package : QFN72 ### Performance Grade : 9_High-Performance_1.0V INFO <35001786> - synthesis: User-Selected Strategy Settings Optimization goal = Timing Top-level module name = top. Target frequency = 200.000000 MHz. Maximum fanout = 1000. Timing path count = 3 (default) BRAM utilization = 100.000000 % DSP usage = true DSP utilization = 100.000000 % fsm_encoding_style = auto resolve_mixed_drivers = 0 fix_gated_clocks = 1 Mux style = auto (Default) Use Carry Chain = true carry_chain_length = 0 Loop Limit = 1950. Use IO Insertion = TRUE Use IO Reg = AUTO Resource Sharing = TRUE Propagate Constants = TRUE Remove Duplicate Registers = TRUE force_gsr = yes Output HDL file name = lab03_impl_1.vm. ROM style = auto RAM style = auto The -comp option is FALSE. The -syn option is FALSE. -sdc option: SDC file input is C:/Users/ssyahril/Downloads/FAE_F2F_Training_Labs_V2/FAE_F2F_Training_Labs_V2/LAB_03/my_timing.sdc. Hardtimer checking is enabled (default). The -dt option is not used. -path C:/Users/ssyahril/Downloads/FAE_F2F_Training_Labs_V2/FAE_F2F_Training_Labs_V2/LAB_03 (searchpath added) -path C:/Users/ssyahril/Downloads/FAE_F2F_Training_Labs_V2/FAE_F2F_Training_Labs_V2/LAB_03/impl_1 (searchpath added) -path C:/lscc/radiant/2023.2/ispfpga/je5d00/data (searchpath added) Mixed language design Verilog design file = C:/lscc/radiant/2023.2/ip/pmi/pmi_lifcl.v VHDL library = pmi VHDL design file = C:/lscc/radiant/2023.2/ip/pmi/pmi_lifcl.vhd VHDL library = work VHDL design file = C:/Users/ssyahril/Downloads/FAE_F2F_Training_Labs_V2/FAE_F2F_Training_Labs_V2/LAB_03/source/impl_1/Top.vhd The -r option is OFF. [ Remove LOC Properties is OFF. ] WARNING <35935050> - synthesis: input port MBISTCLK is not connected on this instance. VDB-5050 Compile design. Compile Design Begin Analyzing Verilog file c:/lscc/radiant/2023.2/ip/pmi/pmi_lifcl.v. VERI-1482 INFO <35901328> - synthesis: c:/lscc/radiant/2023.2/ip/pmi/pmi_lifcl.v(1): analyzing included file c:/lscc/radiant/2023.2/ip/pmi/pmi_addsub.v. VERI-1328 INFO <35901328> - synthesis: c:/lscc/radiant/2023.2/ip/pmi/pmi_addsub.v(40): analyzing included file c:/lscc/radiant/2023.2/ip/pmi/../common/adder_subtractor/rtl/lscc_add_sub.v. VERI-1328 INFO <35901328> - synthesis: c:/lscc/radiant/2023.2/ip/pmi/pmi_lifcl.v(2): analyzing included file c:/lscc/radiant/2023.2/ip/pmi/pmi_add.v. VERI-1328 INFO <35901328> - synthesis: c:/lscc/radiant/2023.2/ip/pmi/pmi_add.v(50): analyzing included file c:/lscc/radiant/2023.2/ip/pmi/../common/adder/rtl/lscc_adder.v. VERI-1328 INFO <35901328> - synthesis: c:/lscc/radiant/2023.2/ip/pmi/pmi_lifcl.v(3): analyzing included file c:/lscc/radiant/2023.2/ip/pmi/pmi_complex_mult.v. VERI-1328 INFO <35901328> - synthesis: c:/lscc/radiant/2023.2/ip/pmi/pmi_complex_mult.v(52): analyzing included file c:/lscc/radiant/2023.2/ip/pmi/../common/complex_mult/rtl/lscc_complex_mult.v. VERI-1328 INFO <35901328> - synthesis: c:/lscc/radiant/2023.2/ip/pmi/pmi_lifcl.v(4): analyzing included file c:/lscc/radiant/2023.2/ip/pmi/pmi_counter.v. VERI-1328 INFO <35901328> - synthesis: c:/lscc/radiant/2023.2/ip/pmi/pmi_counter.v(39): analyzing included file c:/lscc/radiant/2023.2/ip/pmi/../common/counter/rtl/lscc_cntr.v. VERI-1328 INFO <35901328> - synthesis: c:/lscc/radiant/2023.2/ip/pmi/pmi_lifcl.v(5): analyzing included file c:/lscc/radiant/2023.2/ip/pmi/pmi_distributed_dpram.v. VERI-1328 INFO <35901328> - synthesis: c:/lscc/radiant/2023.2/ip/pmi/pmi_distributed_dpram.v(43): analyzing included file c:/lscc/radiant/2023.2/ip/pmi/../common/distributed_dpram/rtl/lscc_distributed_dpram.v. VERI-1328 INFO <35901328> - synthesis: c:/lscc/radiant/2023.2/ip/pmi/pmi_lifcl.v(6): analyzing included file c:/lscc/radiant/2023.2/ip/pmi/pmi_distributed_spram.v. VERI-1328 INFO <35901328> - synthesis: c:/lscc/radiant/2023.2/ip/pmi/pmi_distributed_spram.v(42): analyzing included file c:/lscc/radiant/2023.2/ip/pmi/../common/distributed_spram/rtl/lscc_distributed_spram.v. VERI-1328 INFO <35901328> - synthesis: c:/lscc/radiant/2023.2/ip/pmi/pmi_lifcl.v(7): analyzing included file c:/lscc/radiant/2023.2/ip/pmi/pmi_distributed_rom.v. VERI-1328 INFO <35901328> - synthesis: c:/lscc/radiant/2023.2/ip/pmi/pmi_distributed_rom.v(42): analyzing included file c:/lscc/radiant/2023.2/ip/pmi/../common/distributed_rom/rtl/lscc_distributed_rom.v. VERI-1328 INFO <35901328> - synthesis: c:/lscc/radiant/2023.2/ip/pmi/pmi_lifcl.v(8): analyzing included file c:/lscc/radiant/2023.2/ip/pmi/pmi_distributed_shift_reg.v. VERI-1328 INFO <35901328> - synthesis: c:/lscc/radiant/2023.2/ip/pmi/pmi_distributed_shift_reg.v(41): analyzing included file c:/lscc/radiant/2023.2/ip/pmi/../common/ram_shift_reg/rtl/lscc_shift_register.v. VERI-1328 INFO <35901328> - synthesis: c:/lscc/radiant/2023.2/ip/pmi/pmi_lifcl.v(9): analyzing included file c:/lscc/radiant/2023.2/ip/pmi/pmi_fifo.v. VERI-1328 INFO <35901328> - synthesis: c:/lscc/radiant/2023.2/ip/pmi/pmi_fifo.v(44): analyzing included file c:/lscc/radiant/2023.2/ip/pmi/../avant/fifo/rtl/lscc_fifo.v. VERI-1328 INFO <35901328> - synthesis: c:/lscc/radiant/2023.2/ip/pmi/pmi_lifcl.v(10): analyzing included file c:/lscc/radiant/2023.2/ip/pmi/pmi_fifo_dc.v. VERI-1328 INFO <35901328> - synthesis: c:/lscc/radiant/2023.2/ip/pmi/pmi_fifo_dc.v(47): analyzing included file c:/lscc/radiant/2023.2/ip/pmi/../avant/fifo_dc/rtl/lscc_fifo_dc.v. VERI-1328 INFO <35901328> - synthesis: c:/lscc/radiant/2023.2/ip/pmi/pmi_lifcl.v(11): analyzing included file c:/lscc/radiant/2023.2/ip/pmi/pmi_mac.v. VERI-1328 INFO <35901328> - synthesis: c:/lscc/radiant/2023.2/ip/pmi/pmi_mac.v(52): analyzing included file c:/lscc/radiant/2023.2/ip/pmi/../common/mult_accumulate/rtl/lscc_mult_accumulate.v. VERI-1328 INFO <35901328> - synthesis: c:/lscc/radiant/2023.2/ip/pmi/pmi_lifcl.v(12): analyzing included file c:/lscc/radiant/2023.2/ip/pmi/pmi_multaddsubsum.v. VERI-1328 INFO <35901328> - synthesis: c:/lscc/radiant/2023.2/ip/pmi/pmi_multaddsubsum.v(53): analyzing included file c:/lscc/radiant/2023.2/ip/pmi/../common/mult_add_sub_sum/rtl/lscc_mult_add_sub_sum.v. VERI-1328 INFO <35901328> - synthesis: c:/lscc/radiant/2023.2/ip/pmi/pmi_lifcl.v(13): analyzing included file c:/lscc/radiant/2023.2/ip/pmi/pmi_multaddsub.v. VERI-1328 INFO <35901328> - synthesis: c:/lscc/radiant/2023.2/ip/pmi/pmi_multaddsub.v(52): analyzing included file c:/lscc/radiant/2023.2/ip/pmi/../common/mult_add_sub/rtl/lscc_mult_add_sub.v. VERI-1328 INFO <35901328> - synthesis: c:/lscc/radiant/2023.2/ip/pmi/pmi_lifcl.v(14): analyzing included file c:/lscc/radiant/2023.2/ip/pmi/pmi_mult.v. VERI-1328 INFO <35901328> - synthesis: c:/lscc/radiant/2023.2/ip/pmi/pmi_mult.v(51): analyzing included file c:/lscc/radiant/2023.2/ip/pmi/../common/multiplier/rtl/lscc_multiplier.v. VERI-1328 INFO <35901328> - synthesis: c:/lscc/radiant/2023.2/ip/pmi/pmi_lifcl.v(15): analyzing included file c:/lscc/radiant/2023.2/ip/pmi/pmi_ram_dp.v. VERI-1328 INFO <35901328> - synthesis: c:/lscc/radiant/2023.2/ip/pmi/pmi_ram_dp.v(48): analyzing included file c:/lscc/radiant/2023.2/ip/pmi/../avant/ram_dp/rtl/lscc_ram_dp.v. VERI-1328 INFO <35901328> - synthesis: c:/lscc/radiant/2023.2/ip/pmi/pmi_lifcl.v(16): analyzing included file c:/lscc/radiant/2023.2/ip/pmi/pmi_ram_dp_be.v. VERI-1328 INFO <35901328> - synthesis: c:/lscc/radiant/2023.2/ip/pmi/pmi_ram_dp_be.v(49): analyzing included file c:/lscc/radiant/2023.2/ip/pmi/../avant/ram_dp/rtl/lscc_ram_dp.v. VERI-1328 INFO <35901328> - synthesis: c:/lscc/radiant/2023.2/ip/pmi/pmi_lifcl.v(17): analyzing included file c:/lscc/radiant/2023.2/ip/pmi/pmi_ram_dp_true.v. VERI-1328 INFO <35901328> - synthesis: c:/lscc/radiant/2023.2/ip/pmi/pmi_ram_dp_true.v(49): analyzing included file c:/lscc/radiant/2023.2/ip/pmi/../avant/ram_dp_true/rtl/lscc_ram_dp_true.v. VERI-1328 INFO <35901328> - synthesis: c:/lscc/radiant/2023.2/ip/pmi/pmi_lifcl.v(18): analyzing included file c:/lscc/radiant/2023.2/ip/pmi/pmi_ram_dq.v. VERI-1328 INFO <35901328> - synthesis: c:/lscc/radiant/2023.2/ip/pmi/pmi_ram_dq.v(45): analyzing included file c:/lscc/radiant/2023.2/ip/pmi/../avant/ram_dq/rtl/lscc_ram_dq.v. VERI-1328 INFO <35901328> - synthesis: c:/lscc/radiant/2023.2/ip/pmi/pmi_lifcl.v(19): analyzing included file c:/lscc/radiant/2023.2/ip/pmi/pmi_ram_dq_be.v. VERI-1328 INFO <35901328> - synthesis: c:/lscc/radiant/2023.2/ip/pmi/pmi_ram_dq_be.v(45): analyzing included file c:/lscc/radiant/2023.2/ip/pmi/../avant/ram_dq/rtl/lscc_ram_dq.v. VERI-1328 INFO <35901328> - synthesis: c:/lscc/radiant/2023.2/ip/pmi/pmi_lifcl.v(20): analyzing included file c:/lscc/radiant/2023.2/ip/pmi/pmi_rom.v. VERI-1328 INFO <35901328> - synthesis: c:/lscc/radiant/2023.2/ip/pmi/pmi_rom.v(45): analyzing included file c:/lscc/radiant/2023.2/ip/pmi/../avant/rom/rtl/lscc_rom.v. VERI-1328 INFO <35901328> - synthesis: c:/lscc/radiant/2023.2/ip/pmi/pmi_lifcl.v(21): analyzing included file c:/lscc/radiant/2023.2/ip/pmi/pmi_sub.v. VERI-1328 INFO <35901328> - synthesis: c:/lscc/radiant/2023.2/ip/pmi/pmi_sub.v(50): analyzing included file c:/lscc/radiant/2023.2/ip/pmi/../common/subtractor/rtl/lscc_subtractor.v. VERI-1328 Analyzing VHDL file c:/lscc/radiant/2023.2/ip/pmi/pmi_lifcl.vhd. VHDL-1481 Analyzing VHDL file c:/lscc/radiant/2023.2/ip/pmi/pmi_lifcl.vhd INFO <35921014> - synthesis: c:/lscc/radiant/2023.2/ip/pmi/pmi_lifcl.vhd(4): analyzing package components. VHDL-1014 Analyzing VHDL file c:/users/ssyahril/downloads/fae_f2f_training_labs_v2/fae_f2f_training_labs_v2/lab_03/source/impl_1/top.vhd. VHDL-1481 Analyzing VHDL file c:/users/ssyahril/downloads/fae_f2f_training_labs_v2/fae_f2f_training_labs_v2/lab_03/source/impl_1/top.vhd INFO <35921012> - synthesis: c:/users/ssyahril/downloads/fae_f2f_training_labs_v2/fae_f2f_training_labs_v2/lab_03/source/impl_1/top.vhd(7): analyzing entity top. VHDL-1012 INFO <35921010> - synthesis: c:/users/ssyahril/downloads/fae_f2f_training_labs_v2/fae_f2f_training_labs_v2/lab_03/source/impl_1/top.vhd(16): analyzing architecture behave. VHDL-1010 INFO <35921504> - synthesis: The default VHDL library search path is now "C:/Users/ssyahril/Downloads/FAE_F2F_Training_Labs_V2/FAE_F2F_Training_Labs_V2/LAB_03/impl_1". VHDL-1504 Top module language type = VHDL. Top module name (VHDL, mixed language): top ### Number of Logic Cells: 13824 ### Number of RAM Blocks: 24 ### Number of DSP Blocks: 198 ### Number of PLLs: 2 ### Number of IO Pins: 71 ########################################################## WARNING <35935040> - synthesis: Register CNT2_i2 clock is stuck at Zero. VDB-5040 CRITICAL <35001747> - synthesis: Bit(s) of register CNT2_e2 stuck at '0': 7, 6, 5, 4, 3, 2, 1 CRITICAL <35001748> - synthesis: Bit(s) of register CNT2_e2 stuck at '1': 0 WARNING <35935040> - synthesis: Register CNT2_i17 clock is stuck at Zero. VDB-5040 WARNING <35935040> - synthesis: Register CNT1_i2 clock is stuck at Zero. VDB-5040 CRITICAL <35001747> - synthesis: Bit(s) of register CNT1_e2 stuck at '0': 1 CRITICAL <35001748> - synthesis: Bit(s) of register CNT1_e2 stuck at '1': 0 WARNING <35935040> - synthesis: Register CNT1_i17 clock is stuck at Zero. VDB-5040 CRITICAL <35001747> - synthesis: Bit(s) of register CNT2_e3_e2 stuck at '0': 7, 6, 5, 4, 3, 2, 1 CRITICAL <35001748> - synthesis: Bit(s) of register CNT2_e3_e2 stuck at '1': 0 WARNING <35935040> - synthesis: Register CNT2_e3_i17 clock is stuck at Zero. VDB-5040 WARNING <35935040> - synthesis: Register CNT1_e3_i2 clock is stuck at Zero. VDB-5040 WARNING <35935040> - synthesis: Register CNT2_e3_i2 clock is stuck at Zero. VDB-5040 WARNING <35935040> - synthesis: Register CNT1_e3_i17 clock is stuck at Zero. VDB-5040 CRITICAL <35001747> - synthesis: Bit(s) of register CNT1_e3_e3_e2 stuck at '0': 1 CRITICAL <35001748> - synthesis: Bit(s) of register CNT1_e3_e3_e2 stuck at '1': 0 GSR will not be inferred because no asynchronous signal was found in the netlist. Starting design annotation.... Starting full timing analysis... Starting design annotation.... Starting full timing analysis... Starting design annotation.... Starting full timing analysis... Starting design annotation.... Starting full timing analysis... WARNING <35935047> - synthesis: Unused instance GSR_INST is removed. VDB-5047 Area Report ################### Begin Area Report (top)###################### Number of register bits => 18 of 13824 (0 % ) CCU2 => 5 DCC => 1 FD1P3DX => 18 GSR => 1 IB => 2 INV => 1 LUT4 => 3 OB => 8 ################### End Area Report ################## Number of odd-length carry chains : 0 Number of even-length carry chains : 1 Clock Report ################### Begin Clock Report ###################### Clock Nets Number of Clocks: 2 Net : clk2, loads : 8 Net : Clk_c, loads : 3 Clock Enable Nets Number of Clock Enables: 2 Net : VCC_net, loads : 50 Net : En1_c, loads : 2 Highest fanout non-clock nets Top 10 highest fanout non-clock nets: Net : VCC_net, loads : 50 Net : clk2_derived_9, loads : 8 Net : CNT1[0], loads : 3 Net : En1_c, loads : 2 Net : CNT1[1], loads : 2 Net : CNT2[7], loads : 2 Net : CNT2[6], loads : 2 Net : CNT2[5], loads : 2 Net : CNT2[4], loads : 2 Net : CNT2[3], loads : 2 ################### End Clock Report ################## Peak Memory Usage: 295 MB -------------------------------------------------------------- Total CPU Time: 7 secs Total REAL Time: 8 secs -------------------------------------------------------------- Checksum -- synthesis -- netlist: 705ae1d76e65db04950817fd2b9dc699cfb0bb9d