Timing Report
Lattice Timing Report - Setup and Hold, Version Radiant Software (64-bit) 2023.2.1.288.0
Thu Jun 6 10:01:38 2024
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2023 Lattice Semiconductor Corporation, All rights reserved.
Command line: timing -sethld -sp 9_High-Performance_1.0V -hsp m -v 10 -u 10 -endpoints 10 -nperend 1 -html -rpt lab07_impl_1.tw1 lab07_impl_1_map.udb -gui -msgset C:/Users/ssyahril/Downloads/FAE_F2F_Training_Labs_V2/FAE_F2F_Training_Labs_V2/LAB_07/promote.xml
-------------------------------------------
Design: top
Family: LFCPNX
Device: LFCPNX-50
Package: ASG256
Performance: 9_High-Performance_1.0V
Package Status: Final Version 16
Performance Hardware Data Status : Final Version 3.9
-------------------------------------------
=====================================================================
Table of Contents
=====================================================================
1 Timing Overview
1.1 SDC Constraints
1.2 Constraint Coverage
1.3 Overall Summary
1.4 Unconstrained Report
1.5 Combinational Loop
2 Setup at Speed Grade 9_High-Performance_1.0V Corner at 85 Degrees
2.1 Clock Summary
2.2 Endpoint slacks
2.3 Detailed Report
3 Setup at Speed Grade 9_High-Performance_1.0V Corner at 0 Degrees
3.1 Clock Summary
3.2 Endpoint slacks
3.3 Detailed Report
4 Hold at Speed Grade m Corner at 0 Degrees
4.1 Endpoint slacks
4.2 Detailed Report
=====================================================================
End of Table of Contents
=====================================================================
1 Timing Overview
1.1 SDC Constraints
create_clock -name {ClkA} -period 10 [get_ports ClkA]
create_clock -name {ClkB} -period 9.80392156862745 [get_ports ClkB]
set_false_path -from [get_clocks ClkA] -to [get_clocks ClkB]
set_false_path -from [get_clocks ClkB] -to [get_clocks ClkA]
set_false_path -through [get_nets {B_sig A_Sig}]
set_false_path -from [get_pins A_Sig_c.ff_inst/Q] -to [get_pins {MyCDC01/A_Sig1_c.ff_inst/CE MyCDC01/A_Sig_c.ff_inst/CE MyCDC01/A_Sig1_c.ff_inst/LSR MyCDC01/A_Sig_c.ff_inst/LSR MyCDC01/A_Sig_c.ff_inst/DF MyCDC02/A_Sig1.ff_inst/CE MyCDC02/A_Sig_c.ff_inst/CE MyCDC02/A_Sig1.ff_inst/LSR MyCDC02/A_Sig_c.ff_inst/LSR MyCDC02/A_Sig_c.ff_inst/DF}]
set_false_path -from [get_pins B_sig_c.ff_inst/Q] -to [get_pins {MyCDC01/A_Sig1_c.ff_inst/CE MyCDC01/A_Sig_c.ff_inst/CE MyCDC01/A_Sig1_c.ff_inst/LSR MyCDC01/A_Sig_c.ff_inst/LSR MyCDC01/A_Sig_c.ff_inst/DF MyCDC02/A_Sig1.ff_inst/CE MyCDC02/A_Sig_c.ff_inst/CE MyCDC02/A_Sig1.ff_inst/LSR MyCDC02/A_Sig_c.ff_inst/LSR MyCDC02/A_Sig_c.ff_inst/DF}]
1.2 Constraint Coverage
Constraint Coverage: 62.5%
1.3 Overall Summary
Setup at Speed Grade 9_High-Performance_1.0V Corner at 85 Degrees Timing Errors: 0 endpoints; Total Negative Slack: 0.000 ns
Setup at Speed Grade 9_High-Performance_1.0V Corner at 0 Degrees Timing Errors: 0 endpoints; Total Negative Slack: 0.000 ns
Hold at Speed Grade m Corner at 0 Degrees Timing Errors: 0 endpoints; Total Negative Slack: 0.000 ns
1.4 Unconstrained Report
1.4.1 Unconstrained Start/End Points
Clocked but unconstrained timing start points
-------------------------------------------------------------------
Listing 2 Start Points | Type
-------------------------------------------------------------------
out2_i1.ff_inst/Q | No required time
out1_i0.ff_inst/Q | No required time
-------------------------------------------------------------------
|
Number of unconstrained timing start po |
ints | 2
|
-------------------------------------------------------------------
Clocked but unconstrained timing end points
-------------------------------------------------------------------
Listing 2 End Points | Type
-------------------------------------------------------------------
A_Sig_c.ff_inst/DF | No arrival time
B_sig_c.ff_inst/DF | No arrival time
-------------------------------------------------------------------
|
Number of unconstrained timing end poin |
ts | 2
|
-------------------------------------------------------------------
1.4.2 Start/End Points Without Timing Constraints
I/O ports without constraint
----------------------------
Possible constraints to use on I/O ports are:
set_input_delay,
set_output_delay,
set_max_delay,
create_clock,
create_generated_clock,
...
-------------------------------------------------------------------
Listing 4 Start or End Points | Type
-------------------------------------------------------------------
A | input
B | input
out2 | output
out1 | output
-------------------------------------------------------------------
|
Number of I/O ports without constraint | 4
|
-------------------------------------------------------------------
Nets without clock definition
Define a clock on a top level port or a generated clock on a clock divider pin associated with this net(s).
--------------------------------------------------
There is no instance satisfying reporting criteria
1.5 Combinational Loop
None
2 Setup at Speed Grade 9_High-Performance_1.0V Corner at 85 Degrees
2.1 Clock Summary
2.1.1 Clock "ClkA"
create_clock -name {ClkA} -period 10 [get_ports ClkA]
Single Clock Domain
-------------------------------------------------------------------------------------------------------
Clock ClkA | | Period | Frequency
-------------------------------------------------------------------------------------------------------
From ClkA | Target | 10.000 ns | 100.000 MHz
| Actual (all paths) | 5.000 ns | 200.000 MHz
ClkA_pad.bb_inst/B (MPW) | (50% duty cycle) | 5.000 ns | 200.000 MHz
-------------------------------------------------------------------------------------------------------
Clock Domain Crossing
------------------------------------------------------------------------------------------------------
Clock ClkA | Worst Time Between Edges | Comment
------------------------------------------------------------------------------------------------------
From ClkB | ---- | False path
------------------------------------------------------------------------------------------------------
2.1.2 Clock "ClkB"
create_clock -name {ClkB} -period 9.80392156862745 [get_ports ClkB]
Single Clock Domain
-------------------------------------------------------------------------------------------------------
Clock ClkB | | Period | Frequency
-------------------------------------------------------------------------------------------------------
From ClkB | Target | 9.804 ns | 102.000 MHz
| Actual (all paths) | 5.000 ns | 200.000 MHz
ClkB_pad.bb_inst/B (MPW) | (50% duty cycle) | 5.000 ns | 200.000 MHz
-------------------------------------------------------------------------------------------------------
Clock Domain Crossing
------------------------------------------------------------------------------------------------------
Clock ClkB | Worst Time Between Edges | Comment
------------------------------------------------------------------------------------------------------
From ClkA | ---- | False path
------------------------------------------------------------------------------------------------------
2.2 Endpoint slacks
-------------------------------------------------------
Listing 4 End Points | Slack
-------------------------------------------------------
out2_i1.ff_inst/DF | 9.045 ns
MyCDC01/A_Sig1_c.ff_inst/DF | 9.235 ns
out1_i0.ff_inst/DF | 9.241 ns
MyCDC02/A_Sig1.ff_inst/DF | 9.431 ns
-------------------------------------------------------
|
Setup # of endpoints with negative slack:| 0
|
-------------------------------------------------------
2.3 Detailed Report
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
Detail report of critical paths
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Detailed Report for timing paths
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++++Path 1 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Path Begin : MyCDC01/A_Sig1_c.ff_inst/Q (SLICE)
Path End : out2_i1.ff_inst/DF (SLICE)
Source Clock : ClkB (R)
Destination Clock: ClkB (R)
Logic Level : 2
Delay Ratio : 36.7% (route), 63.3% (logic)
Clock Skew : 0.000 ns
Setup Constraint : 9.803 ns
Common Path Skew : 0.000 ns
Path Slack : 9.044 ns (Passed)
Source Clock Path
{
"path_begin":
{
"type":"port",
"log_name":"ClkB",
"phy_name":"ClkB"
},
"path_end":
{
"type":"pin",
"log_name":"MyCDC01/A_Sig1_c.ff_inst/CLK",
"phy_name":"MyCDC01.A_Sig1_c.SLICE_2/CLK"
},
"path_sections":[
{
"type":"net_delay",
"net":
{
"log_name":"ClkB",
"phy_name":"ClkB"
},
"arrive":0.000,
"delay":0.000
},
{
"type":"site_delay",
"pin0":
{
"log_name":"ClkB_pad.bb_inst/B",
"phy_name":"ClkB_pad.bb_inst/IOPAD"
},
"pin1":
{
"log_name":"ClkB_pad.bb_inst/O",
"phy_name":"ClkB_pad.bb_inst/PADDI"
},
"arrive":1.366,
"delay":1.366
},
{
"type":"net_delay",
"net":
{
"log_name":"MyCDC01/ClkB_c",
"phy_name":"ClkB_c"
},
"arrive":1.987,
"delay":0.621
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":1.987,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- -------------- ---------------- --------- --------------------- ------
ClkB top CLOCK LATENCY 0.000 0.000 1
ClkB NET DELAY 0.000 0.000 1
ClkB_pad.bb_inst/B->ClkB_pad.bb_inst/O SEIO33_CORE PADI_DEL 1.366 1.366 4
MyCDC01/ClkB_c NET DELAY 0.621 1.987 4
MyCDC01/A_Sig1_c.ff_inst/CLK CLOCK PIN 0.000 1.987 1
Data Path
{
"path_begin":
{
"type":"pin",
"log_name":"MyCDC01/A_Sig1_c.ff_inst/Q",
"phy_name":"MyCDC01.A_Sig1_c.SLICE_2/Q0"
},
"path_end":
{
"type":"pin",
"log_name":"out2_i1.ff_inst/DF",
"phy_name":"SLICE_4/DI0"
},
"path_sections":[
{
"type":"site_delay",
"pin0":
{
"log_name":"MyCDC01/A_Sig1_c.ff_inst/CLK",
"phy_name":"MyCDC01.A_Sig1_c.SLICE_2/CLK"
},
"pin1":
{
"log_name":"MyCDC01/A_Sig1_c.ff_inst/Q",
"phy_name":"MyCDC01.A_Sig1_c.SLICE_2/Q0"
},
"arrive":2.291,
"delay":0.304
},
{
"type":"net_delay",
"net":
{
"log_name":"MyCDC01/A_Sig1",
"phy_name":"A_Sig1"
},
"arrive":2.591,
"delay":0.300
},
{
"type":"site_delay",
"pin0":
{
"log_name":"i9_2_lut/B",
"phy_name":"SLICE_4/B0"
},
"pin1":
{
"log_name":"i9_2_lut/Z",
"phy_name":"SLICE_4/F0"
},
"arrive":2.804,
"delay":0.213
},
{
"type":"net_delay",
"net":
{
"log_name":"out2_c_N_2",
"phy_name":"out2_c_N_2"
},
"arrive":2.804,
"delay":0.000
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":2.804,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- -------------- ---------------- --------- --------------------- ------
MyCDC01/A_Sig1_c.ff_inst/CLK->MyCDC01/A_Sig1_c.ff_inst/Q
SLICE REG_DEL 0.304 2.291 1
MyCDC01/A_Sig1 NET DELAY 0.300 2.591 1
i9_2_lut/B->i9_2_lut/Z SLICE CTOF_DEL 0.213 2.804 1
out2_c_N_2 NET DELAY 0.000 2.804 1
out2_i1.ff_inst/DF ENDPOINT 0.000 2.804 1
Destination Clock Path
{
"path_begin":
{
"type":"port",
"log_name":"ClkB",
"phy_name":"ClkB"
},
"path_end":
{
"type":"pin",
"log_name":"out2_i1.ff_inst/CLK",
"phy_name":"SLICE_4/CLK"
},
"path_sections":[
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":9.803,
"delay":0.000
},
{
"type":"net_delay",
"net":
{
"log_name":"ClkB",
"phy_name":"ClkB"
},
"arrive":9.803,
"delay":0.000
},
{
"type":"site_delay",
"pin0":
{
"log_name":"ClkB_pad.bb_inst/B",
"phy_name":"ClkB_pad.bb_inst/IOPAD"
},
"pin1":
{
"log_name":"ClkB_pad.bb_inst/O",
"phy_name":"ClkB_pad.bb_inst/PADDI"
},
"arrive":11.169,
"delay":1.366
},
{
"type":"net_delay",
"net":
{
"log_name":"MyCDC01/ClkB_c",
"phy_name":"ClkB_c"
},
"arrive":11.790,
"delay":0.621
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":11.790,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- -------------- ---------------- --------- --------------------- ------
CONSTRAINT 0.000 9.803 1
ClkB top CLOCK LATENCY 0.000 9.803 1
ClkB NET DELAY 0.000 9.803 1
ClkB_pad.bb_inst/B->ClkB_pad.bb_inst/O SEIO33_CORE PADI_DEL 1.366 11.169 4
MyCDC01/ClkB_c NET DELAY 0.621 11.790 4
out2_i1.ff_inst/CLK CLOCK PIN 0.000 11.790 1
Uncertainty -(0.000) 11.790
Common Path Skew 0.000 11.790
Setup time -(-0.058) 11.848
---------------------------------------- -------------- ---------------- --------- --------------------- ------
Required Time 11.848
Arrival Time -(2.804)
---------------------------------------- -------------- ---------------- --------- --------------------- ------
Path Slack (Passed) 9.044
++++ Path 2 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Path Begin : MyCDC01/A_Sig_c.ff_inst/Q (SLICE)
Path End : MyCDC01/A_Sig1_c.ff_inst/DF (SLICE)
Source Clock : ClkB (R)
Destination Clock: ClkB (R)
Logic Level : 1
Delay Ratio : 49.7% (route), 50.3% (logic)
Clock Skew : 0.000 ns
Setup Constraint : 9.803 ns
Common Path Skew : 0.000 ns
Path Slack : 9.234 ns (Passed)
Source Clock Path
{
"path_begin":
{
"type":"port",
"log_name":"ClkB",
"phy_name":"ClkB"
},
"path_end":
{
"type":"pin",
"log_name":"MyCDC01/A_Sig_c.ff_inst/CLK",
"phy_name":"MyCDC01.A_Sig_c.SLICE_3/CLK"
},
"path_sections":[
{
"type":"net_delay",
"net":
{
"log_name":"ClkB",
"phy_name":"ClkB"
},
"arrive":0.000,
"delay":0.000
},
{
"type":"site_delay",
"pin0":
{
"log_name":"ClkB_pad.bb_inst/B",
"phy_name":"ClkB_pad.bb_inst/IOPAD"
},
"pin1":
{
"log_name":"ClkB_pad.bb_inst/O",
"phy_name":"ClkB_pad.bb_inst/PADDI"
},
"arrive":1.366,
"delay":1.366
},
{
"type":"net_delay",
"net":
{
"log_name":"MyCDC01/ClkB_c",
"phy_name":"ClkB_c"
},
"arrive":1.987,
"delay":0.621
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":1.987,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- -------------- ---------------- --------- --------------------- ------
ClkB top CLOCK LATENCY 0.000 0.000 1
ClkB NET DELAY 0.000 0.000 1
ClkB_pad.bb_inst/B->ClkB_pad.bb_inst/O SEIO33_CORE PADI_DEL 1.366 1.366 4
MyCDC01/ClkB_c NET DELAY 0.621 1.987 4
MyCDC01/A_Sig_c.ff_inst/CLK CLOCK PIN 0.000 1.987 1
Data Path
{
"path_begin":
{
"type":"pin",
"log_name":"MyCDC01/A_Sig_c.ff_inst/Q",
"phy_name":"MyCDC01.A_Sig_c.SLICE_3/Q0"
},
"path_end":
{
"type":"pin",
"log_name":"MyCDC01/A_Sig1_c.ff_inst/DF",
"phy_name":"MyCDC01.A_Sig1_c.SLICE_2/M0"
},
"path_sections":[
{
"type":"site_delay",
"pin0":
{
"log_name":"MyCDC01/A_Sig_c.ff_inst/CLK",
"phy_name":"MyCDC01.A_Sig_c.SLICE_3/CLK"
},
"pin1":
{
"log_name":"MyCDC01/A_Sig_c.ff_inst/Q",
"phy_name":"MyCDC01.A_Sig_c.SLICE_3/Q0"
},
"arrive":2.291,
"delay":0.304
},
{
"type":"net_delay",
"net":
{
"log_name":"MyCDC01/A_Sig_adj_3",
"phy_name":"MyCDC01.A_Sig_adj_3"
},
"arrive":2.591,
"delay":0.300
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":2.591,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- -------------- ---------------- --------- --------------------- ------
MyCDC01/A_Sig_c.ff_inst/CLK->MyCDC01/A_Sig_c.ff_inst/Q
SLICE REG_DEL 0.304 2.291 1
MyCDC01/A_Sig_adj_3 NET DELAY 0.300 2.591 1
MyCDC01/A_Sig1_c.ff_inst/DF ENDPOINT 0.000 2.591 1
Destination Clock Path
{
"path_begin":
{
"type":"port",
"log_name":"ClkB",
"phy_name":"ClkB"
},
"path_end":
{
"type":"pin",
"log_name":"MyCDC01/A_Sig1_c.ff_inst/CLK",
"phy_name":"MyCDC01.A_Sig1_c.SLICE_2/CLK"
},
"path_sections":[
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":9.803,
"delay":0.000
},
{
"type":"net_delay",
"net":
{
"log_name":"ClkB",
"phy_name":"ClkB"
},
"arrive":9.803,
"delay":0.000
},
{
"type":"site_delay",
"pin0":
{
"log_name":"ClkB_pad.bb_inst/B",
"phy_name":"ClkB_pad.bb_inst/IOPAD"
},
"pin1":
{
"log_name":"ClkB_pad.bb_inst/O",
"phy_name":"ClkB_pad.bb_inst/PADDI"
},
"arrive":11.169,
"delay":1.366
},
{
"type":"net_delay",
"net":
{
"log_name":"MyCDC01/ClkB_c",
"phy_name":"ClkB_c"
},
"arrive":11.790,
"delay":0.621
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":11.790,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- -------------- ---------------- --------- --------------------- ------
CONSTRAINT 0.000 9.803 1
ClkB top CLOCK LATENCY 0.000 9.803 1
ClkB NET DELAY 0.000 9.803 1
ClkB_pad.bb_inst/B->ClkB_pad.bb_inst/O SEIO33_CORE PADI_DEL 1.366 11.169 4
MyCDC01/ClkB_c NET DELAY 0.621 11.790 4
MyCDC01/A_Sig1_c.ff_inst/CLK CLOCK PIN 0.000 11.790 1
Uncertainty -(0.000) 11.790
Common Path Skew 0.000 11.790
Setup time -(-0.035) 11.825
---------------------------------------- -------------- ---------------- --------- --------------------- ------
Required Time 11.825
Arrival Time -(2.591)
---------------------------------------- -------------- ---------------- --------- --------------------- ------
Path Slack (Passed) 9.234
++++ Path 3 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Path Begin : MyCDC02/A_Sig1.ff_inst/Q (SLICE)
Path End : out1_i0.ff_inst/DF (SLICE)
Source Clock : ClkA (R)
Destination Clock: ClkA (R)
Logic Level : 2
Delay Ratio : 36.7% (route), 63.3% (logic)
Clock Skew : 0.000 ns
Setup Constraint : 10.000 ns
Common Path Skew : 0.000 ns
Path Slack : 9.241 ns (Passed)
Source Clock Path
{
"path_begin":
{
"type":"port",
"log_name":"ClkA",
"phy_name":"ClkA"
},
"path_end":
{
"type":"pin",
"log_name":"MyCDC02/A_Sig1.ff_inst/CLK",
"phy_name":"MyCDC02.A_Sig1.SLICE_0/CLK"
},
"path_sections":[
{
"type":"net_delay",
"net":
{
"log_name":"ClkA",
"phy_name":"ClkA"
},
"arrive":0.000,
"delay":0.000
},
{
"type":"site_delay",
"pin0":
{
"log_name":"ClkA_pad.bb_inst/B",
"phy_name":"ClkA_pad.bb_inst/IOPAD"
},
"pin1":
{
"log_name":"ClkA_pad.bb_inst/O",
"phy_name":"ClkA_pad.bb_inst/PADDI"
},
"arrive":1.366,
"delay":1.366
},
{
"type":"net_delay",
"net":
{
"log_name":"MyCDC02/ClkA_c",
"phy_name":"ClkA_c"
},
"arrive":1.987,
"delay":0.621
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":1.987,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- -------------- ---------------- --------- --------------------- ------
ClkA top CLOCK LATENCY 0.000 0.000 1
ClkA NET DELAY 0.000 0.000 1
ClkA_pad.bb_inst/B->ClkA_pad.bb_inst/O SEIO33_CORE PADI_DEL 1.366 1.366 4
MyCDC02/ClkA_c NET DELAY 0.621 1.987 4
MyCDC02/A_Sig1.ff_inst/CLK CLOCK PIN 0.000 1.987 1
Data Path
{
"path_begin":
{
"type":"pin",
"log_name":"MyCDC02/A_Sig1.ff_inst/Q",
"phy_name":"MyCDC02.A_Sig1.SLICE_0/Q0"
},
"path_end":
{
"type":"pin",
"log_name":"out1_i0.ff_inst/DF",
"phy_name":"SLICE_6/DI0"
},
"path_sections":[
{
"type":"site_delay",
"pin0":
{
"log_name":"MyCDC02/A_Sig1.ff_inst/CLK",
"phy_name":"MyCDC02.A_Sig1.SLICE_0/CLK"
},
"pin1":
{
"log_name":"MyCDC02/A_Sig1.ff_inst/Q",
"phy_name":"MyCDC02.A_Sig1.SLICE_0/Q0"
},
"arrive":2.291,
"delay":0.304
},
{
"type":"net_delay",
"net":
{
"log_name":"MyCDC02/B_sig1",
"phy_name":"B_sig1"
},
"arrive":2.591,
"delay":0.300
},
{
"type":"site_delay",
"pin0":
{
"log_name":"i5_2_lut/B",
"phy_name":"SLICE_6/B0"
},
"pin1":
{
"log_name":"i5_2_lut/Z",
"phy_name":"SLICE_6/F0"
},
"arrive":2.804,
"delay":0.213
},
{
"type":"net_delay",
"net":
{
"log_name":"out1_c_N_1",
"phy_name":"out1_c_N_1"
},
"arrive":2.804,
"delay":0.000
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":2.804,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- -------------- ---------------- --------- --------------------- ------
MyCDC02/A_Sig1.ff_inst/CLK->MyCDC02/A_Sig1.ff_inst/Q
SLICE REG_DEL 0.304 2.291 1
MyCDC02/B_sig1 NET DELAY 0.300 2.591 1
i5_2_lut/B->i5_2_lut/Z SLICE CTOF_DEL 0.213 2.804 1
out1_c_N_1 NET DELAY 0.000 2.804 1
out1_i0.ff_inst/DF ENDPOINT 0.000 2.804 1
Destination Clock Path
{
"path_begin":
{
"type":"port",
"log_name":"ClkA",
"phy_name":"ClkA"
},
"path_end":
{
"type":"pin",
"log_name":"out1_i0.ff_inst/CLK",
"phy_name":"SLICE_6/CLK"
},
"path_sections":[
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":10.000,
"delay":0.000
},
{
"type":"net_delay",
"net":
{
"log_name":"ClkA",
"phy_name":"ClkA"
},
"arrive":10.000,
"delay":0.000
},
{
"type":"site_delay",
"pin0":
{
"log_name":"ClkA_pad.bb_inst/B",
"phy_name":"ClkA_pad.bb_inst/IOPAD"
},
"pin1":
{
"log_name":"ClkA_pad.bb_inst/O",
"phy_name":"ClkA_pad.bb_inst/PADDI"
},
"arrive":11.366,
"delay":1.366
},
{
"type":"net_delay",
"net":
{
"log_name":"MyCDC02/ClkA_c",
"phy_name":"ClkA_c"
},
"arrive":11.987,
"delay":0.621
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":11.987,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- -------------- ---------------- --------- --------------------- ------
CONSTRAINT 0.000 10.000 1
ClkA top CLOCK LATENCY 0.000 10.000 1
ClkA NET DELAY 0.000 10.000 1
ClkA_pad.bb_inst/B->ClkA_pad.bb_inst/O SEIO33_CORE PADI_DEL 1.366 11.366 4
MyCDC02/ClkA_c NET DELAY 0.621 11.987 4
out1_i0.ff_inst/CLK CLOCK PIN 0.000 11.987 1
Uncertainty -(0.000) 11.987
Common Path Skew 0.000 11.987
Setup time -(-0.058) 12.045
---------------------------------------- -------------- ---------------- --------- --------------------- ------
Required Time 12.045
Arrival Time -(2.804)
---------------------------------------- -------------- ---------------- --------- --------------------- ------
Path Slack (Passed) 9.241
++++ Path 4 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Path Begin : MyCDC02/A_Sig_c.ff_inst/Q (SLICE)
Path End : MyCDC02/A_Sig1.ff_inst/DF (SLICE)
Source Clock : ClkA (R)
Destination Clock: ClkA (R)
Logic Level : 1
Delay Ratio : 49.7% (route), 50.3% (logic)
Clock Skew : 0.000 ns
Setup Constraint : 10.000 ns
Common Path Skew : 0.000 ns
Path Slack : 9.431 ns (Passed)
Source Clock Path
{
"path_begin":
{
"type":"port",
"log_name":"ClkA",
"phy_name":"ClkA"
},
"path_end":
{
"type":"pin",
"log_name":"MyCDC02/A_Sig_c.ff_inst/CLK",
"phy_name":"MyCDC02.A_Sig_c.SLICE_1/CLK"
},
"path_sections":[
{
"type":"net_delay",
"net":
{
"log_name":"ClkA",
"phy_name":"ClkA"
},
"arrive":0.000,
"delay":0.000
},
{
"type":"site_delay",
"pin0":
{
"log_name":"ClkA_pad.bb_inst/B",
"phy_name":"ClkA_pad.bb_inst/IOPAD"
},
"pin1":
{
"log_name":"ClkA_pad.bb_inst/O",
"phy_name":"ClkA_pad.bb_inst/PADDI"
},
"arrive":1.366,
"delay":1.366
},
{
"type":"net_delay",
"net":
{
"log_name":"MyCDC02/ClkA_c",
"phy_name":"ClkA_c"
},
"arrive":1.987,
"delay":0.621
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":1.987,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- -------------- ---------------- --------- --------------------- ------
ClkA top CLOCK LATENCY 0.000 0.000 1
ClkA NET DELAY 0.000 0.000 1
ClkA_pad.bb_inst/B->ClkA_pad.bb_inst/O SEIO33_CORE PADI_DEL 1.366 1.366 4
MyCDC02/ClkA_c NET DELAY 0.621 1.987 4
MyCDC02/A_Sig_c.ff_inst/CLK CLOCK PIN 0.000 1.987 1
Data Path
{
"path_begin":
{
"type":"pin",
"log_name":"MyCDC02/A_Sig_c.ff_inst/Q",
"phy_name":"MyCDC02.A_Sig_c.SLICE_1/Q0"
},
"path_end":
{
"type":"pin",
"log_name":"MyCDC02/A_Sig1.ff_inst/DF",
"phy_name":"MyCDC02.A_Sig1.SLICE_0/M0"
},
"path_sections":[
{
"type":"site_delay",
"pin0":
{
"log_name":"MyCDC02/A_Sig_c.ff_inst/CLK",
"phy_name":"MyCDC02.A_Sig_c.SLICE_1/CLK"
},
"pin1":
{
"log_name":"MyCDC02/A_Sig_c.ff_inst/Q",
"phy_name":"MyCDC02.A_Sig_c.SLICE_1/Q0"
},
"arrive":2.291,
"delay":0.304
},
{
"type":"net_delay",
"net":
{
"log_name":"MyCDC02/A_Sig",
"phy_name":"MyCDC02.A_Sig"
},
"arrive":2.591,
"delay":0.300
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":2.591,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- -------------- ---------------- --------- --------------------- ------
MyCDC02/A_Sig_c.ff_inst/CLK->MyCDC02/A_Sig_c.ff_inst/Q
SLICE REG_DEL 0.304 2.291 1
MyCDC02/A_Sig NET DELAY 0.300 2.591 1
MyCDC02/A_Sig1.ff_inst/DF ENDPOINT 0.000 2.591 1
Destination Clock Path
{
"path_begin":
{
"type":"port",
"log_name":"ClkA",
"phy_name":"ClkA"
},
"path_end":
{
"type":"pin",
"log_name":"MyCDC02/A_Sig1.ff_inst/CLK",
"phy_name":"MyCDC02.A_Sig1.SLICE_0/CLK"
},
"path_sections":[
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":10.000,
"delay":0.000
},
{
"type":"net_delay",
"net":
{
"log_name":"ClkA",
"phy_name":"ClkA"
},
"arrive":10.000,
"delay":0.000
},
{
"type":"site_delay",
"pin0":
{
"log_name":"ClkA_pad.bb_inst/B",
"phy_name":"ClkA_pad.bb_inst/IOPAD"
},
"pin1":
{
"log_name":"ClkA_pad.bb_inst/O",
"phy_name":"ClkA_pad.bb_inst/PADDI"
},
"arrive":11.366,
"delay":1.366
},
{
"type":"net_delay",
"net":
{
"log_name":"MyCDC02/ClkA_c",
"phy_name":"ClkA_c"
},
"arrive":11.987,
"delay":0.621
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":11.987,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- -------------- ---------------- --------- --------------------- ------
CONSTRAINT 0.000 10.000 1
ClkA top CLOCK LATENCY 0.000 10.000 1
ClkA NET DELAY 0.000 10.000 1
ClkA_pad.bb_inst/B->ClkA_pad.bb_inst/O SEIO33_CORE PADI_DEL 1.366 11.366 4
MyCDC02/ClkA_c NET DELAY 0.621 11.987 4
MyCDC02/A_Sig1.ff_inst/CLK CLOCK PIN 0.000 11.987 1
Uncertainty -(0.000) 11.987
Common Path Skew 0.000 11.987
Setup time -(-0.035) 12.022
---------------------------------------- -------------- ---------------- --------- --------------------- ------
Required Time 12.022
Arrival Time -(2.591)
---------------------------------------- -------------- ---------------- --------- --------------------- ------
Path Slack (Passed) 9.431
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
End of Detailed Report for timing paths
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
##########################################################
3 Setup at Speed Grade 9_High-Performance_1.0V Corner at 0 Degrees
3.1 Clock Summary
3.1.1 Clock "ClkA"
create_clock -name {ClkA} -period 10 [get_ports ClkA]
Single Clock Domain
-------------------------------------------------------------------------------------------------------
Clock ClkA | | Period | Frequency
-------------------------------------------------------------------------------------------------------
From ClkA | Target | 10.000 ns | 100.000 MHz
| Actual (all paths) | 5.000 ns | 200.000 MHz
ClkA_pad.bb_inst/B (MPW) | (50% duty cycle) | 5.000 ns | 200.000 MHz
-------------------------------------------------------------------------------------------------------
Clock Domain Crossing
------------------------------------------------------------------------------------------------------
Clock ClkA | Worst Time Between Edges | Comment
------------------------------------------------------------------------------------------------------
From ClkB | ---- | False path
------------------------------------------------------------------------------------------------------
3.1.2 Clock "ClkB"
create_clock -name {ClkB} -period 9.80392156862745 [get_ports ClkB]
Single Clock Domain
-------------------------------------------------------------------------------------------------------
Clock ClkB | | Period | Frequency
-------------------------------------------------------------------------------------------------------
From ClkB | Target | 9.804 ns | 102.000 MHz
| Actual (all paths) | 5.000 ns | 200.000 MHz
ClkB_pad.bb_inst/B (MPW) | (50% duty cycle) | 5.000 ns | 200.000 MHz
-------------------------------------------------------------------------------------------------------
Clock Domain Crossing
------------------------------------------------------------------------------------------------------
Clock ClkB | Worst Time Between Edges | Comment
------------------------------------------------------------------------------------------------------
From ClkA | ---- | False path
------------------------------------------------------------------------------------------------------
3.2 Endpoint slacks
-------------------------------------------------------
Listing 4 End Points | Slack
-------------------------------------------------------
out2_i1.ff_inst/DF | 9.044 ns
MyCDC01/A_Sig1_c.ff_inst/DF | 9.234 ns
out1_i0.ff_inst/DF | 9.240 ns
MyCDC02/A_Sig1.ff_inst/DF | 9.430 ns
-------------------------------------------------------
|
Setup # of endpoints with negative slack:| 0
|
-------------------------------------------------------
3.3 Detailed Report
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
Detail report of critical paths
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Detailed Report for timing paths
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++++Path 1 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Path Begin : MyCDC01/A_Sig1_c.ff_inst/Q (SLICE)
Path End : out2_i1.ff_inst/DF (SLICE)
Source Clock : ClkB (R)
Destination Clock: ClkB (R)
Logic Level : 2
Delay Ratio : 36.7% (route), 63.3% (logic)
Clock Skew : 0.000 ns
Setup Constraint : 9.803 ns
Common Path Skew : 0.000 ns
Path Slack : 9.043 ns (Passed)
Source Clock Path
{
"path_begin":
{
"type":"port",
"log_name":"ClkB",
"phy_name":"ClkB"
},
"path_end":
{
"type":"pin",
"log_name":"MyCDC01/A_Sig1_c.ff_inst/CLK",
"phy_name":"MyCDC01.A_Sig1_c.SLICE_2/CLK"
},
"path_sections":[
{
"type":"net_delay",
"net":
{
"log_name":"ClkB",
"phy_name":"ClkB"
},
"arrive":0.000,
"delay":0.000
},
{
"type":"site_delay",
"pin0":
{
"log_name":"ClkB_pad.bb_inst/B",
"phy_name":"ClkB_pad.bb_inst/IOPAD"
},
"pin1":
{
"log_name":"ClkB_pad.bb_inst/O",
"phy_name":"ClkB_pad.bb_inst/PADDI"
},
"arrive":1.238,
"delay":1.238
},
{
"type":"net_delay",
"net":
{
"log_name":"MyCDC01/ClkB_c",
"phy_name":"ClkB_c"
},
"arrive":1.859,
"delay":0.621
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":1.859,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- -------------- ---------------- --------- --------------------- ------
ClkB top CLOCK LATENCY 0.000 0.000 1
ClkB NET DELAY 0.000 0.000 1
ClkB_pad.bb_inst/B->ClkB_pad.bb_inst/O SEIO33_CORE PADI_DEL 1.238 1.238 4
MyCDC01/ClkB_c NET DELAY 0.621 1.859 4
MyCDC01/A_Sig1_c.ff_inst/CLK CLOCK PIN 0.000 1.859 1
Data Path
{
"path_begin":
{
"type":"pin",
"log_name":"MyCDC01/A_Sig1_c.ff_inst/Q",
"phy_name":"MyCDC01.A_Sig1_c.SLICE_2/Q0"
},
"path_end":
{
"type":"pin",
"log_name":"out2_i1.ff_inst/DF",
"phy_name":"SLICE_4/DI0"
},
"path_sections":[
{
"type":"site_delay",
"pin0":
{
"log_name":"MyCDC01/A_Sig1_c.ff_inst/CLK",
"phy_name":"MyCDC01.A_Sig1_c.SLICE_2/CLK"
},
"pin1":
{
"log_name":"MyCDC01/A_Sig1_c.ff_inst/Q",
"phy_name":"MyCDC01.A_Sig1_c.SLICE_2/Q0"
},
"arrive":2.164,
"delay":0.305
},
{
"type":"net_delay",
"net":
{
"log_name":"MyCDC01/A_Sig1",
"phy_name":"A_Sig1"
},
"arrive":2.464,
"delay":0.300
},
{
"type":"site_delay",
"pin0":
{
"log_name":"i9_2_lut/B",
"phy_name":"SLICE_4/B0"
},
"pin1":
{
"log_name":"i9_2_lut/Z",
"phy_name":"SLICE_4/F0"
},
"arrive":2.677,
"delay":0.213
},
{
"type":"net_delay",
"net":
{
"log_name":"out2_c_N_2",
"phy_name":"out2_c_N_2"
},
"arrive":2.677,
"delay":0.000
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":2.677,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- -------------- ---------------- --------- --------------------- ------
MyCDC01/A_Sig1_c.ff_inst/CLK->MyCDC01/A_Sig1_c.ff_inst/Q
SLICE REG_DEL 0.305 2.164 1
MyCDC01/A_Sig1 NET DELAY 0.300 2.464 1
i9_2_lut/B->i9_2_lut/Z SLICE CTOF_DEL 0.213 2.677 1
out2_c_N_2 NET DELAY 0.000 2.677 1
out2_i1.ff_inst/DF ENDPOINT 0.000 2.677 1
Destination Clock Path
{
"path_begin":
{
"type":"port",
"log_name":"ClkB",
"phy_name":"ClkB"
},
"path_end":
{
"type":"pin",
"log_name":"out2_i1.ff_inst/CLK",
"phy_name":"SLICE_4/CLK"
},
"path_sections":[
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":9.803,
"delay":0.000
},
{
"type":"net_delay",
"net":
{
"log_name":"ClkB",
"phy_name":"ClkB"
},
"arrive":9.803,
"delay":0.000
},
{
"type":"site_delay",
"pin0":
{
"log_name":"ClkB_pad.bb_inst/B",
"phy_name":"ClkB_pad.bb_inst/IOPAD"
},
"pin1":
{
"log_name":"ClkB_pad.bb_inst/O",
"phy_name":"ClkB_pad.bb_inst/PADDI"
},
"arrive":11.041,
"delay":1.238
},
{
"type":"net_delay",
"net":
{
"log_name":"MyCDC01/ClkB_c",
"phy_name":"ClkB_c"
},
"arrive":11.662,
"delay":0.621
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":11.662,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- -------------- ---------------- --------- --------------------- ------
CONSTRAINT 0.000 9.803 1
ClkB top CLOCK LATENCY 0.000 9.803 1
ClkB NET DELAY 0.000 9.803 1
ClkB_pad.bb_inst/B->ClkB_pad.bb_inst/O SEIO33_CORE PADI_DEL 1.238 11.041 4
MyCDC01/ClkB_c NET DELAY 0.621 11.662 4
out2_i1.ff_inst/CLK CLOCK PIN 0.000 11.662 1
Uncertainty -(0.000) 11.662
Common Path Skew 0.000 11.662
Setup time -(-0.058) 11.720
---------------------------------------- -------------- ---------------- --------- --------------------- ------
Required Time 11.720
Arrival Time -(2.677)
---------------------------------------- -------------- ---------------- --------- --------------------- ------
Path Slack (Passed) 9.043
++++ Path 2 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Path Begin : MyCDC01/A_Sig_c.ff_inst/Q (SLICE)
Path End : MyCDC01/A_Sig1_c.ff_inst/DF (SLICE)
Source Clock : ClkB (R)
Destination Clock: ClkB (R)
Logic Level : 1
Delay Ratio : 49.6% (route), 50.4% (logic)
Clock Skew : 0.000 ns
Setup Constraint : 9.803 ns
Common Path Skew : 0.000 ns
Path Slack : 9.233 ns (Passed)
Source Clock Path
{
"path_begin":
{
"type":"port",
"log_name":"ClkB",
"phy_name":"ClkB"
},
"path_end":
{
"type":"pin",
"log_name":"MyCDC01/A_Sig_c.ff_inst/CLK",
"phy_name":"MyCDC01.A_Sig_c.SLICE_3/CLK"
},
"path_sections":[
{
"type":"net_delay",
"net":
{
"log_name":"ClkB",
"phy_name":"ClkB"
},
"arrive":0.000,
"delay":0.000
},
{
"type":"site_delay",
"pin0":
{
"log_name":"ClkB_pad.bb_inst/B",
"phy_name":"ClkB_pad.bb_inst/IOPAD"
},
"pin1":
{
"log_name":"ClkB_pad.bb_inst/O",
"phy_name":"ClkB_pad.bb_inst/PADDI"
},
"arrive":1.238,
"delay":1.238
},
{
"type":"net_delay",
"net":
{
"log_name":"MyCDC01/ClkB_c",
"phy_name":"ClkB_c"
},
"arrive":1.859,
"delay":0.621
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":1.859,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- -------------- ---------------- --------- --------------------- ------
ClkB top CLOCK LATENCY 0.000 0.000 1
ClkB NET DELAY 0.000 0.000 1
ClkB_pad.bb_inst/B->ClkB_pad.bb_inst/O SEIO33_CORE PADI_DEL 1.238 1.238 4
MyCDC01/ClkB_c NET DELAY 0.621 1.859 4
MyCDC01/A_Sig_c.ff_inst/CLK CLOCK PIN 0.000 1.859 1
Data Path
{
"path_begin":
{
"type":"pin",
"log_name":"MyCDC01/A_Sig_c.ff_inst/Q",
"phy_name":"MyCDC01.A_Sig_c.SLICE_3/Q0"
},
"path_end":
{
"type":"pin",
"log_name":"MyCDC01/A_Sig1_c.ff_inst/DF",
"phy_name":"MyCDC01.A_Sig1_c.SLICE_2/M0"
},
"path_sections":[
{
"type":"site_delay",
"pin0":
{
"log_name":"MyCDC01/A_Sig_c.ff_inst/CLK",
"phy_name":"MyCDC01.A_Sig_c.SLICE_3/CLK"
},
"pin1":
{
"log_name":"MyCDC01/A_Sig_c.ff_inst/Q",
"phy_name":"MyCDC01.A_Sig_c.SLICE_3/Q0"
},
"arrive":2.164,
"delay":0.305
},
{
"type":"net_delay",
"net":
{
"log_name":"MyCDC01/A_Sig_adj_3",
"phy_name":"MyCDC01.A_Sig_adj_3"
},
"arrive":2.464,
"delay":0.300
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":2.464,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- -------------- ---------------- --------- --------------------- ------
MyCDC01/A_Sig_c.ff_inst/CLK->MyCDC01/A_Sig_c.ff_inst/Q
SLICE REG_DEL 0.305 2.164 1
MyCDC01/A_Sig_adj_3 NET DELAY 0.300 2.464 1
MyCDC01/A_Sig1_c.ff_inst/DF ENDPOINT 0.000 2.464 1
Destination Clock Path
{
"path_begin":
{
"type":"port",
"log_name":"ClkB",
"phy_name":"ClkB"
},
"path_end":
{
"type":"pin",
"log_name":"MyCDC01/A_Sig1_c.ff_inst/CLK",
"phy_name":"MyCDC01.A_Sig1_c.SLICE_2/CLK"
},
"path_sections":[
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":9.803,
"delay":0.000
},
{
"type":"net_delay",
"net":
{
"log_name":"ClkB",
"phy_name":"ClkB"
},
"arrive":9.803,
"delay":0.000
},
{
"type":"site_delay",
"pin0":
{
"log_name":"ClkB_pad.bb_inst/B",
"phy_name":"ClkB_pad.bb_inst/IOPAD"
},
"pin1":
{
"log_name":"ClkB_pad.bb_inst/O",
"phy_name":"ClkB_pad.bb_inst/PADDI"
},
"arrive":11.041,
"delay":1.238
},
{
"type":"net_delay",
"net":
{
"log_name":"MyCDC01/ClkB_c",
"phy_name":"ClkB_c"
},
"arrive":11.662,
"delay":0.621
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":11.662,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- -------------- ---------------- --------- --------------------- ------
CONSTRAINT 0.000 9.803 1
ClkB top CLOCK LATENCY 0.000 9.803 1
ClkB NET DELAY 0.000 9.803 1
ClkB_pad.bb_inst/B->ClkB_pad.bb_inst/O SEIO33_CORE PADI_DEL 1.238 11.041 4
MyCDC01/ClkB_c NET DELAY 0.621 11.662 4
MyCDC01/A_Sig1_c.ff_inst/CLK CLOCK PIN 0.000 11.662 1
Uncertainty -(0.000) 11.662
Common Path Skew 0.000 11.662
Setup time -(-0.035) 11.697
---------------------------------------- -------------- ---------------- --------- --------------------- ------
Required Time 11.697
Arrival Time -(2.464)
---------------------------------------- -------------- ---------------- --------- --------------------- ------
Path Slack (Passed) 9.233
++++ Path 3 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Path Begin : MyCDC02/A_Sig1.ff_inst/Q (SLICE)
Path End : out1_i0.ff_inst/DF (SLICE)
Source Clock : ClkA (R)
Destination Clock: ClkA (R)
Logic Level : 2
Delay Ratio : 36.7% (route), 63.3% (logic)
Clock Skew : 0.000 ns
Setup Constraint : 10.000 ns
Common Path Skew : 0.000 ns
Path Slack : 9.240 ns (Passed)
Source Clock Path
{
"path_begin":
{
"type":"port",
"log_name":"ClkA",
"phy_name":"ClkA"
},
"path_end":
{
"type":"pin",
"log_name":"MyCDC02/A_Sig1.ff_inst/CLK",
"phy_name":"MyCDC02.A_Sig1.SLICE_0/CLK"
},
"path_sections":[
{
"type":"net_delay",
"net":
{
"log_name":"ClkA",
"phy_name":"ClkA"
},
"arrive":0.000,
"delay":0.000
},
{
"type":"site_delay",
"pin0":
{
"log_name":"ClkA_pad.bb_inst/B",
"phy_name":"ClkA_pad.bb_inst/IOPAD"
},
"pin1":
{
"log_name":"ClkA_pad.bb_inst/O",
"phy_name":"ClkA_pad.bb_inst/PADDI"
},
"arrive":1.238,
"delay":1.238
},
{
"type":"net_delay",
"net":
{
"log_name":"MyCDC02/ClkA_c",
"phy_name":"ClkA_c"
},
"arrive":1.859,
"delay":0.621
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":1.859,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- -------------- ---------------- --------- --------------------- ------
ClkA top CLOCK LATENCY 0.000 0.000 1
ClkA NET DELAY 0.000 0.000 1
ClkA_pad.bb_inst/B->ClkA_pad.bb_inst/O SEIO33_CORE PADI_DEL 1.238 1.238 4
MyCDC02/ClkA_c NET DELAY 0.621 1.859 4
MyCDC02/A_Sig1.ff_inst/CLK CLOCK PIN 0.000 1.859 1
Data Path
{
"path_begin":
{
"type":"pin",
"log_name":"MyCDC02/A_Sig1.ff_inst/Q",
"phy_name":"MyCDC02.A_Sig1.SLICE_0/Q0"
},
"path_end":
{
"type":"pin",
"log_name":"out1_i0.ff_inst/DF",
"phy_name":"SLICE_6/DI0"
},
"path_sections":[
{
"type":"site_delay",
"pin0":
{
"log_name":"MyCDC02/A_Sig1.ff_inst/CLK",
"phy_name":"MyCDC02.A_Sig1.SLICE_0/CLK"
},
"pin1":
{
"log_name":"MyCDC02/A_Sig1.ff_inst/Q",
"phy_name":"MyCDC02.A_Sig1.SLICE_0/Q0"
},
"arrive":2.164,
"delay":0.305
},
{
"type":"net_delay",
"net":
{
"log_name":"MyCDC02/B_sig1",
"phy_name":"B_sig1"
},
"arrive":2.464,
"delay":0.300
},
{
"type":"site_delay",
"pin0":
{
"log_name":"i5_2_lut/B",
"phy_name":"SLICE_6/B0"
},
"pin1":
{
"log_name":"i5_2_lut/Z",
"phy_name":"SLICE_6/F0"
},
"arrive":2.677,
"delay":0.213
},
{
"type":"net_delay",
"net":
{
"log_name":"out1_c_N_1",
"phy_name":"out1_c_N_1"
},
"arrive":2.677,
"delay":0.000
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":2.677,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- -------------- ---------------- --------- --------------------- ------
MyCDC02/A_Sig1.ff_inst/CLK->MyCDC02/A_Sig1.ff_inst/Q
SLICE REG_DEL 0.305 2.164 1
MyCDC02/B_sig1 NET DELAY 0.300 2.464 1
i5_2_lut/B->i5_2_lut/Z SLICE CTOF_DEL 0.213 2.677 1
out1_c_N_1 NET DELAY 0.000 2.677 1
out1_i0.ff_inst/DF ENDPOINT 0.000 2.677 1
Destination Clock Path
{
"path_begin":
{
"type":"port",
"log_name":"ClkA",
"phy_name":"ClkA"
},
"path_end":
{
"type":"pin",
"log_name":"out1_i0.ff_inst/CLK",
"phy_name":"SLICE_6/CLK"
},
"path_sections":[
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":10.000,
"delay":0.000
},
{
"type":"net_delay",
"net":
{
"log_name":"ClkA",
"phy_name":"ClkA"
},
"arrive":10.000,
"delay":0.000
},
{
"type":"site_delay",
"pin0":
{
"log_name":"ClkA_pad.bb_inst/B",
"phy_name":"ClkA_pad.bb_inst/IOPAD"
},
"pin1":
{
"log_name":"ClkA_pad.bb_inst/O",
"phy_name":"ClkA_pad.bb_inst/PADDI"
},
"arrive":11.238,
"delay":1.238
},
{
"type":"net_delay",
"net":
{
"log_name":"MyCDC02/ClkA_c",
"phy_name":"ClkA_c"
},
"arrive":11.859,
"delay":0.621
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":11.859,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- -------------- ---------------- --------- --------------------- ------
CONSTRAINT 0.000 10.000 1
ClkA top CLOCK LATENCY 0.000 10.000 1
ClkA NET DELAY 0.000 10.000 1
ClkA_pad.bb_inst/B->ClkA_pad.bb_inst/O SEIO33_CORE PADI_DEL 1.238 11.238 4
MyCDC02/ClkA_c NET DELAY 0.621 11.859 4
out1_i0.ff_inst/CLK CLOCK PIN 0.000 11.859 1
Uncertainty -(0.000) 11.859
Common Path Skew 0.000 11.859
Setup time -(-0.058) 11.917
---------------------------------------- -------------- ---------------- --------- --------------------- ------
Required Time 11.917
Arrival Time -(2.677)
---------------------------------------- -------------- ---------------- --------- --------------------- ------
Path Slack (Passed) 9.240
++++ Path 4 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Path Begin : MyCDC02/A_Sig_c.ff_inst/Q (SLICE)
Path End : MyCDC02/A_Sig1.ff_inst/DF (SLICE)
Source Clock : ClkA (R)
Destination Clock: ClkA (R)
Logic Level : 1
Delay Ratio : 49.6% (route), 50.4% (logic)
Clock Skew : 0.000 ns
Setup Constraint : 10.000 ns
Common Path Skew : 0.000 ns
Path Slack : 9.430 ns (Passed)
Source Clock Path
{
"path_begin":
{
"type":"port",
"log_name":"ClkA",
"phy_name":"ClkA"
},
"path_end":
{
"type":"pin",
"log_name":"MyCDC02/A_Sig_c.ff_inst/CLK",
"phy_name":"MyCDC02.A_Sig_c.SLICE_1/CLK"
},
"path_sections":[
{
"type":"net_delay",
"net":
{
"log_name":"ClkA",
"phy_name":"ClkA"
},
"arrive":0.000,
"delay":0.000
},
{
"type":"site_delay",
"pin0":
{
"log_name":"ClkA_pad.bb_inst/B",
"phy_name":"ClkA_pad.bb_inst/IOPAD"
},
"pin1":
{
"log_name":"ClkA_pad.bb_inst/O",
"phy_name":"ClkA_pad.bb_inst/PADDI"
},
"arrive":1.238,
"delay":1.238
},
{
"type":"net_delay",
"net":
{
"log_name":"MyCDC02/ClkA_c",
"phy_name":"ClkA_c"
},
"arrive":1.859,
"delay":0.621
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":1.859,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- -------------- ---------------- --------- --------------------- ------
ClkA top CLOCK LATENCY 0.000 0.000 1
ClkA NET DELAY 0.000 0.000 1
ClkA_pad.bb_inst/B->ClkA_pad.bb_inst/O SEIO33_CORE PADI_DEL 1.238 1.238 4
MyCDC02/ClkA_c NET DELAY 0.621 1.859 4
MyCDC02/A_Sig_c.ff_inst/CLK CLOCK PIN 0.000 1.859 1
Data Path
{
"path_begin":
{
"type":"pin",
"log_name":"MyCDC02/A_Sig_c.ff_inst/Q",
"phy_name":"MyCDC02.A_Sig_c.SLICE_1/Q0"
},
"path_end":
{
"type":"pin",
"log_name":"MyCDC02/A_Sig1.ff_inst/DF",
"phy_name":"MyCDC02.A_Sig1.SLICE_0/M0"
},
"path_sections":[
{
"type":"site_delay",
"pin0":
{
"log_name":"MyCDC02/A_Sig_c.ff_inst/CLK",
"phy_name":"MyCDC02.A_Sig_c.SLICE_1/CLK"
},
"pin1":
{
"log_name":"MyCDC02/A_Sig_c.ff_inst/Q",
"phy_name":"MyCDC02.A_Sig_c.SLICE_1/Q0"
},
"arrive":2.164,
"delay":0.305
},
{
"type":"net_delay",
"net":
{
"log_name":"MyCDC02/A_Sig",
"phy_name":"MyCDC02.A_Sig"
},
"arrive":2.464,
"delay":0.300
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":2.464,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- -------------- ---------------- --------- --------------------- ------
MyCDC02/A_Sig_c.ff_inst/CLK->MyCDC02/A_Sig_c.ff_inst/Q
SLICE REG_DEL 0.305 2.164 1
MyCDC02/A_Sig NET DELAY 0.300 2.464 1
MyCDC02/A_Sig1.ff_inst/DF ENDPOINT 0.000 2.464 1
Destination Clock Path
{
"path_begin":
{
"type":"port",
"log_name":"ClkA",
"phy_name":"ClkA"
},
"path_end":
{
"type":"pin",
"log_name":"MyCDC02/A_Sig1.ff_inst/CLK",
"phy_name":"MyCDC02.A_Sig1.SLICE_0/CLK"
},
"path_sections":[
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":10.000,
"delay":0.000
},
{
"type":"net_delay",
"net":
{
"log_name":"ClkA",
"phy_name":"ClkA"
},
"arrive":10.000,
"delay":0.000
},
{
"type":"site_delay",
"pin0":
{
"log_name":"ClkA_pad.bb_inst/B",
"phy_name":"ClkA_pad.bb_inst/IOPAD"
},
"pin1":
{
"log_name":"ClkA_pad.bb_inst/O",
"phy_name":"ClkA_pad.bb_inst/PADDI"
},
"arrive":11.238,
"delay":1.238
},
{
"type":"net_delay",
"net":
{
"log_name":"MyCDC02/ClkA_c",
"phy_name":"ClkA_c"
},
"arrive":11.859,
"delay":0.621
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":11.859,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- -------------- ---------------- --------- --------------------- ------
CONSTRAINT 0.000 10.000 1
ClkA top CLOCK LATENCY 0.000 10.000 1
ClkA NET DELAY 0.000 10.000 1
ClkA_pad.bb_inst/B->ClkA_pad.bb_inst/O SEIO33_CORE PADI_DEL 1.238 11.238 4
MyCDC02/ClkA_c NET DELAY 0.621 11.859 4
MyCDC02/A_Sig1.ff_inst/CLK CLOCK PIN 0.000 11.859 1
Uncertainty -(0.000) 11.859
Common Path Skew 0.000 11.859
Setup time -(-0.035) 11.894
---------------------------------------- -------------- ---------------- --------- --------------------- ------
Required Time 11.894
Arrival Time -(2.464)
---------------------------------------- -------------- ---------------- --------- --------------------- ------
Path Slack (Passed) 9.430
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
End of Detailed Report for timing paths
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
##########################################################
4 Hold at Speed Grade m Corner at 0 Degrees
4.1 Endpoint slacks
-------------------------------------------------------
Listing 4 End Points | Slack
-------------------------------------------------------
MyCDC02/A_Sig1.ff_inst/DF | 0.376 ns
MyCDC01/A_Sig1_c.ff_inst/DF | 0.376 ns
out1_i0.ff_inst/DF | 0.475 ns
out2_i1.ff_inst/DF | 0.475 ns
-------------------------------------------------------
|
Hold # of endpoints with negative slack: | 0
|
-------------------------------------------------------
4.2 Detailed Report
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
Detail report of critical paths
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Detailed Report for timing paths
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++++Path 1 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Path Begin : MyCDC02/A_Sig_c.ff_inst/Q (SLICE)
Path End : MyCDC02/A_Sig1.ff_inst/DF (SLICE)
Source Clock : ClkA (R)
Destination Clock: ClkA (R)
Logic Level : 1
Delay Ratio : 63.4% (route), 36.6% (logic)
Clock Skew : 0.000 ns
Hold Constraint : 0.000 ns
Common Path Skew : 0.000 ns
Path Slack : 0.376 ns (Passed)
Source Clock Path
{
"path_begin":
{
"type":"port",
"log_name":"ClkA",
"phy_name":"ClkA"
},
"path_end":
{
"type":"pin",
"log_name":"MyCDC02/A_Sig_c.ff_inst/CLK",
"phy_name":"MyCDC02.A_Sig_c.SLICE_1/CLK"
},
"path_sections":[
{
"type":"net_delay",
"net":
{
"log_name":"ClkA",
"phy_name":"ClkA"
},
"arrive":0.000,
"delay":0.000
},
{
"type":"site_delay",
"pin0":
{
"log_name":"ClkA_pad.bb_inst/B",
"phy_name":"ClkA_pad.bb_inst/IOPAD"
},
"pin1":
{
"log_name":"ClkA_pad.bb_inst/O",
"phy_name":"ClkA_pad.bb_inst/PADDI"
},
"arrive":1.000,
"delay":1.000
},
{
"type":"net_delay",
"net":
{
"log_name":"MyCDC02/ClkA_c",
"phy_name":"ClkA_c"
},
"arrive":1.621,
"delay":0.621
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":1.621,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- -------------- ---------------- ----- --------------------- ------
ClkA top CLOCK LATENCY 0.000 0.000 1
ClkA NET DELAY 0.000 0.000 1
ClkA_pad.bb_inst/B->ClkA_pad.bb_inst/O SEIO33_CORE PADI_DEL 1.000 1.000 4
MyCDC02/ClkA_c NET DELAY 0.621 1.621 4
MyCDC02/A_Sig_c.ff_inst/CLK CLOCK PIN 0.000 1.621 1
Data Path
{
"path_begin":
{
"type":"pin",
"log_name":"MyCDC02/A_Sig_c.ff_inst/Q",
"phy_name":"MyCDC02.A_Sig_c.SLICE_1/Q0"
},
"path_end":
{
"type":"pin",
"log_name":"MyCDC02/A_Sig1.ff_inst/DF",
"phy_name":"MyCDC02.A_Sig1.SLICE_0/M0"
},
"path_sections":[
{
"type":"site_delay",
"pin0":
{
"log_name":"MyCDC02/A_Sig_c.ff_inst/CLK",
"phy_name":"MyCDC02.A_Sig_c.SLICE_1/CLK"
},
"pin1":
{
"log_name":"MyCDC02/A_Sig_c.ff_inst/Q",
"phy_name":"MyCDC02.A_Sig_c.SLICE_1/Q0"
},
"arrive":1.794,
"delay":0.173
},
{
"type":"net_delay",
"net":
{
"log_name":"MyCDC02/A_Sig",
"phy_name":"MyCDC02.A_Sig"
},
"arrive":2.094,
"delay":0.300
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":2.094,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- -------------- ---------------- ----- --------------------- ------
MyCDC02/A_Sig_c.ff_inst/CLK->MyCDC02/A_Sig_c.ff_inst/Q
SLICE REG_DEL 0.173 1.794 1
MyCDC02/A_Sig NET DELAY 0.300 2.094 1
MyCDC02/A_Sig1.ff_inst/DF ENDPOINT 0.000 2.094 1
Destination Clock Path
{
"path_begin":
{
"type":"port",
"log_name":"ClkA",
"phy_name":"ClkA"
},
"path_end":
{
"type":"pin",
"log_name":"MyCDC02/A_Sig1.ff_inst/CLK",
"phy_name":"MyCDC02.A_Sig1.SLICE_0/CLK"
},
"path_sections":[
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":0.000,
"delay":0.000
},
{
"type":"net_delay",
"net":
{
"log_name":"ClkA",
"phy_name":"ClkA"
},
"arrive":0.000,
"delay":0.000
},
{
"type":"site_delay",
"pin0":
{
"log_name":"ClkA_pad.bb_inst/B",
"phy_name":"ClkA_pad.bb_inst/IOPAD"
},
"pin1":
{
"log_name":"ClkA_pad.bb_inst/O",
"phy_name":"ClkA_pad.bb_inst/PADDI"
},
"arrive":1.000,
"delay":1.000
},
{
"type":"net_delay",
"net":
{
"log_name":"MyCDC02/ClkA_c",
"phy_name":"ClkA_c"
},
"arrive":1.621,
"delay":0.621
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":1.621,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- -------------- ---------------- ----- --------------------- ------
CONSTRAINT 0.000 0.000 1
ClkA top CLOCK LATENCY 0.000 0.000 1
ClkA NET DELAY 0.000 0.000 1
ClkA_pad.bb_inst/B->ClkA_pad.bb_inst/O SEIO33_CORE PADI_DEL 1.000 1.000 4
MyCDC02/ClkA_c NET DELAY 0.621 1.621 4
MyCDC02/A_Sig1.ff_inst/CLK CLOCK PIN 0.000 1.621 1
Uncertainty 0.000 1.621
Common Path Skew 0.000 1.621
Hold time 0.097 1.718
---------------------------------------- -------------- ---------------- ----- --------------------- ------
Required Time -1.718
Arrival Time 2.094
---------------------------------------- -------------- ---------------- ----- --------------------- ------
Path Slack (Passed) 0.376
++++ Path 2 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Path Begin : MyCDC01/A_Sig_c.ff_inst/Q (SLICE)
Path End : MyCDC01/A_Sig1_c.ff_inst/DF (SLICE)
Source Clock : ClkB (R)
Destination Clock: ClkB (R)
Logic Level : 1
Delay Ratio : 63.4% (route), 36.6% (logic)
Clock Skew : 0.000 ns
Hold Constraint : 0.000 ns
Common Path Skew : 0.000 ns
Path Slack : 0.376 ns (Passed)
Source Clock Path
{
"path_begin":
{
"type":"port",
"log_name":"ClkB",
"phy_name":"ClkB"
},
"path_end":
{
"type":"pin",
"log_name":"MyCDC01/A_Sig_c.ff_inst/CLK",
"phy_name":"MyCDC01.A_Sig_c.SLICE_3/CLK"
},
"path_sections":[
{
"type":"net_delay",
"net":
{
"log_name":"ClkB",
"phy_name":"ClkB"
},
"arrive":0.000,
"delay":0.000
},
{
"type":"site_delay",
"pin0":
{
"log_name":"ClkB_pad.bb_inst/B",
"phy_name":"ClkB_pad.bb_inst/IOPAD"
},
"pin1":
{
"log_name":"ClkB_pad.bb_inst/O",
"phy_name":"ClkB_pad.bb_inst/PADDI"
},
"arrive":1.000,
"delay":1.000
},
{
"type":"net_delay",
"net":
{
"log_name":"MyCDC01/ClkB_c",
"phy_name":"ClkB_c"
},
"arrive":1.621,
"delay":0.621
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":1.621,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- -------------- ---------------- ----- --------------------- ------
ClkB top CLOCK LATENCY 0.000 0.000 1
ClkB NET DELAY 0.000 0.000 1
ClkB_pad.bb_inst/B->ClkB_pad.bb_inst/O SEIO33_CORE PADI_DEL 1.000 1.000 4
MyCDC01/ClkB_c NET DELAY 0.621 1.621 4
MyCDC01/A_Sig_c.ff_inst/CLK CLOCK PIN 0.000 1.621 1
Data Path
{
"path_begin":
{
"type":"pin",
"log_name":"MyCDC01/A_Sig_c.ff_inst/Q",
"phy_name":"MyCDC01.A_Sig_c.SLICE_3/Q0"
},
"path_end":
{
"type":"pin",
"log_name":"MyCDC01/A_Sig1_c.ff_inst/DF",
"phy_name":"MyCDC01.A_Sig1_c.SLICE_2/M0"
},
"path_sections":[
{
"type":"site_delay",
"pin0":
{
"log_name":"MyCDC01/A_Sig_c.ff_inst/CLK",
"phy_name":"MyCDC01.A_Sig_c.SLICE_3/CLK"
},
"pin1":
{
"log_name":"MyCDC01/A_Sig_c.ff_inst/Q",
"phy_name":"MyCDC01.A_Sig_c.SLICE_3/Q0"
},
"arrive":1.794,
"delay":0.173
},
{
"type":"net_delay",
"net":
{
"log_name":"MyCDC01/A_Sig_adj_3",
"phy_name":"MyCDC01.A_Sig_adj_3"
},
"arrive":2.094,
"delay":0.300
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":2.094,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- -------------- ---------------- ----- --------------------- ------
MyCDC01/A_Sig_c.ff_inst/CLK->MyCDC01/A_Sig_c.ff_inst/Q
SLICE REG_DEL 0.173 1.794 1
MyCDC01/A_Sig_adj_3 NET DELAY 0.300 2.094 1
MyCDC01/A_Sig1_c.ff_inst/DF ENDPOINT 0.000 2.094 1
Destination Clock Path
{
"path_begin":
{
"type":"port",
"log_name":"ClkB",
"phy_name":"ClkB"
},
"path_end":
{
"type":"pin",
"log_name":"MyCDC01/A_Sig1_c.ff_inst/CLK",
"phy_name":"MyCDC01.A_Sig1_c.SLICE_2/CLK"
},
"path_sections":[
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":0.000,
"delay":0.000
},
{
"type":"net_delay",
"net":
{
"log_name":"ClkB",
"phy_name":"ClkB"
},
"arrive":0.000,
"delay":0.000
},
{
"type":"site_delay",
"pin0":
{
"log_name":"ClkB_pad.bb_inst/B",
"phy_name":"ClkB_pad.bb_inst/IOPAD"
},
"pin1":
{
"log_name":"ClkB_pad.bb_inst/O",
"phy_name":"ClkB_pad.bb_inst/PADDI"
},
"arrive":1.000,
"delay":1.000
},
{
"type":"net_delay",
"net":
{
"log_name":"MyCDC01/ClkB_c",
"phy_name":"ClkB_c"
},
"arrive":1.621,
"delay":0.621
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":1.621,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- -------------- ---------------- ----- --------------------- ------
CONSTRAINT 0.000 0.000 1
ClkB top CLOCK LATENCY 0.000 0.000 1
ClkB NET DELAY 0.000 0.000 1
ClkB_pad.bb_inst/B->ClkB_pad.bb_inst/O SEIO33_CORE PADI_DEL 1.000 1.000 4
MyCDC01/ClkB_c NET DELAY 0.621 1.621 4
MyCDC01/A_Sig1_c.ff_inst/CLK CLOCK PIN 0.000 1.621 1
Uncertainty 0.000 1.621
Common Path Skew 0.000 1.621
Hold time 0.097 1.718
---------------------------------------- -------------- ---------------- ----- --------------------- ------
Required Time -1.718
Arrival Time 2.094
---------------------------------------- -------------- ---------------- ----- --------------------- ------
Path Slack (Passed) 0.376
++++ Path 3 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Path Begin : MyCDC02/A_Sig1.ff_inst/Q (SLICE)
Path End : out1_i0.ff_inst/DF (SLICE)
Source Clock : ClkA (R)
Destination Clock: ClkA (R)
Logic Level : 2
Delay Ratio : 50.9% (route), 49.1% (logic)
Clock Skew : 0.000 ns
Hold Constraint : 0.000 ns
Common Path Skew : 0.000 ns
Path Slack : 0.475 ns (Passed)
Source Clock Path
{
"path_begin":
{
"type":"port",
"log_name":"ClkA",
"phy_name":"ClkA"
},
"path_end":
{
"type":"pin",
"log_name":"MyCDC02/A_Sig1.ff_inst/CLK",
"phy_name":"MyCDC02.A_Sig1.SLICE_0/CLK"
},
"path_sections":[
{
"type":"net_delay",
"net":
{
"log_name":"ClkA",
"phy_name":"ClkA"
},
"arrive":0.000,
"delay":0.000
},
{
"type":"site_delay",
"pin0":
{
"log_name":"ClkA_pad.bb_inst/B",
"phy_name":"ClkA_pad.bb_inst/IOPAD"
},
"pin1":
{
"log_name":"ClkA_pad.bb_inst/O",
"phy_name":"ClkA_pad.bb_inst/PADDI"
},
"arrive":1.000,
"delay":1.000
},
{
"type":"net_delay",
"net":
{
"log_name":"MyCDC02/ClkA_c",
"phy_name":"ClkA_c"
},
"arrive":1.621,
"delay":0.621
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":1.621,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- -------------- ---------------- ----- --------------------- ------
ClkA top CLOCK LATENCY 0.000 0.000 1
ClkA NET DELAY 0.000 0.000 1
ClkA_pad.bb_inst/B->ClkA_pad.bb_inst/O SEIO33_CORE PADI_DEL 1.000 1.000 4
MyCDC02/ClkA_c NET DELAY 0.621 1.621 4
MyCDC02/A_Sig1.ff_inst/CLK CLOCK PIN 0.000 1.621 1
Data Path
{
"path_begin":
{
"type":"pin",
"log_name":"MyCDC02/A_Sig1.ff_inst/Q",
"phy_name":"MyCDC02.A_Sig1.SLICE_0/Q0"
},
"path_end":
{
"type":"pin",
"log_name":"out1_i0.ff_inst/DF",
"phy_name":"SLICE_6/DI0"
},
"path_sections":[
{
"type":"site_delay",
"pin0":
{
"log_name":"MyCDC02/A_Sig1.ff_inst/CLK",
"phy_name":"MyCDC02.A_Sig1.SLICE_0/CLK"
},
"pin1":
{
"log_name":"MyCDC02/A_Sig1.ff_inst/Q",
"phy_name":"MyCDC02.A_Sig1.SLICE_0/Q0"
},
"arrive":1.794,
"delay":0.173
},
{
"type":"net_delay",
"net":
{
"log_name":"MyCDC02/B_sig1",
"phy_name":"B_sig1"
},
"arrive":2.094,
"delay":0.300
},
{
"type":"site_delay",
"pin0":
{
"log_name":"i5_2_lut/B",
"phy_name":"SLICE_6/B0"
},
"pin1":
{
"log_name":"i5_2_lut/Z",
"phy_name":"SLICE_6/F0"
},
"arrive":2.210,
"delay":0.116
},
{
"type":"net_delay",
"net":
{
"log_name":"out1_c_N_1",
"phy_name":"out1_c_N_1"
},
"arrive":2.210,
"delay":0.000
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":2.210,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- -------------- ---------------- ----- --------------------- ------
MyCDC02/A_Sig1.ff_inst/CLK->MyCDC02/A_Sig1.ff_inst/Q
SLICE REG_DEL 0.173 1.794 1
MyCDC02/B_sig1 NET DELAY 0.300 2.094 1
i5_2_lut/B->i5_2_lut/Z SLICE CTOF_DEL 0.116 2.210 1
out1_c_N_1 NET DELAY 0.000 2.210 1
out1_i0.ff_inst/DF ENDPOINT 0.000 2.210 1
Destination Clock Path
{
"path_begin":
{
"type":"port",
"log_name":"ClkA",
"phy_name":"ClkA"
},
"path_end":
{
"type":"pin",
"log_name":"out1_i0.ff_inst/CLK",
"phy_name":"SLICE_6/CLK"
},
"path_sections":[
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":0.000,
"delay":0.000
},
{
"type":"net_delay",
"net":
{
"log_name":"ClkA",
"phy_name":"ClkA"
},
"arrive":0.000,
"delay":0.000
},
{
"type":"site_delay",
"pin0":
{
"log_name":"ClkA_pad.bb_inst/B",
"phy_name":"ClkA_pad.bb_inst/IOPAD"
},
"pin1":
{
"log_name":"ClkA_pad.bb_inst/O",
"phy_name":"ClkA_pad.bb_inst/PADDI"
},
"arrive":1.000,
"delay":1.000
},
{
"type":"net_delay",
"net":
{
"log_name":"MyCDC02/ClkA_c",
"phy_name":"ClkA_c"
},
"arrive":1.621,
"delay":0.621
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":1.621,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- -------------- ---------------- ----- --------------------- ------
CONSTRAINT 0.000 0.000 1
ClkA top CLOCK LATENCY 0.000 0.000 1
ClkA NET DELAY 0.000 0.000 1
ClkA_pad.bb_inst/B->ClkA_pad.bb_inst/O SEIO33_CORE PADI_DEL 1.000 1.000 4
MyCDC02/ClkA_c NET DELAY 0.621 1.621 4
out1_i0.ff_inst/CLK CLOCK PIN 0.000 1.621 1
Uncertainty 0.000 1.621
Common Path Skew 0.000 1.621
Hold time 0.114 1.735
---------------------------------------- -------------- ---------------- ----- --------------------- ------
Required Time -1.735
Arrival Time 2.210
---------------------------------------- -------------- ---------------- ----- --------------------- ------
Path Slack (Passed) 0.475
++++ Path 4 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Path Begin : MyCDC01/A_Sig1_c.ff_inst/Q (SLICE)
Path End : out2_i1.ff_inst/DF (SLICE)
Source Clock : ClkB (R)
Destination Clock: ClkB (R)
Logic Level : 2
Delay Ratio : 50.9% (route), 49.1% (logic)
Clock Skew : 0.000 ns
Hold Constraint : 0.000 ns
Common Path Skew : 0.000 ns
Path Slack : 0.475 ns (Passed)
Source Clock Path
{
"path_begin":
{
"type":"port",
"log_name":"ClkB",
"phy_name":"ClkB"
},
"path_end":
{
"type":"pin",
"log_name":"MyCDC01/A_Sig1_c.ff_inst/CLK",
"phy_name":"MyCDC01.A_Sig1_c.SLICE_2/CLK"
},
"path_sections":[
{
"type":"net_delay",
"net":
{
"log_name":"ClkB",
"phy_name":"ClkB"
},
"arrive":0.000,
"delay":0.000
},
{
"type":"site_delay",
"pin0":
{
"log_name":"ClkB_pad.bb_inst/B",
"phy_name":"ClkB_pad.bb_inst/IOPAD"
},
"pin1":
{
"log_name":"ClkB_pad.bb_inst/O",
"phy_name":"ClkB_pad.bb_inst/PADDI"
},
"arrive":1.000,
"delay":1.000
},
{
"type":"net_delay",
"net":
{
"log_name":"MyCDC01/ClkB_c",
"phy_name":"ClkB_c"
},
"arrive":1.621,
"delay":0.621
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":1.621,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- -------------- ---------------- ----- --------------------- ------
ClkB top CLOCK LATENCY 0.000 0.000 1
ClkB NET DELAY 0.000 0.000 1
ClkB_pad.bb_inst/B->ClkB_pad.bb_inst/O SEIO33_CORE PADI_DEL 1.000 1.000 4
MyCDC01/ClkB_c NET DELAY 0.621 1.621 4
MyCDC01/A_Sig1_c.ff_inst/CLK CLOCK PIN 0.000 1.621 1
Data Path
{
"path_begin":
{
"type":"pin",
"log_name":"MyCDC01/A_Sig1_c.ff_inst/Q",
"phy_name":"MyCDC01.A_Sig1_c.SLICE_2/Q0"
},
"path_end":
{
"type":"pin",
"log_name":"out2_i1.ff_inst/DF",
"phy_name":"SLICE_4/DI0"
},
"path_sections":[
{
"type":"site_delay",
"pin0":
{
"log_name":"MyCDC01/A_Sig1_c.ff_inst/CLK",
"phy_name":"MyCDC01.A_Sig1_c.SLICE_2/CLK"
},
"pin1":
{
"log_name":"MyCDC01/A_Sig1_c.ff_inst/Q",
"phy_name":"MyCDC01.A_Sig1_c.SLICE_2/Q0"
},
"arrive":1.794,
"delay":0.173
},
{
"type":"net_delay",
"net":
{
"log_name":"MyCDC01/A_Sig1",
"phy_name":"A_Sig1"
},
"arrive":2.094,
"delay":0.300
},
{
"type":"site_delay",
"pin0":
{
"log_name":"i9_2_lut/B",
"phy_name":"SLICE_4/B0"
},
"pin1":
{
"log_name":"i9_2_lut/Z",
"phy_name":"SLICE_4/F0"
},
"arrive":2.210,
"delay":0.116
},
{
"type":"net_delay",
"net":
{
"log_name":"out2_c_N_2",
"phy_name":"out2_c_N_2"
},
"arrive":2.210,
"delay":0.000
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":2.210,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- -------------- ---------------- ----- --------------------- ------
MyCDC01/A_Sig1_c.ff_inst/CLK->MyCDC01/A_Sig1_c.ff_inst/Q
SLICE REG_DEL 0.173 1.794 1
MyCDC01/A_Sig1 NET DELAY 0.300 2.094 1
i9_2_lut/B->i9_2_lut/Z SLICE CTOF_DEL 0.116 2.210 1
out2_c_N_2 NET DELAY 0.000 2.210 1
out2_i1.ff_inst/DF ENDPOINT 0.000 2.210 1
Destination Clock Path
{
"path_begin":
{
"type":"port",
"log_name":"ClkB",
"phy_name":"ClkB"
},
"path_end":
{
"type":"pin",
"log_name":"out2_i1.ff_inst/CLK",
"phy_name":"SLICE_4/CLK"
},
"path_sections":[
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":0.000,
"delay":0.000
},
{
"type":"net_delay",
"net":
{
"log_name":"ClkB",
"phy_name":"ClkB"
},
"arrive":0.000,
"delay":0.000
},
{
"type":"site_delay",
"pin0":
{
"log_name":"ClkB_pad.bb_inst/B",
"phy_name":"ClkB_pad.bb_inst/IOPAD"
},
"pin1":
{
"log_name":"ClkB_pad.bb_inst/O",
"phy_name":"ClkB_pad.bb_inst/PADDI"
},
"arrive":1.000,
"delay":1.000
},
{
"type":"net_delay",
"net":
{
"log_name":"MyCDC01/ClkB_c",
"phy_name":"ClkB_c"
},
"arrive":1.621,
"delay":0.621
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":1.621,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- -------------- ---------------- ----- --------------------- ------
CONSTRAINT 0.000 0.000 1
ClkB top CLOCK LATENCY 0.000 0.000 1
ClkB NET DELAY 0.000 0.000 1
ClkB_pad.bb_inst/B->ClkB_pad.bb_inst/O SEIO33_CORE PADI_DEL 1.000 1.000 4
MyCDC01/ClkB_c NET DELAY 0.621 1.621 4
out2_i1.ff_inst/CLK CLOCK PIN 0.000 1.621 1
Uncertainty 0.000 1.621
Common Path Skew 0.000 1.621
Hold time 0.114 1.735
---------------------------------------- -------------- ---------------- ----- --------------------- ------
Required Time -1.735
Arrival Time 2.210
---------------------------------------- -------------- ---------------- ----- --------------------- ------
Path Slack (Passed) 0.475
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
End of Detailed Report for timing paths
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
##########################################################