Copyright (c) 2002-2022 Lattice Semiconductor Corporation,  All rights reserved.

Tue Jun 25 17:24:10 2024

Command Line: par -w -n 1 -t 1 -s 1 -cores 1 -hsp m -exp parPathBased=OFF \
	LAB01_impl_1_map.udb LAB01_impl_1.udb 


Cost Table Summary
Level/       Number       Estimated       Timing       Estimated Worst    Timing          Run      Run
Cost [udb]   Unrouted     Worst Slack     Score        Slack(hold)        Score(hold)     Time     Status
----------   --------     -----------     ------       ---------------    -----------     ----     ------
5_1   *      0            -1.802          1802         -                  -               16       Completed
* : Design saved.

Total (real) run time for 1-seed: 17 secs 

par done!

Lattice Place and Route Report for Design "LAB01_impl_1_map.udb"
Tue Jun 25 17:24:10 2024


Best Par Run
PAR: Place And Route Radiant Software (64-bit) 2023.2.1.288.0.
Command Line: par -w -t 1 -cores 1 -hsp m -exp parPathBased=OFF \
	LAB01_impl_1_map.udb LAB01_impl_1_par.dir/5_1.udb 

Loading LAB01_impl_1_map.udb ...
Loading device for application GENERIC from file 'jd5d80.nph' in environment: C:/lscc/radiant/2023.2/ispfpga.
Package Status:                     Final          Version 16.
Performance Hardware Data Status:   Final          Version 3.9.



Design:  top
Family:  LFCPNX
Device:  LFCPNX-50
Package: CBG256
Performance Grade:   9_High-Performance_1.0V

Device SLICE utilization summary after final SLICE packing:
   SLICE              5/39936        <1% used

WARNING <70009502> - par: The preferred point for defining clocks is top level ports and driver pins. Pad delays will not be taken into consideration if clocks are defined on nets.
Number of Signals: 13
Number of Connections: 70

Device utilization summary:

   VHI                   1/1           100% used
   SEIO18A               1/132           1% used
                         1/84            1% bonded
   SEIO33                4/159           3% used
                         4/75            5% bonded
   PLL                   1/3            33% used
   SLICE                 5/21500        <1% used
     LUT                 2/43000        <1% used
     REG                 4/43000        <1% used


Pin Constraint Summary:
   0 out of 5 pins locked (0% locked).

User does not specify BBOX for group 'FFA', set to size (1x1) internally by PAR.


User does not specify BBOX for group 'FFB', set to size (1x1) internally by PAR.


User does not specify BBOX for group 'FFC', set to size (1x1) internally by PAR.


User does not specify BBOX for group 'FFD', set to size (1x1) internally by PAR.

.
Starting Placer Phase 0 (HIER). CPU time: 6 secs , REAL time: 7 secs 
........
Finished Placer Phase 0 (HIER). CPU time: 6 secs , REAL time: 7 secs 


User does not specify BBOX for group 'FFA', set to size (1x1) internally by PAR.


User does not specify BBOX for group 'FFB', set to size (1x1) internally by PAR.


User does not specify BBOX for group 'FFC', set to size (1x1) internally by PAR.


User does not specify BBOX for group 'FFD', set to size (1x1) internally by PAR.

.   
Starting Placer Phase 1. CPU time: 6 secs , REAL time: 7 secs 
..  ..
....................

Placer score = 47867.
Finished Placer Phase 1. CPU time: 10 secs , REAL time: 11 secs 

Starting Placer Phase 2.
.

Placer score =  47867
Finished Placer Phase 2.  CPU time: 10 secs , REAL time: 11 secs 



Clock Report

Global Clock Resources:
  CLK_PIN    : 0 out of 26 (0%)
  PLL        : 1 out of 3 (33%)
  PCS        : 0 out of 1 (0%)
  DCS        : 0 out of 2 (0%)
  DCC        : 0 out of 62 (0%)
  ECLKDIV    : 0 out of 12 (0%)
  PCLKDIV    : 0 out of 2 (0%)
  OSC        : 0 out of 1 (0%)

Global Clocks:
  PRIMARY "clk1" from CLKOP on comp "MyPLL.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst" on PLL site "PLL_LLC", clk load = 2, ce load = 0, sr load = 0
  PRIMARY "clk2" from CLKOS on comp "MyPLL.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst" on PLL site "PLL_LLC", clk load = 2, ce load = 0, sr load = 0

  PRIMARY  : 2 out of 16 (12%)

Edge Clocks:

  No edge clock selected.





I/O Usage Summary (final):
   4 out of 159 (2.5%) SEIO33 sites used.
   4 out of 75 (5.3%) bonded SEIO33 sites used.
   Number of SEIO33 components: 4; differential: 0
   Number of Vref pins used: 0
   1 out of 132 (0.8%) SEIO18 sites used.
   1 out of 84 (1.2%) bonded SEIO18 sites used.
   Number of SEIO18 components: 1; differential: 0
   0 out of 66 (0.0%) DIFFIO18 sites used.
   0 out of 42 (0.0%) bonded DIFFIO18 sites used.
   Number of DIFFIO18 components: 0; differential: 0

I/O Bank Usage Summary:
+----------+---------------+------------+------------+------------+
| I/O Bank | Usage         | Bank Vccio | Bank Vref1 | Bank Vref2 |
+----------+---------------+------------+------------+------------+
| 0        | 1 / 12 (  8%) | 3.3V       | -          | -          |
| 1        | 0 / 25 (  0%) | -          | -          | -          |
| 2        | 2 / 6 ( 33%)  | 3.3V       | -          | -          |
| 3        | 0 / 24 (  0%) | -          | -          | -          |
| 4        | 0 / 24 (  0%) | -          | -          | -          |
| 5        | 1 / 36 (  2%) | 1.8V       | -          | -          |
| 6        | 0 / 6 (  0%)  | -          | -          | -          |
| 7        | 1 / 26 (  3%) | 3.3V       | -          | -          |
+----------+---------------+------------+------------+------------+

Total Placer CPU time: 10 secs , REAL time: 11 secs 


Checksum -- place: 753670dce36e285012f3cb342f88086654c3080
Writing design to file LAB01_impl_1_par.dir/5_1.udb ...


Start NBR router at 17:24:21 06/25/24

*****************************************************************
Info: NBR allows conflicts(one node used by more than one signal)
      in the earlier iterations. In each iteration, it tries to  
      solve the conflicts while keeping the critical connections 
      routed as short as possible. The routing process is said to
      be completed when no conflicts exist and all connections   
      are routed.                                                
Note: NBR uses a different method to calculate timing slacks. The
      worst slack and total negative slack may not be the same as
      that in timing report. You should always run the timing    
      tool to verify your design.                                
*****************************************************************

Starting routing resource preassignment
Preassignment Summary:
--------------------------------------------------------------------------------
3 connections routed with dedicated routing resources
2 global clock signals routed
20 connections routed (of 70 total) (28.57%)
---------------------------------------------------------
Clock routing summary:
Primary clocks (8 used out of 64 available):
    Signal "clk1" (2, 18, 34, 50)
       Clock   loads: 2     out of     2 routed (100.00%)
    Signal "clk2" (5, 21, 37, 53)
       Clock   loads: 2     out of     2 routed (100.00%)
Other clocks:
    Signal "VCC_net"
       Clock   loads: 2     out of     2 routed (100.00%)
       Control loads: 2     out of     2 routed (100.00%)
       Data    loads: 9     out of     9 routed (100.00%)
    Signal "MyPLL.lscc_pll_inst.fbclk_w"
       Clock   loads: 1     out of     1 routed (100.00%)
    Signal "Clk_c"
       Clock   loads: 1     out of     1 routed (100.00%)
---------------------------------------------------------
--------------------------------------------------------------------------------
Completed routing resource preassignment
WARNING <70009502> - par: The preferred point for defining clocks is top level ports and driver pins. Pad delays will not be taken into consideration if clocks are defined on nets.

Start NBR section for initial routing at 17:24:25 06/25/24
Level 4, iteration 1
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Routing in Serial Mode ......
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
1(0.00%) conflict; 0(0.00%) untouched conn; 3853 (nbr) score; 
Estimated worst slack/total negative slack<setup>: -1.927ns/-3.854ns; real time: 4 secs 

Info: Initial congestion level at 75.00% usage is 0
Info: Initial congestion area  at 75.00% usage is 0 (0.00%)

Start NBR section for normal routing at 17:24:26 06/25/24
Level 4, iteration 1
1(0.00%) conflict; 0(0.00%) untouched conn; 3603 (nbr) score; 
Estimated worst slack/total negative slack<setup>: -1.802ns/-3.604ns; real time: 5 secs 
Level 4, iteration 2
0(0.00%) conflict; 0(0.00%) untouched conn; 3603 (nbr) score; 
Estimated worst slack/total negative slack<setup>: -1.802ns/-3.604ns; real time: 5 secs 

Start NBR section for post-routing at 17:24:26 06/25/24

End NBR router with 0 unrouted connection

Checksum -- route: 3479e7a15d1057588c850f314e0f17fb25bf2c13

Total CPU time 4 secs 
Total REAL time: 5 secs 
Completely routed.
End of route.  70 routed (100.00%); 0 unrouted.

Writing design to file LAB01_impl_1_par.dir/5_1.udb ...


All signals are completely routed.


PAR_SUMMARY::Run status = Completed
PAR_SUMMARY::Number of unrouted conns = 0
PAR_SUMMARY::Estimated worst slack<setup/<ns>> = -1.802
PAR_SUMMARY::Timing score<setup/<ns>> = 1.802
PAR_SUMMARY::Estimated worst slack<hold/<ns>> = <n/a>
PAR_SUMMARY::Timing score<hold/<ns>> = <n/a>
PAR_SUMMARY::Number of errors = 0

Note: user must run 'timing' for timing closure signoff.

Total CPU  Time: 16 secs 
Total REAL Time: 17 secs 
Peak Memory Usage: 765.45 MB


par done!

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