Timing Report
Lattice Timing Report - Setup and Hold, Version Radiant Software (64-bit) 2023.2.1.288.0
Thu Jun 6 10:02:03 2024
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2023 Lattice Semiconductor Corporation, All rights reserved.
Command line: timing -sethld -v 10 -u 10 -endpoints 10 -nperend 1 -sp 9_High-Performance_1.0V -hsp m -pwrprd -html -rpt lab07_impl_1.twr lab07_impl_1.udb -gui -msgset C:/Users/ssyahril/Downloads/FAE_F2F_Training_Labs_V2/FAE_F2F_Training_Labs_V2/LAB_07/promote.xml
-------------------------------------------
Design: top
Family: LFCPNX
Device: LFCPNX-50
Package: ASG256
Performance: 9_High-Performance_1.0V
Package Status: Final Version 16
Performance Hardware Data Status : Final Version 3.9
-------------------------------------------
=====================================================================
Table of Contents
=====================================================================
1 Timing Overview
1.1 SDC Constraints
1.2 Constraint Coverage
1.3 Overall Summary
1.4 Unconstrained Report
1.5 Combinational Loop
2 Setup at Speed Grade 9_High-Performance_1.0V Corner at 85 Degrees
2.1 Clock Summary
2.2 Endpoint slacks
2.3 Detailed Report
3 Setup at Speed Grade 9_High-Performance_1.0V Corner at 0 Degrees
3.1 Clock Summary
3.2 Endpoint slacks
3.3 Detailed Report
4 Hold at Speed Grade m Corner at 0 Degrees
4.1 Endpoint slacks
4.2 Detailed Report
=====================================================================
End of Table of Contents
=====================================================================
1 Timing Overview
1.1 SDC Constraints
create_clock -name {ClkA} -period 10 [get_ports ClkA]
create_clock -name {ClkB} -period 9.80392156862745 [get_ports ClkB]
set_false_path -from [get_clocks ClkA] -to [get_clocks ClkB]
set_false_path -from [get_clocks ClkB] -to [get_clocks ClkA]
set_false_path -through [get_nets {B_sig A_Sig}]
set_false_path -from [get_pins A_Sig_c.ff_inst/Q] -to [get_pins {MyCDC01/A_Sig1_c.ff_inst/CE MyCDC01/A_Sig_c.ff_inst/CE MyCDC01/A_Sig1_c.ff_inst/LSR MyCDC01/A_Sig_c.ff_inst/LSR MyCDC01/A_Sig_c.ff_inst/DF MyCDC02/A_Sig1.ff_inst/CE MyCDC02/A_Sig_c.ff_inst/CE MyCDC02/A_Sig1.ff_inst/LSR MyCDC02/A_Sig_c.ff_inst/LSR MyCDC02/A_Sig_c.ff_inst/DF}]
set_false_path -from [get_pins B_sig_c.ff_inst/Q] -to [get_pins {MyCDC01/A_Sig1_c.ff_inst/CE MyCDC01/A_Sig_c.ff_inst/CE MyCDC01/A_Sig1_c.ff_inst/LSR MyCDC01/A_Sig_c.ff_inst/LSR MyCDC01/A_Sig_c.ff_inst/DF MyCDC02/A_Sig1.ff_inst/CE MyCDC02/A_Sig_c.ff_inst/CE MyCDC02/A_Sig1.ff_inst/LSR MyCDC02/A_Sig_c.ff_inst/LSR MyCDC02/A_Sig_c.ff_inst/DF}]
1.2 Constraint Coverage
Constraint Coverage: 62.5%
1.3 Overall Summary
Setup at Speed Grade 9_High-Performance_1.0V Corner at 85 Degrees Timing Errors: 0 endpoints; Total Negative Slack: 0.000 ns
Setup at Speed Grade 9_High-Performance_1.0V Corner at 0 Degrees Timing Errors: 0 endpoints; Total Negative Slack: 0.000 ns
Hold at Speed Grade m Corner at 0 Degrees Timing Errors: 0 endpoints; Total Negative Slack: 0.000 ns
1.4 Unconstrained Report
1.4.1 Unconstrained Start/End Points
Clocked but unconstrained timing start points
-------------------------------------------------------------------
Listing 2 Start Points | Type
-------------------------------------------------------------------
out2_i1.ff_inst/Q | No required time
out1_i0.ff_inst/Q | No required time
-------------------------------------------------------------------
|
Number of unconstrained timing start po |
ints | 2
|
-------------------------------------------------------------------
Clocked but unconstrained timing end points
-------------------------------------------------------------------
Listing 2 End Points | Type
-------------------------------------------------------------------
A_Sig_c.ff_inst/DF | No arrival time
B_sig_c.ff_inst/DF | No arrival time
-------------------------------------------------------------------
|
Number of unconstrained timing end poin |
ts | 2
|
-------------------------------------------------------------------
1.4.2 Start/End Points Without Timing Constraints
I/O ports without constraint
----------------------------
Possible constraints to use on I/O ports are:
set_input_delay,
set_output_delay,
set_max_delay,
create_clock,
create_generated_clock,
...
-------------------------------------------------------------------
Listing 4 Start or End Points | Type
-------------------------------------------------------------------
A | input
B | input
out2 | output
out1 | output
-------------------------------------------------------------------
|
Number of I/O ports without constraint | 4
|
-------------------------------------------------------------------
Nets without clock definition
Define a clock on a top level port or a generated clock on a clock divider pin associated with this net(s).
--------------------------------------------------
There is no instance satisfying reporting criteria
1.5 Combinational Loop
None
2 Setup at Speed Grade 9_High-Performance_1.0V Corner at 85 Degrees
2.1 Clock Summary
2.1.1 Clock "ClkA"
create_clock -name {ClkA} -period 10 [get_ports ClkA]
Single Clock Domain
-------------------------------------------------------------------------------------------------------
Clock ClkA | | Period | Frequency
-------------------------------------------------------------------------------------------------------
From ClkA | Target | 10.000 ns | 100.000 MHz
| Actual (all paths) | 5.000 ns | 200.000 MHz
ClkA_pad.bb_inst/B (MPW) | (50% duty cycle) | 5.000 ns | 200.000 MHz
-------------------------------------------------------------------------------------------------------
Clock Domain Crossing
------------------------------------------------------------------------------------------------------
Clock ClkA | Worst Time Between Edges | Comment
------------------------------------------------------------------------------------------------------
From ClkB | ---- | False path
------------------------------------------------------------------------------------------------------
2.1.2 Clock "ClkB"
create_clock -name {ClkB} -period 9.80392156862745 [get_ports ClkB]
Single Clock Domain
-------------------------------------------------------------------------------------------------------
Clock ClkB | | Period | Frequency
-------------------------------------------------------------------------------------------------------
From ClkB | Target | 9.804 ns | 102.000 MHz
| Actual (all paths) | 5.000 ns | 200.000 MHz
ClkB_pad.bb_inst/B (MPW) | (50% duty cycle) | 5.000 ns | 200.000 MHz
-------------------------------------------------------------------------------------------------------
Clock Domain Crossing
------------------------------------------------------------------------------------------------------
Clock ClkB | Worst Time Between Edges | Comment
------------------------------------------------------------------------------------------------------
From ClkA | ---- | False path
------------------------------------------------------------------------------------------------------
2.2 Endpoint slacks
-------------------------------------------------------
Listing 4 End Points | Slack
-------------------------------------------------------
out2_i1.ff_inst/DF | 9.037 ns
MyCDC01/A_Sig1_c.ff_inst/DF | 9.149 ns
out1_i0.ff_inst/DF | 9.268 ns
MyCDC02/A_Sig1.ff_inst/DF | 9.403 ns
-------------------------------------------------------
|
Setup # of endpoints with negative slack:| 0
|
-------------------------------------------------------
2.3 Detailed Report
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
Detail report of critical paths
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Detailed Report for timing paths
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++++Path 1 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Path Begin : MyCDC01/A_Sig1_c.ff_inst/Q (SLICE_R43C157D)
Path End : out2_i1.ff_inst/DF (SLICE_R44C157D)
Source Clock : ClkB (R)
Destination Clock: ClkB (R)
Logic Level : 2
Delay Ratio : 35.2% (route), 64.8% (logic)
Clock Skew : -0.143 ns
Setup Constraint : 9.803 ns
Common Path Skew : 0.116 ns
Path Slack : 9.036 ns (Passed)
Source Clock Path
{
"path_begin":
{
"type":"port",
"log_name":"ClkB",
"phy_name":"ClkB"
},
"path_end":
{
"type":"pin",
"log_name":"MyCDC01/A_Sig1_c.ff_inst/CLK",
"phy_name":"MyCDC01.A_Sig1_c.SLICE_2/CLK"
},
"path_sections":[
{
"type":"net_delay",
"net":
{
"log_name":"ClkB",
"phy_name":"ClkB"
},
"arrive":0.000,
"delay":0.000
},
{
"type":"site_delay",
"pin0":
{
"log_name":"ClkB_pad.bb_inst/B",
"phy_name":"ClkB_pad.bb_inst/IOPAD"
},
"pin1":
{
"log_name":"ClkB_pad.bb_inst/O",
"phy_name":"ClkB_pad.bb_inst/PADDI"
},
"arrive":1.366,
"delay":1.366
},
{
"type":"net_delay",
"net":
{
"log_name":"MyCDC01/ClkB_c",
"phy_name":"ClkB_c"
},
"arrive":3.807,
"delay":2.441
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":3.807,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- --------------- ---------------- --------- --------------------- ------
ClkB top CLOCK LATENCY 0.000 0.000 1
ClkB NET DELAY 0.000 0.000 1
ClkB_pad.bb_inst/B->ClkB_pad.bb_inst/O SEIO33_CORE_J11 PADI_DEL 1.366 1.366 4
MyCDC01/ClkB_c NET DELAY 2.441 3.807 4
MyCDC01/A_Sig1_c.ff_inst/CLK CLOCK PIN 0.000 3.807 1
Data Path
{
"path_begin":
{
"type":"pin",
"log_name":"MyCDC01/A_Sig1_c.ff_inst/Q",
"phy_name":"MyCDC01.A_Sig1_c.SLICE_2/Q0"
},
"path_end":
{
"type":"pin",
"log_name":"out2_i1.ff_inst/DF",
"phy_name":"SLICE_4/DI0"
},
"path_sections":[
{
"type":"site_delay",
"pin0":
{
"log_name":"MyCDC01/A_Sig1_c.ff_inst/CLK",
"phy_name":"MyCDC01.A_Sig1_c.SLICE_2/CLK"
},
"pin1":
{
"log_name":"MyCDC01/A_Sig1_c.ff_inst/Q",
"phy_name":"MyCDC01.A_Sig1_c.SLICE_2/Q0"
},
"arrive":4.111,
"delay":0.304
},
{
"type":"net_delay",
"net":
{
"log_name":"MyCDC01/A_Sig1",
"phy_name":"A_Sig1"
},
"arrive":4.392,
"delay":0.281
},
{
"type":"site_delay",
"pin0":
{
"log_name":"i9_2_lut/B",
"phy_name":"SLICE_4/A0"
},
"pin1":
{
"log_name":"i9_2_lut/Z",
"phy_name":"SLICE_4/F0"
},
"arrive":4.605,
"delay":0.213
},
{
"type":"net_delay",
"net":
{
"log_name":"out2_c_N_2",
"phy_name":"out2_c_N_2"
},
"arrive":4.605,
"delay":0.000
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":4.605,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- --------------- ---------------- --------- --------------------- ------
MyCDC01/A_Sig1_c.ff_inst/CLK->MyCDC01/A_Sig1_c.ff_inst/Q
SLICE_R43C157D REG_DEL 0.304 4.111 1
MyCDC01/A_Sig1 NET DELAY 0.281 4.392 1
i9_2_lut/B->i9_2_lut/Z SLICE_R44C157D CTOF_DEL 0.213 4.605 1
out2_c_N_2 NET DELAY 0.000 4.605 1
out2_i1.ff_inst/DF ENDPOINT 0.000 4.605 1
Destination Clock Path
{
"path_begin":
{
"type":"port",
"log_name":"ClkB",
"phy_name":"ClkB"
},
"path_end":
{
"type":"pin",
"log_name":"out2_i1.ff_inst/CLK",
"phy_name":"SLICE_4/CLK"
},
"path_sections":[
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":9.803,
"delay":0.000
},
{
"type":"net_delay",
"net":
{
"log_name":"ClkB",
"phy_name":"ClkB"
},
"arrive":9.803,
"delay":0.000
},
{
"type":"site_delay",
"pin0":
{
"log_name":"ClkB_pad.bb_inst/B",
"phy_name":"ClkB_pad.bb_inst/IOPAD"
},
"pin1":
{
"log_name":"ClkB_pad.bb_inst/O",
"phy_name":"ClkB_pad.bb_inst/PADDI"
},
"arrive":11.169,
"delay":1.366
},
{
"type":"net_delay",
"net":
{
"log_name":"MyCDC01/ClkB_c",
"phy_name":"ClkB_c"
},
"arrive":13.467,
"delay":2.298
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":13.467,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- --------------- ---------------- --------- --------------------- ------
CONSTRAINT 0.000 9.803 1
ClkB top CLOCK LATENCY 0.000 9.803 1
ClkB NET DELAY 0.000 9.803 1
ClkB_pad.bb_inst/B->ClkB_pad.bb_inst/O SEIO33_CORE_J11 PADI_DEL 1.366 11.169 4
MyCDC01/ClkB_c NET DELAY 2.298 13.467 4
out2_i1.ff_inst/CLK CLOCK PIN 0.000 13.467 1
Uncertainty -(0.000) 13.467
Common Path Skew 0.116 13.583
Setup time -(-0.058) 13.641
---------------------------------------- --------------- ---------------- --------- --------------------- ------
Required Time 13.641
Arrival Time -(4.605)
---------------------------------------- --------------- ---------------- --------- --------------------- ------
Path Slack (Passed) 9.036
++++ Path 2 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Path Begin : MyCDC01/A_Sig_c.ff_inst/Q (SLICE_R42C157B)
Path End : MyCDC01/A_Sig1_c.ff_inst/DF (SLICE_R43C157D)
Source Clock : ClkB (R)
Destination Clock: ClkB (R)
Logic Level : 1
Delay Ratio : 54.1% (route), 45.9% (logic)
Clock Skew : -0.143 ns
Setup Constraint : 9.803 ns
Common Path Skew : 0.116 ns
Path Slack : 9.148 ns (Passed)
Source Clock Path
{
"path_begin":
{
"type":"port",
"log_name":"ClkB",
"phy_name":"ClkB"
},
"path_end":
{
"type":"pin",
"log_name":"MyCDC01/A_Sig_c.ff_inst/CLK",
"phy_name":"MyCDC01.A_Sig_c.SLICE_3/CLK"
},
"path_sections":[
{
"type":"net_delay",
"net":
{
"log_name":"ClkB",
"phy_name":"ClkB"
},
"arrive":0.000,
"delay":0.000
},
{
"type":"site_delay",
"pin0":
{
"log_name":"ClkB_pad.bb_inst/B",
"phy_name":"ClkB_pad.bb_inst/IOPAD"
},
"pin1":
{
"log_name":"ClkB_pad.bb_inst/O",
"phy_name":"ClkB_pad.bb_inst/PADDI"
},
"arrive":1.366,
"delay":1.366
},
{
"type":"net_delay",
"net":
{
"log_name":"MyCDC01/ClkB_c",
"phy_name":"ClkB_c"
},
"arrive":3.807,
"delay":2.441
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":3.807,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- --------------- ---------------- --------- --------------------- ------
ClkB top CLOCK LATENCY 0.000 0.000 1
ClkB NET DELAY 0.000 0.000 1
ClkB_pad.bb_inst/B->ClkB_pad.bb_inst/O SEIO33_CORE_J11 PADI_DEL 1.366 1.366 4
MyCDC01/ClkB_c NET DELAY 2.441 3.807 4
MyCDC01/A_Sig_c.ff_inst/CLK CLOCK PIN 0.000 3.807 1
Data Path
{
"path_begin":
{
"type":"pin",
"log_name":"MyCDC01/A_Sig_c.ff_inst/Q",
"phy_name":"MyCDC01.A_Sig_c.SLICE_3/Q0"
},
"path_end":
{
"type":"pin",
"log_name":"MyCDC01/A_Sig1_c.ff_inst/DF",
"phy_name":"MyCDC01.A_Sig1_c.SLICE_2/M0"
},
"path_sections":[
{
"type":"site_delay",
"pin0":
{
"log_name":"MyCDC01/A_Sig_c.ff_inst/CLK",
"phy_name":"MyCDC01.A_Sig_c.SLICE_3/CLK"
},
"pin1":
{
"log_name":"MyCDC01/A_Sig_c.ff_inst/Q",
"phy_name":"MyCDC01.A_Sig_c.SLICE_3/Q0"
},
"arrive":4.111,
"delay":0.304
},
{
"type":"net_delay",
"net":
{
"log_name":"MyCDC01/A_Sig_adj_3",
"phy_name":"MyCDC01.A_Sig_adj_3"
},
"arrive":4.470,
"delay":0.359
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":4.470,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- --------------- ---------------- --------- --------------------- ------
MyCDC01/A_Sig_c.ff_inst/CLK->MyCDC01/A_Sig_c.ff_inst/Q
SLICE_R42C157B REG_DEL 0.304 4.111 1
MyCDC01/A_Sig_adj_3 NET DELAY 0.359 4.470 1
MyCDC01/A_Sig1_c.ff_inst/DF ENDPOINT 0.000 4.470 1
Destination Clock Path
{
"path_begin":
{
"type":"port",
"log_name":"ClkB",
"phy_name":"ClkB"
},
"path_end":
{
"type":"pin",
"log_name":"MyCDC01/A_Sig1_c.ff_inst/CLK",
"phy_name":"MyCDC01.A_Sig1_c.SLICE_2/CLK"
},
"path_sections":[
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":9.803,
"delay":0.000
},
{
"type":"net_delay",
"net":
{
"log_name":"ClkB",
"phy_name":"ClkB"
},
"arrive":9.803,
"delay":0.000
},
{
"type":"site_delay",
"pin0":
{
"log_name":"ClkB_pad.bb_inst/B",
"phy_name":"ClkB_pad.bb_inst/IOPAD"
},
"pin1":
{
"log_name":"ClkB_pad.bb_inst/O",
"phy_name":"ClkB_pad.bb_inst/PADDI"
},
"arrive":11.169,
"delay":1.366
},
{
"type":"net_delay",
"net":
{
"log_name":"MyCDC01/ClkB_c",
"phy_name":"ClkB_c"
},
"arrive":13.467,
"delay":2.298
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":13.467,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- --------------- ---------------- --------- --------------------- ------
CONSTRAINT 0.000 9.803 1
ClkB top CLOCK LATENCY 0.000 9.803 1
ClkB NET DELAY 0.000 9.803 1
ClkB_pad.bb_inst/B->ClkB_pad.bb_inst/O SEIO33_CORE_J11 PADI_DEL 1.366 11.169 4
MyCDC01/ClkB_c NET DELAY 2.298 13.467 4
MyCDC01/A_Sig1_c.ff_inst/CLK CLOCK PIN 0.000 13.467 1
Uncertainty -(0.000) 13.467
Common Path Skew 0.116 13.583
Setup time -(-0.035) 13.618
---------------------------------------- --------------- ---------------- --------- --------------------- ------
Required Time 13.618
Arrival Time -(4.470)
---------------------------------------- --------------- ---------------- --------- --------------------- ------
Path Slack (Passed) 9.148
++++ Path 3 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Path Begin : MyCDC02/A_Sig1.ff_inst/Q (SLICE_R43C157B)
Path End : out1_i0.ff_inst/DF (SLICE_R42C157C)
Source Clock : ClkA (R)
Destination Clock: ClkA (R)
Logic Level : 2
Delay Ratio : 32.2% (route), 67.8% (logic)
Clock Skew : -0.146 ns
Setup Constraint : 10.000 ns
Common Path Skew : 0.119 ns
Path Slack : 9.268 ns (Passed)
Source Clock Path
{
"path_begin":
{
"type":"port",
"log_name":"ClkA",
"phy_name":"ClkA"
},
"path_end":
{
"type":"pin",
"log_name":"MyCDC02/A_Sig1.ff_inst/CLK",
"phy_name":"MyCDC02.A_Sig1.SLICE_0/CLK"
},
"path_sections":[
{
"type":"net_delay",
"net":
{
"log_name":"ClkA",
"phy_name":"ClkA"
},
"arrive":0.000,
"delay":0.000
},
{
"type":"site_delay",
"pin0":
{
"log_name":"ClkA_pad.bb_inst/B",
"phy_name":"ClkA_pad.bb_inst/IOPAD"
},
"pin1":
{
"log_name":"ClkA_pad.bb_inst/O",
"phy_name":"ClkA_pad.bb_inst/PADDI"
},
"arrive":1.366,
"delay":1.366
},
{
"type":"net_delay",
"net":
{
"log_name":"MyCDC02/ClkA_c",
"phy_name":"ClkA_c"
},
"arrive":3.923,
"delay":2.557
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":3.923,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- --------------- ---------------- --------- --------------------- ------
ClkA top CLOCK LATENCY 0.000 0.000 1
ClkA NET DELAY 0.000 0.000 1
ClkA_pad.bb_inst/B->ClkA_pad.bb_inst/O SEIO33_CORE_J16 PADI_DEL 1.366 1.366 4
MyCDC02/ClkA_c NET DELAY 2.557 3.923 4
MyCDC02/A_Sig1.ff_inst/CLK CLOCK PIN 0.000 3.923 1
Data Path
{
"path_begin":
{
"type":"pin",
"log_name":"MyCDC02/A_Sig1.ff_inst/Q",
"phy_name":"MyCDC02.A_Sig1.SLICE_0/Q0"
},
"path_end":
{
"type":"pin",
"log_name":"out1_i0.ff_inst/DF",
"phy_name":"SLICE_6/DI0"
},
"path_sections":[
{
"type":"site_delay",
"pin0":
{
"log_name":"MyCDC02/A_Sig1.ff_inst/CLK",
"phy_name":"MyCDC02.A_Sig1.SLICE_0/CLK"
},
"pin1":
{
"log_name":"MyCDC02/A_Sig1.ff_inst/Q",
"phy_name":"MyCDC02.A_Sig1.SLICE_0/Q0"
},
"arrive":4.227,
"delay":0.304
},
{
"type":"net_delay",
"net":
{
"log_name":"MyCDC02/B_sig1",
"phy_name":"B_sig1"
},
"arrive":4.473,
"delay":0.246
},
{
"type":"site_delay",
"pin0":
{
"log_name":"i5_2_lut/B",
"phy_name":"SLICE_6/D0"
},
"pin1":
{
"log_name":"i5_2_lut/Z",
"phy_name":"SLICE_6/F0"
},
"arrive":4.686,
"delay":0.213
},
{
"type":"net_delay",
"net":
{
"log_name":"out1_c_N_1",
"phy_name":"out1_c_N_1"
},
"arrive":4.686,
"delay":0.000
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":4.686,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- --------------- ---------------- --------- --------------------- ------
MyCDC02/A_Sig1.ff_inst/CLK->MyCDC02/A_Sig1.ff_inst/Q
SLICE_R43C157B REG_DEL 0.304 4.227 1
MyCDC02/B_sig1 NET DELAY 0.246 4.473 1
i5_2_lut/B->i5_2_lut/Z SLICE_R42C157C CTOF_DEL 0.213 4.686 1
out1_c_N_1 NET DELAY 0.000 4.686 1
out1_i0.ff_inst/DF ENDPOINT 0.000 4.686 1
Destination Clock Path
{
"path_begin":
{
"type":"port",
"log_name":"ClkA",
"phy_name":"ClkA"
},
"path_end":
{
"type":"pin",
"log_name":"out1_i0.ff_inst/CLK",
"phy_name":"SLICE_6/CLK"
},
"path_sections":[
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":10.000,
"delay":0.000
},
{
"type":"net_delay",
"net":
{
"log_name":"ClkA",
"phy_name":"ClkA"
},
"arrive":10.000,
"delay":0.000
},
{
"type":"site_delay",
"pin0":
{
"log_name":"ClkA_pad.bb_inst/B",
"phy_name":"ClkA_pad.bb_inst/IOPAD"
},
"pin1":
{
"log_name":"ClkA_pad.bb_inst/O",
"phy_name":"ClkA_pad.bb_inst/PADDI"
},
"arrive":11.366,
"delay":1.366
},
{
"type":"net_delay",
"net":
{
"log_name":"MyCDC02/ClkA_c",
"phy_name":"ClkA_c"
},
"arrive":13.777,
"delay":2.411
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":13.777,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- --------------- ---------------- --------- --------------------- ------
CONSTRAINT 0.000 10.000 1
ClkA top CLOCK LATENCY 0.000 10.000 1
ClkA NET DELAY 0.000 10.000 1
ClkA_pad.bb_inst/B->ClkA_pad.bb_inst/O SEIO33_CORE_J16 PADI_DEL 1.366 11.366 4
MyCDC02/ClkA_c NET DELAY 2.411 13.777 4
out1_i0.ff_inst/CLK CLOCK PIN 0.000 13.777 1
Uncertainty -(0.000) 13.777
Common Path Skew 0.119 13.896
Setup time -(-0.058) 13.954
---------------------------------------- --------------- ---------------- --------- --------------------- ------
Required Time 13.954
Arrival Time -(4.686)
---------------------------------------- --------------- ---------------- --------- --------------------- ------
Path Slack (Passed) 9.268
++++ Path 4 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Path Begin : MyCDC02/A_Sig_c.ff_inst/Q (SLICE_R44C157B)
Path End : MyCDC02/A_Sig1.ff_inst/DF (SLICE_R43C157B)
Source Clock : ClkA (R)
Destination Clock: ClkA (R)
Logic Level : 1
Delay Ratio : 49.8% (route), 50.2% (logic)
Clock Skew : -0.146 ns
Setup Constraint : 10.000 ns
Common Path Skew : 0.119 ns
Path Slack : 9.403 ns (Passed)
Source Clock Path
{
"path_begin":
{
"type":"port",
"log_name":"ClkA",
"phy_name":"ClkA"
},
"path_end":
{
"type":"pin",
"log_name":"MyCDC02/A_Sig_c.ff_inst/CLK",
"phy_name":"MyCDC02.A_Sig_c.SLICE_1/CLK"
},
"path_sections":[
{
"type":"net_delay",
"net":
{
"log_name":"ClkA",
"phy_name":"ClkA"
},
"arrive":0.000,
"delay":0.000
},
{
"type":"site_delay",
"pin0":
{
"log_name":"ClkA_pad.bb_inst/B",
"phy_name":"ClkA_pad.bb_inst/IOPAD"
},
"pin1":
{
"log_name":"ClkA_pad.bb_inst/O",
"phy_name":"ClkA_pad.bb_inst/PADDI"
},
"arrive":1.366,
"delay":1.366
},
{
"type":"net_delay",
"net":
{
"log_name":"MyCDC02/ClkA_c",
"phy_name":"ClkA_c"
},
"arrive":3.923,
"delay":2.557
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":3.923,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- --------------- ---------------- --------- --------------------- ------
ClkA top CLOCK LATENCY 0.000 0.000 1
ClkA NET DELAY 0.000 0.000 1
ClkA_pad.bb_inst/B->ClkA_pad.bb_inst/O SEIO33_CORE_J16 PADI_DEL 1.366 1.366 4
MyCDC02/ClkA_c NET DELAY 2.557 3.923 4
MyCDC02/A_Sig_c.ff_inst/CLK CLOCK PIN 0.000 3.923 1
Data Path
{
"path_begin":
{
"type":"pin",
"log_name":"MyCDC02/A_Sig_c.ff_inst/Q",
"phy_name":"MyCDC02.A_Sig_c.SLICE_1/Q0"
},
"path_end":
{
"type":"pin",
"log_name":"MyCDC02/A_Sig1.ff_inst/DF",
"phy_name":"MyCDC02.A_Sig1.SLICE_0/M0"
},
"path_sections":[
{
"type":"site_delay",
"pin0":
{
"log_name":"MyCDC02/A_Sig_c.ff_inst/CLK",
"phy_name":"MyCDC02.A_Sig_c.SLICE_1/CLK"
},
"pin1":
{
"log_name":"MyCDC02/A_Sig_c.ff_inst/Q",
"phy_name":"MyCDC02.A_Sig_c.SLICE_1/Q0"
},
"arrive":4.227,
"delay":0.304
},
{
"type":"net_delay",
"net":
{
"log_name":"MyCDC02/A_Sig",
"phy_name":"MyCDC02.A_Sig"
},
"arrive":4.528,
"delay":0.301
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":4.528,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- --------------- ---------------- --------- --------------------- ------
MyCDC02/A_Sig_c.ff_inst/CLK->MyCDC02/A_Sig_c.ff_inst/Q
SLICE_R44C157B REG_DEL 0.304 4.227 1
MyCDC02/A_Sig NET DELAY 0.301 4.528 1
MyCDC02/A_Sig1.ff_inst/DF ENDPOINT 0.000 4.528 1
Destination Clock Path
{
"path_begin":
{
"type":"port",
"log_name":"ClkA",
"phy_name":"ClkA"
},
"path_end":
{
"type":"pin",
"log_name":"MyCDC02/A_Sig1.ff_inst/CLK",
"phy_name":"MyCDC02.A_Sig1.SLICE_0/CLK"
},
"path_sections":[
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":10.000,
"delay":0.000
},
{
"type":"net_delay",
"net":
{
"log_name":"ClkA",
"phy_name":"ClkA"
},
"arrive":10.000,
"delay":0.000
},
{
"type":"site_delay",
"pin0":
{
"log_name":"ClkA_pad.bb_inst/B",
"phy_name":"ClkA_pad.bb_inst/IOPAD"
},
"pin1":
{
"log_name":"ClkA_pad.bb_inst/O",
"phy_name":"ClkA_pad.bb_inst/PADDI"
},
"arrive":11.366,
"delay":1.366
},
{
"type":"net_delay",
"net":
{
"log_name":"MyCDC02/ClkA_c",
"phy_name":"ClkA_c"
},
"arrive":13.777,
"delay":2.411
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":13.777,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- --------------- ---------------- --------- --------------------- ------
CONSTRAINT 0.000 10.000 1
ClkA top CLOCK LATENCY 0.000 10.000 1
ClkA NET DELAY 0.000 10.000 1
ClkA_pad.bb_inst/B->ClkA_pad.bb_inst/O SEIO33_CORE_J16 PADI_DEL 1.366 11.366 4
MyCDC02/ClkA_c NET DELAY 2.411 13.777 4
MyCDC02/A_Sig1.ff_inst/CLK CLOCK PIN 0.000 13.777 1
Uncertainty -(0.000) 13.777
Common Path Skew 0.119 13.896
Setup time -(-0.035) 13.931
---------------------------------------- --------------- ---------------- --------- --------------------- ------
Required Time 13.931
Arrival Time -(4.528)
---------------------------------------- --------------- ---------------- --------- --------------------- ------
Path Slack (Passed) 9.403
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
End of Detailed Report for timing paths
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
##########################################################
3 Setup at Speed Grade 9_High-Performance_1.0V Corner at 0 Degrees
3.1 Clock Summary
3.1.1 Clock "ClkA"
create_clock -name {ClkA} -period 10 [get_ports ClkA]
Single Clock Domain
-------------------------------------------------------------------------------------------------------
Clock ClkA | | Period | Frequency
-------------------------------------------------------------------------------------------------------
From ClkA | Target | 10.000 ns | 100.000 MHz
| Actual (all paths) | 5.000 ns | 200.000 MHz
ClkA_pad.bb_inst/B (MPW) | (50% duty cycle) | 5.000 ns | 200.000 MHz
-------------------------------------------------------------------------------------------------------
Clock Domain Crossing
------------------------------------------------------------------------------------------------------
Clock ClkA | Worst Time Between Edges | Comment
------------------------------------------------------------------------------------------------------
From ClkB | ---- | False path
------------------------------------------------------------------------------------------------------
3.1.2 Clock "ClkB"
create_clock -name {ClkB} -period 9.80392156862745 [get_ports ClkB]
Single Clock Domain
-------------------------------------------------------------------------------------------------------
Clock ClkB | | Period | Frequency
-------------------------------------------------------------------------------------------------------
From ClkB | Target | 9.804 ns | 102.000 MHz
| Actual (all paths) | 5.000 ns | 200.000 MHz
ClkB_pad.bb_inst/B (MPW) | (50% duty cycle) | 5.000 ns | 200.000 MHz
-------------------------------------------------------------------------------------------------------
Clock Domain Crossing
------------------------------------------------------------------------------------------------------
Clock ClkB | Worst Time Between Edges | Comment
------------------------------------------------------------------------------------------------------
From ClkA | ---- | False path
------------------------------------------------------------------------------------------------------
3.2 Endpoint slacks
-------------------------------------------------------
Listing 4 End Points | Slack
-------------------------------------------------------
out2_i1.ff_inst/DF | 9.045 ns
MyCDC01/A_Sig1_c.ff_inst/DF | 9.162 ns
out1_i0.ff_inst/DF | 9.278 ns
MyCDC02/A_Sig1.ff_inst/DF | 9.407 ns
-------------------------------------------------------
|
Setup # of endpoints with negative slack:| 0
|
-------------------------------------------------------
3.3 Detailed Report
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
Detail report of critical paths
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Detailed Report for timing paths
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++++Path 1 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Path Begin : MyCDC01/A_Sig1_c.ff_inst/Q (SLICE_R43C157D)
Path End : out2_i1.ff_inst/DF (SLICE_R44C157D)
Source Clock : ClkB (R)
Destination Clock: ClkB (R)
Logic Level : 2
Delay Ratio : 34.3% (route), 65.7% (logic)
Clock Skew : -0.154 ns
Setup Constraint : 9.803 ns
Common Path Skew : 0.125 ns
Path Slack : 9.044 ns (Passed)
Source Clock Path
{
"path_begin":
{
"type":"port",
"log_name":"ClkB",
"phy_name":"ClkB"
},
"path_end":
{
"type":"pin",
"log_name":"MyCDC01/A_Sig1_c.ff_inst/CLK",
"phy_name":"MyCDC01.A_Sig1_c.SLICE_2/CLK"
},
"path_sections":[
{
"type":"net_delay",
"net":
{
"log_name":"ClkB",
"phy_name":"ClkB"
},
"arrive":0.000,
"delay":0.000
},
{
"type":"site_delay",
"pin0":
{
"log_name":"ClkB_pad.bb_inst/B",
"phy_name":"ClkB_pad.bb_inst/IOPAD"
},
"pin1":
{
"log_name":"ClkB_pad.bb_inst/O",
"phy_name":"ClkB_pad.bb_inst/PADDI"
},
"arrive":1.238,
"delay":1.238
},
{
"type":"net_delay",
"net":
{
"log_name":"MyCDC01/ClkB_c",
"phy_name":"ClkB_c"
},
"arrive":3.866,
"delay":2.628
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":3.866,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- --------------- ---------------- --------- --------------------- ------
ClkB top CLOCK LATENCY 0.000 0.000 1
ClkB NET DELAY 0.000 0.000 1
ClkB_pad.bb_inst/B->ClkB_pad.bb_inst/O SEIO33_CORE_J11 PADI_DEL 1.238 1.238 4
MyCDC01/ClkB_c NET DELAY 2.628 3.866 4
MyCDC01/A_Sig1_c.ff_inst/CLK CLOCK PIN 0.000 3.866 1
Data Path
{
"path_begin":
{
"type":"pin",
"log_name":"MyCDC01/A_Sig1_c.ff_inst/Q",
"phy_name":"MyCDC01.A_Sig1_c.SLICE_2/Q0"
},
"path_end":
{
"type":"pin",
"log_name":"out2_i1.ff_inst/DF",
"phy_name":"SLICE_4/DI0"
},
"path_sections":[
{
"type":"site_delay",
"pin0":
{
"log_name":"MyCDC01/A_Sig1_c.ff_inst/CLK",
"phy_name":"MyCDC01.A_Sig1_c.SLICE_2/CLK"
},
"pin1":
{
"log_name":"MyCDC01/A_Sig1_c.ff_inst/Q",
"phy_name":"MyCDC01.A_Sig1_c.SLICE_2/Q0"
},
"arrive":4.171,
"delay":0.305
},
{
"type":"net_delay",
"net":
{
"log_name":"MyCDC01/A_Sig1",
"phy_name":"A_Sig1"
},
"arrive":4.441,
"delay":0.270
},
{
"type":"site_delay",
"pin0":
{
"log_name":"i9_2_lut/B",
"phy_name":"SLICE_4/A0"
},
"pin1":
{
"log_name":"i9_2_lut/Z",
"phy_name":"SLICE_4/F0"
},
"arrive":4.654,
"delay":0.213
},
{
"type":"net_delay",
"net":
{
"log_name":"out2_c_N_2",
"phy_name":"out2_c_N_2"
},
"arrive":4.654,
"delay":0.000
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":4.654,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- --------------- ---------------- --------- --------------------- ------
MyCDC01/A_Sig1_c.ff_inst/CLK->MyCDC01/A_Sig1_c.ff_inst/Q
SLICE_R43C157D REG_DEL 0.305 4.171 1
MyCDC01/A_Sig1 NET DELAY 0.270 4.441 1
i9_2_lut/B->i9_2_lut/Z SLICE_R44C157D CTOF_DEL 0.213 4.654 1
out2_c_N_2 NET DELAY 0.000 4.654 1
out2_i1.ff_inst/DF ENDPOINT 0.000 4.654 1
Destination Clock Path
{
"path_begin":
{
"type":"port",
"log_name":"ClkB",
"phy_name":"ClkB"
},
"path_end":
{
"type":"pin",
"log_name":"out2_i1.ff_inst/CLK",
"phy_name":"SLICE_4/CLK"
},
"path_sections":[
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":9.803,
"delay":0.000
},
{
"type":"net_delay",
"net":
{
"log_name":"ClkB",
"phy_name":"ClkB"
},
"arrive":9.803,
"delay":0.000
},
{
"type":"site_delay",
"pin0":
{
"log_name":"ClkB_pad.bb_inst/B",
"phy_name":"ClkB_pad.bb_inst/IOPAD"
},
"pin1":
{
"log_name":"ClkB_pad.bb_inst/O",
"phy_name":"ClkB_pad.bb_inst/PADDI"
},
"arrive":11.041,
"delay":1.238
},
{
"type":"net_delay",
"net":
{
"log_name":"MyCDC01/ClkB_c",
"phy_name":"ClkB_c"
},
"arrive":13.515,
"delay":2.474
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":13.515,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- --------------- ---------------- --------- --------------------- ------
CONSTRAINT 0.000 9.803 1
ClkB top CLOCK LATENCY 0.000 9.803 1
ClkB NET DELAY 0.000 9.803 1
ClkB_pad.bb_inst/B->ClkB_pad.bb_inst/O SEIO33_CORE_J11 PADI_DEL 1.238 11.041 4
MyCDC01/ClkB_c NET DELAY 2.474 13.515 4
out2_i1.ff_inst/CLK CLOCK PIN 0.000 13.515 1
Uncertainty -(0.000) 13.515
Common Path Skew 0.125 13.640
Setup time -(-0.058) 13.698
---------------------------------------- --------------- ---------------- --------- --------------------- ------
Required Time 13.698
Arrival Time -(4.654)
---------------------------------------- --------------- ---------------- --------- --------------------- ------
Path Slack (Passed) 9.044
++++ Path 2 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Path Begin : MyCDC01/A_Sig_c.ff_inst/Q (SLICE_R42C157B)
Path End : MyCDC01/A_Sig1_c.ff_inst/DF (SLICE_R43C157D)
Source Clock : ClkB (R)
Destination Clock: ClkB (R)
Logic Level : 1
Delay Ratio : 54.6% (route), 45.4% (logic)
Clock Skew : -0.154 ns
Setup Constraint : 9.803 ns
Common Path Skew : 0.125 ns
Path Slack : 9.161 ns (Passed)
Source Clock Path
{
"path_begin":
{
"type":"port",
"log_name":"ClkB",
"phy_name":"ClkB"
},
"path_end":
{
"type":"pin",
"log_name":"MyCDC01/A_Sig_c.ff_inst/CLK",
"phy_name":"MyCDC01.A_Sig_c.SLICE_3/CLK"
},
"path_sections":[
{
"type":"net_delay",
"net":
{
"log_name":"ClkB",
"phy_name":"ClkB"
},
"arrive":0.000,
"delay":0.000
},
{
"type":"site_delay",
"pin0":
{
"log_name":"ClkB_pad.bb_inst/B",
"phy_name":"ClkB_pad.bb_inst/IOPAD"
},
"pin1":
{
"log_name":"ClkB_pad.bb_inst/O",
"phy_name":"ClkB_pad.bb_inst/PADDI"
},
"arrive":1.238,
"delay":1.238
},
{
"type":"net_delay",
"net":
{
"log_name":"MyCDC01/ClkB_c",
"phy_name":"ClkB_c"
},
"arrive":3.866,
"delay":2.628
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":3.866,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- --------------- ---------------- --------- --------------------- ------
ClkB top CLOCK LATENCY 0.000 0.000 1
ClkB NET DELAY 0.000 0.000 1
ClkB_pad.bb_inst/B->ClkB_pad.bb_inst/O SEIO33_CORE_J11 PADI_DEL 1.238 1.238 4
MyCDC01/ClkB_c NET DELAY 2.628 3.866 4
MyCDC01/A_Sig_c.ff_inst/CLK CLOCK PIN 0.000 3.866 1
Data Path
{
"path_begin":
{
"type":"pin",
"log_name":"MyCDC01/A_Sig_c.ff_inst/Q",
"phy_name":"MyCDC01.A_Sig_c.SLICE_3/Q0"
},
"path_end":
{
"type":"pin",
"log_name":"MyCDC01/A_Sig1_c.ff_inst/DF",
"phy_name":"MyCDC01.A_Sig1_c.SLICE_2/M0"
},
"path_sections":[
{
"type":"site_delay",
"pin0":
{
"log_name":"MyCDC01/A_Sig_c.ff_inst/CLK",
"phy_name":"MyCDC01.A_Sig_c.SLICE_3/CLK"
},
"pin1":
{
"log_name":"MyCDC01/A_Sig_c.ff_inst/Q",
"phy_name":"MyCDC01.A_Sig_c.SLICE_3/Q0"
},
"arrive":4.159,
"delay":0.293
},
{
"type":"net_delay",
"net":
{
"log_name":"MyCDC01/A_Sig_adj_3",
"phy_name":"MyCDC01.A_Sig_adj_3"
},
"arrive":4.512,
"delay":0.353
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":4.512,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- --------------- ---------------- --------- --------------------- ------
MyCDC01/A_Sig_c.ff_inst/CLK->MyCDC01/A_Sig_c.ff_inst/Q
SLICE_R42C157B REG_DEL 0.293 4.159 1
MyCDC01/A_Sig_adj_3 NET DELAY 0.353 4.512 1
MyCDC01/A_Sig1_c.ff_inst/DF ENDPOINT 0.000 4.512 1
Destination Clock Path
{
"path_begin":
{
"type":"port",
"log_name":"ClkB",
"phy_name":"ClkB"
},
"path_end":
{
"type":"pin",
"log_name":"MyCDC01/A_Sig1_c.ff_inst/CLK",
"phy_name":"MyCDC01.A_Sig1_c.SLICE_2/CLK"
},
"path_sections":[
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":9.803,
"delay":0.000
},
{
"type":"net_delay",
"net":
{
"log_name":"ClkB",
"phy_name":"ClkB"
},
"arrive":9.803,
"delay":0.000
},
{
"type":"site_delay",
"pin0":
{
"log_name":"ClkB_pad.bb_inst/B",
"phy_name":"ClkB_pad.bb_inst/IOPAD"
},
"pin1":
{
"log_name":"ClkB_pad.bb_inst/O",
"phy_name":"ClkB_pad.bb_inst/PADDI"
},
"arrive":11.041,
"delay":1.238
},
{
"type":"net_delay",
"net":
{
"log_name":"MyCDC01/ClkB_c",
"phy_name":"ClkB_c"
},
"arrive":13.515,
"delay":2.474
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":13.515,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- --------------- ---------------- --------- --------------------- ------
CONSTRAINT 0.000 9.803 1
ClkB top CLOCK LATENCY 0.000 9.803 1
ClkB NET DELAY 0.000 9.803 1
ClkB_pad.bb_inst/B->ClkB_pad.bb_inst/O SEIO33_CORE_J11 PADI_DEL 1.238 11.041 4
MyCDC01/ClkB_c NET DELAY 2.474 13.515 4
MyCDC01/A_Sig1_c.ff_inst/CLK CLOCK PIN 0.000 13.515 1
Uncertainty -(0.000) 13.515
Common Path Skew 0.125 13.640
Setup time -(-0.033) 13.673
---------------------------------------- --------------- ---------------- --------- --------------------- ------
Required Time 13.673
Arrival Time -(4.512)
---------------------------------------- --------------- ---------------- --------- --------------------- ------
Path Slack (Passed) 9.161
++++ Path 3 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Path Begin : MyCDC02/A_Sig1.ff_inst/Q (SLICE_R43C157B)
Path End : out1_i0.ff_inst/DF (SLICE_R42C157C)
Source Clock : ClkA (R)
Destination Clock: ClkA (R)
Logic Level : 2
Delay Ratio : 31.1% (route), 68.9% (logic)
Clock Skew : -0.156 ns
Setup Constraint : 10.000 ns
Common Path Skew : 0.128 ns
Path Slack : 9.278 ns (Passed)
Source Clock Path
{
"path_begin":
{
"type":"port",
"log_name":"ClkA",
"phy_name":"ClkA"
},
"path_end":
{
"type":"pin",
"log_name":"MyCDC02/A_Sig1.ff_inst/CLK",
"phy_name":"MyCDC02.A_Sig1.SLICE_0/CLK"
},
"path_sections":[
{
"type":"net_delay",
"net":
{
"log_name":"ClkA",
"phy_name":"ClkA"
},
"arrive":0.000,
"delay":0.000
},
{
"type":"site_delay",
"pin0":
{
"log_name":"ClkA_pad.bb_inst/B",
"phy_name":"ClkA_pad.bb_inst/IOPAD"
},
"pin1":
{
"log_name":"ClkA_pad.bb_inst/O",
"phy_name":"ClkA_pad.bb_inst/PADDI"
},
"arrive":1.238,
"delay":1.238
},
{
"type":"net_delay",
"net":
{
"log_name":"MyCDC02/ClkA_c",
"phy_name":"ClkA_c"
},
"arrive":3.990,
"delay":2.752
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":3.990,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- --------------- ---------------- --------- --------------------- ------
ClkA top CLOCK LATENCY 0.000 0.000 1
ClkA NET DELAY 0.000 0.000 1
ClkA_pad.bb_inst/B->ClkA_pad.bb_inst/O SEIO33_CORE_J16 PADI_DEL 1.238 1.238 4
MyCDC02/ClkA_c NET DELAY 2.752 3.990 4
MyCDC02/A_Sig1.ff_inst/CLK CLOCK PIN 0.000 3.990 1
Data Path
{
"path_begin":
{
"type":"pin",
"log_name":"MyCDC02/A_Sig1.ff_inst/Q",
"phy_name":"MyCDC02.A_Sig1.SLICE_0/Q0"
},
"path_end":
{
"type":"pin",
"log_name":"out1_i0.ff_inst/DF",
"phy_name":"SLICE_6/DI0"
},
"path_sections":[
{
"type":"site_delay",
"pin0":
{
"log_name":"MyCDC02/A_Sig1.ff_inst/CLK",
"phy_name":"MyCDC02.A_Sig1.SLICE_0/CLK"
},
"pin1":
{
"log_name":"MyCDC02/A_Sig1.ff_inst/Q",
"phy_name":"MyCDC02.A_Sig1.SLICE_0/Q0"
},
"arrive":4.295,
"delay":0.305
},
{
"type":"net_delay",
"net":
{
"log_name":"MyCDC02/B_sig1",
"phy_name":"B_sig1"
},
"arrive":4.529,
"delay":0.234
},
{
"type":"site_delay",
"pin0":
{
"log_name":"i5_2_lut/B",
"phy_name":"SLICE_6/D0"
},
"pin1":
{
"log_name":"i5_2_lut/Z",
"phy_name":"SLICE_6/F0"
},
"arrive":4.742,
"delay":0.213
},
{
"type":"net_delay",
"net":
{
"log_name":"out1_c_N_1",
"phy_name":"out1_c_N_1"
},
"arrive":4.742,
"delay":0.000
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":4.742,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- --------------- ---------------- --------- --------------------- ------
MyCDC02/A_Sig1.ff_inst/CLK->MyCDC02/A_Sig1.ff_inst/Q
SLICE_R43C157B REG_DEL 0.305 4.295 1
MyCDC02/B_sig1 NET DELAY 0.234 4.529 1
i5_2_lut/B->i5_2_lut/Z SLICE_R42C157C CTOF_DEL 0.213 4.742 1
out1_c_N_1 NET DELAY 0.000 4.742 1
out1_i0.ff_inst/DF ENDPOINT 0.000 4.742 1
Destination Clock Path
{
"path_begin":
{
"type":"port",
"log_name":"ClkA",
"phy_name":"ClkA"
},
"path_end":
{
"type":"pin",
"log_name":"out1_i0.ff_inst/CLK",
"phy_name":"SLICE_6/CLK"
},
"path_sections":[
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":10.000,
"delay":0.000
},
{
"type":"net_delay",
"net":
{
"log_name":"ClkA",
"phy_name":"ClkA"
},
"arrive":10.000,
"delay":0.000
},
{
"type":"site_delay",
"pin0":
{
"log_name":"ClkA_pad.bb_inst/B",
"phy_name":"ClkA_pad.bb_inst/IOPAD"
},
"pin1":
{
"log_name":"ClkA_pad.bb_inst/O",
"phy_name":"ClkA_pad.bb_inst/PADDI"
},
"arrive":11.238,
"delay":1.238
},
{
"type":"net_delay",
"net":
{
"log_name":"MyCDC02/ClkA_c",
"phy_name":"ClkA_c"
},
"arrive":13.834,
"delay":2.596
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":13.834,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- --------------- ---------------- --------- --------------------- ------
CONSTRAINT 0.000 10.000 1
ClkA top CLOCK LATENCY 0.000 10.000 1
ClkA NET DELAY 0.000 10.000 1
ClkA_pad.bb_inst/B->ClkA_pad.bb_inst/O SEIO33_CORE_J16 PADI_DEL 1.238 11.238 4
MyCDC02/ClkA_c NET DELAY 2.596 13.834 4
out1_i0.ff_inst/CLK CLOCK PIN 0.000 13.834 1
Uncertainty -(0.000) 13.834
Common Path Skew 0.128 13.962
Setup time -(-0.058) 14.020
---------------------------------------- --------------- ---------------- --------- --------------------- ------
Required Time 14.020
Arrival Time -(4.742)
---------------------------------------- --------------- ---------------- --------- --------------------- ------
Path Slack (Passed) 9.278
++++ Path 4 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Path Begin : MyCDC02/A_Sig_c.ff_inst/Q (SLICE_R44C157B)
Path End : MyCDC02/A_Sig1.ff_inst/DF (SLICE_R43C157B)
Source Clock : ClkA (R)
Destination Clock: ClkA (R)
Logic Level : 1
Delay Ratio : 51.0% (route), 49.0% (logic)
Clock Skew : -0.156 ns
Setup Constraint : 10.000 ns
Common Path Skew : 0.128 ns
Path Slack : 9.407 ns (Passed)
Source Clock Path
{
"path_begin":
{
"type":"port",
"log_name":"ClkA",
"phy_name":"ClkA"
},
"path_end":
{
"type":"pin",
"log_name":"MyCDC02/A_Sig_c.ff_inst/CLK",
"phy_name":"MyCDC02.A_Sig_c.SLICE_1/CLK"
},
"path_sections":[
{
"type":"net_delay",
"net":
{
"log_name":"ClkA",
"phy_name":"ClkA"
},
"arrive":0.000,
"delay":0.000
},
{
"type":"site_delay",
"pin0":
{
"log_name":"ClkA_pad.bb_inst/B",
"phy_name":"ClkA_pad.bb_inst/IOPAD"
},
"pin1":
{
"log_name":"ClkA_pad.bb_inst/O",
"phy_name":"ClkA_pad.bb_inst/PADDI"
},
"arrive":1.238,
"delay":1.238
},
{
"type":"net_delay",
"net":
{
"log_name":"MyCDC02/ClkA_c",
"phy_name":"ClkA_c"
},
"arrive":3.990,
"delay":2.752
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":3.990,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- --------------- ---------------- --------- --------------------- ------
ClkA top CLOCK LATENCY 0.000 0.000 1
ClkA NET DELAY 0.000 0.000 1
ClkA_pad.bb_inst/B->ClkA_pad.bb_inst/O SEIO33_CORE_J16 PADI_DEL 1.238 1.238 4
MyCDC02/ClkA_c NET DELAY 2.752 3.990 4
MyCDC02/A_Sig_c.ff_inst/CLK CLOCK PIN 0.000 3.990 1
Data Path
{
"path_begin":
{
"type":"pin",
"log_name":"MyCDC02/A_Sig_c.ff_inst/Q",
"phy_name":"MyCDC02.A_Sig_c.SLICE_1/Q0"
},
"path_end":
{
"type":"pin",
"log_name":"MyCDC02/A_Sig1.ff_inst/DF",
"phy_name":"MyCDC02.A_Sig1.SLICE_0/M0"
},
"path_sections":[
{
"type":"site_delay",
"pin0":
{
"log_name":"MyCDC02/A_Sig_c.ff_inst/CLK",
"phy_name":"MyCDC02.A_Sig_c.SLICE_1/CLK"
},
"pin1":
{
"log_name":"MyCDC02/A_Sig_c.ff_inst/Q",
"phy_name":"MyCDC02.A_Sig_c.SLICE_1/Q0"
},
"arrive":4.283,
"delay":0.293
},
{
"type":"net_delay",
"net":
{
"log_name":"MyCDC02/A_Sig",
"phy_name":"MyCDC02.A_Sig"
},
"arrive":4.588,
"delay":0.305
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":4.588,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- --------------- ---------------- --------- --------------------- ------
MyCDC02/A_Sig_c.ff_inst/CLK->MyCDC02/A_Sig_c.ff_inst/Q
SLICE_R44C157B REG_DEL 0.293 4.283 1
MyCDC02/A_Sig NET DELAY 0.305 4.588 1
MyCDC02/A_Sig1.ff_inst/DF ENDPOINT 0.000 4.588 1
Destination Clock Path
{
"path_begin":
{
"type":"port",
"log_name":"ClkA",
"phy_name":"ClkA"
},
"path_end":
{
"type":"pin",
"log_name":"MyCDC02/A_Sig1.ff_inst/CLK",
"phy_name":"MyCDC02.A_Sig1.SLICE_0/CLK"
},
"path_sections":[
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":10.000,
"delay":0.000
},
{
"type":"net_delay",
"net":
{
"log_name":"ClkA",
"phy_name":"ClkA"
},
"arrive":10.000,
"delay":0.000
},
{
"type":"site_delay",
"pin0":
{
"log_name":"ClkA_pad.bb_inst/B",
"phy_name":"ClkA_pad.bb_inst/IOPAD"
},
"pin1":
{
"log_name":"ClkA_pad.bb_inst/O",
"phy_name":"ClkA_pad.bb_inst/PADDI"
},
"arrive":11.238,
"delay":1.238
},
{
"type":"net_delay",
"net":
{
"log_name":"MyCDC02/ClkA_c",
"phy_name":"ClkA_c"
},
"arrive":13.834,
"delay":2.596
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":13.834,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- --------------- ---------------- --------- --------------------- ------
CONSTRAINT 0.000 10.000 1
ClkA top CLOCK LATENCY 0.000 10.000 1
ClkA NET DELAY 0.000 10.000 1
ClkA_pad.bb_inst/B->ClkA_pad.bb_inst/O SEIO33_CORE_J16 PADI_DEL 1.238 11.238 4
MyCDC02/ClkA_c NET DELAY 2.596 13.834 4
MyCDC02/A_Sig1.ff_inst/CLK CLOCK PIN 0.000 13.834 1
Uncertainty -(0.000) 13.834
Common Path Skew 0.128 13.962
Setup time -(-0.033) 13.995
---------------------------------------- --------------- ---------------- --------- --------------------- ------
Required Time 13.995
Arrival Time -(4.588)
---------------------------------------- --------------- ---------------- --------- --------------------- ------
Path Slack (Passed) 9.407
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
End of Detailed Report for timing paths
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
##########################################################
4 Hold at Speed Grade m Corner at 0 Degrees
4.1 Endpoint slacks
-------------------------------------------------------
Listing 4 End Points | Slack
-------------------------------------------------------
MyCDC02/A_Sig1.ff_inst/DF | 0.218 ns
MyCDC01/A_Sig1_c.ff_inst/DF | 0.229 ns
out1_i0.ff_inst/DF | 0.272 ns
out2_i1.ff_inst/DF | 0.290 ns
-------------------------------------------------------
|
Hold # of endpoints with negative slack: | 0
|
-------------------------------------------------------
4.2 Detailed Report
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
Detail report of critical paths
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Detailed Report for timing paths
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++++Path 1 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Path Begin : MyCDC02/A_Sig_c.ff_inst/Q (SLICE_R44C157B)
Path End : MyCDC02/A_Sig1.ff_inst/DF (SLICE_R43C157B)
Source Clock : ClkA (R)
Destination Clock: ClkA (R)
Logic Level : 1
Delay Ratio : 47.3% (route), 52.7% (logic)
Clock Skew : 0.121 ns
Hold Constraint : 0.000 ns
Common Path Skew : -0.108 ns
Path Slack : 0.218 ns (Passed)
Source Clock Path
{
"path_begin":
{
"type":"port",
"log_name":"ClkA",
"phy_name":"ClkA"
},
"path_end":
{
"type":"pin",
"log_name":"MyCDC02/A_Sig_c.ff_inst/CLK",
"phy_name":"MyCDC02.A_Sig_c.SLICE_1/CLK"
},
"path_sections":[
{
"type":"net_delay",
"net":
{
"log_name":"ClkA",
"phy_name":"ClkA"
},
"arrive":0.000,
"delay":0.000
},
{
"type":"site_delay",
"pin0":
{
"log_name":"ClkA_pad.bb_inst/B",
"phy_name":"ClkA_pad.bb_inst/IOPAD"
},
"pin1":
{
"log_name":"ClkA_pad.bb_inst/O",
"phy_name":"ClkA_pad.bb_inst/PADDI"
},
"arrive":1.000,
"delay":1.000
},
{
"type":"net_delay",
"net":
{
"log_name":"MyCDC02/ClkA_c",
"phy_name":"ClkA_c"
},
"arrive":2.865,
"delay":1.865
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":2.865,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- --------------- ---------------- ------ --------------------- ------
ClkA top CLOCK LATENCY 0.000 0.000 1
ClkA NET DELAY 0.000 0.000 1
ClkA_pad.bb_inst/B->ClkA_pad.bb_inst/O SEIO33_CORE_J16 PADI_DEL 1.000 1.000 4
MyCDC02/ClkA_c NET DELAY 1.865 2.865 4
MyCDC02/A_Sig_c.ff_inst/CLK CLOCK PIN 0.000 2.865 1
Data Path
{
"path_begin":
{
"type":"pin",
"log_name":"MyCDC02/A_Sig_c.ff_inst/Q",
"phy_name":"MyCDC02.A_Sig_c.SLICE_1/Q0"
},
"path_end":
{
"type":"pin",
"log_name":"MyCDC02/A_Sig1.ff_inst/DF",
"phy_name":"MyCDC02.A_Sig1.SLICE_0/M0"
},
"path_sections":[
{
"type":"site_delay",
"pin0":
{
"log_name":"MyCDC02/A_Sig_c.ff_inst/CLK",
"phy_name":"MyCDC02.A_Sig_c.SLICE_1/CLK"
},
"pin1":
{
"log_name":"MyCDC02/A_Sig_c.ff_inst/Q",
"phy_name":"MyCDC02.A_Sig_c.SLICE_1/Q0"
},
"arrive":3.038,
"delay":0.173
},
{
"type":"net_delay",
"net":
{
"log_name":"MyCDC02/A_Sig",
"phy_name":"MyCDC02.A_Sig"
},
"arrive":3.193,
"delay":0.155
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":3.193,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- --------------- ---------------- ------ --------------------- ------
MyCDC02/A_Sig_c.ff_inst/CLK->MyCDC02/A_Sig_c.ff_inst/Q
SLICE_R44C157B REG_DEL 0.173 3.038 1
MyCDC02/A_Sig NET DELAY 0.155 3.193 1
MyCDC02/A_Sig1.ff_inst/DF ENDPOINT 0.000 3.193 1
Destination Clock Path
{
"path_begin":
{
"type":"port",
"log_name":"ClkA",
"phy_name":"ClkA"
},
"path_end":
{
"type":"pin",
"log_name":"MyCDC02/A_Sig1.ff_inst/CLK",
"phy_name":"MyCDC02.A_Sig1.SLICE_0/CLK"
},
"path_sections":[
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":0.000,
"delay":0.000
},
{
"type":"net_delay",
"net":
{
"log_name":"ClkA",
"phy_name":"ClkA"
},
"arrive":0.000,
"delay":0.000
},
{
"type":"site_delay",
"pin0":
{
"log_name":"ClkA_pad.bb_inst/B",
"phy_name":"ClkA_pad.bb_inst/IOPAD"
},
"pin1":
{
"log_name":"ClkA_pad.bb_inst/O",
"phy_name":"ClkA_pad.bb_inst/PADDI"
},
"arrive":1.000,
"delay":1.000
},
{
"type":"net_delay",
"net":
{
"log_name":"MyCDC02/ClkA_c",
"phy_name":"ClkA_c"
},
"arrive":2.986,
"delay":1.986
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":2.986,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- --------------- ---------------- ------ --------------------- ------
CONSTRAINT 0.000 0.000 1
ClkA top CLOCK LATENCY 0.000 0.000 1
ClkA NET DELAY 0.000 0.000 1
ClkA_pad.bb_inst/B->ClkA_pad.bb_inst/O SEIO33_CORE_J16 PADI_DEL 1.000 1.000 4
MyCDC02/ClkA_c NET DELAY 1.986 2.986 4
MyCDC02/A_Sig1.ff_inst/CLK CLOCK PIN 0.000 2.986 1
Uncertainty 0.000 2.986
Common Path Skew -0.108 2.878
Hold time 0.097 2.975
---------------------------------------- --------------- ---------------- ------ --------------------- ------
Required Time -2.975
Arrival Time 3.193
---------------------------------------- --------------- ---------------- ------ --------------------- ------
Path Slack (Passed) 0.218
++++ Path 2 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Path Begin : MyCDC01/A_Sig_c.ff_inst/Q (SLICE_R42C157B)
Path End : MyCDC01/A_Sig1_c.ff_inst/DF (SLICE_R43C157D)
Source Clock : ClkB (R)
Destination Clock: ClkB (R)
Logic Level : 1
Delay Ratio : 49.1% (route), 50.9% (logic)
Clock Skew : 0.119 ns
Hold Constraint : 0.000 ns
Common Path Skew : -0.105 ns
Path Slack : 0.229 ns (Passed)
Source Clock Path
{
"path_begin":
{
"type":"port",
"log_name":"ClkB",
"phy_name":"ClkB"
},
"path_end":
{
"type":"pin",
"log_name":"MyCDC01/A_Sig_c.ff_inst/CLK",
"phy_name":"MyCDC01.A_Sig_c.SLICE_3/CLK"
},
"path_sections":[
{
"type":"net_delay",
"net":
{
"log_name":"ClkB",
"phy_name":"ClkB"
},
"arrive":0.000,
"delay":0.000
},
{
"type":"site_delay",
"pin0":
{
"log_name":"ClkB_pad.bb_inst/B",
"phy_name":"ClkB_pad.bb_inst/IOPAD"
},
"pin1":
{
"log_name":"ClkB_pad.bb_inst/O",
"phy_name":"ClkB_pad.bb_inst/PADDI"
},
"arrive":1.000,
"delay":1.000
},
{
"type":"net_delay",
"net":
{
"log_name":"MyCDC01/ClkB_c",
"phy_name":"ClkB_c"
},
"arrive":2.779,
"delay":1.779
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":2.779,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- --------------- ---------------- ------ --------------------- ------
ClkB top CLOCK LATENCY 0.000 0.000 1
ClkB NET DELAY 0.000 0.000 1
ClkB_pad.bb_inst/B->ClkB_pad.bb_inst/O SEIO33_CORE_J11 PADI_DEL 1.000 1.000 4
MyCDC01/ClkB_c NET DELAY 1.779 2.779 4
MyCDC01/A_Sig_c.ff_inst/CLK CLOCK PIN 0.000 2.779 1
Data Path
{
"path_begin":
{
"type":"pin",
"log_name":"MyCDC01/A_Sig_c.ff_inst/Q",
"phy_name":"MyCDC01.A_Sig_c.SLICE_3/Q0"
},
"path_end":
{
"type":"pin",
"log_name":"MyCDC01/A_Sig1_c.ff_inst/DF",
"phy_name":"MyCDC01.A_Sig1_c.SLICE_2/M0"
},
"path_sections":[
{
"type":"site_delay",
"pin0":
{
"log_name":"MyCDC01/A_Sig_c.ff_inst/CLK",
"phy_name":"MyCDC01.A_Sig_c.SLICE_3/CLK"
},
"pin1":
{
"log_name":"MyCDC01/A_Sig_c.ff_inst/Q",
"phy_name":"MyCDC01.A_Sig_c.SLICE_3/Q0"
},
"arrive":2.952,
"delay":0.173
},
{
"type":"net_delay",
"net":
{
"log_name":"MyCDC01/A_Sig_adj_3",
"phy_name":"MyCDC01.A_Sig_adj_3"
},
"arrive":3.119,
"delay":0.167
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":3.119,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- --------------- ---------------- ------ --------------------- ------
MyCDC01/A_Sig_c.ff_inst/CLK->MyCDC01/A_Sig_c.ff_inst/Q
SLICE_R42C157B REG_DEL 0.173 2.952 1
MyCDC01/A_Sig_adj_3 NET DELAY 0.167 3.119 1
MyCDC01/A_Sig1_c.ff_inst/DF ENDPOINT 0.000 3.119 1
Destination Clock Path
{
"path_begin":
{
"type":"port",
"log_name":"ClkB",
"phy_name":"ClkB"
},
"path_end":
{
"type":"pin",
"log_name":"MyCDC01/A_Sig1_c.ff_inst/CLK",
"phy_name":"MyCDC01.A_Sig1_c.SLICE_2/CLK"
},
"path_sections":[
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":0.000,
"delay":0.000
},
{
"type":"net_delay",
"net":
{
"log_name":"ClkB",
"phy_name":"ClkB"
},
"arrive":0.000,
"delay":0.000
},
{
"type":"site_delay",
"pin0":
{
"log_name":"ClkB_pad.bb_inst/B",
"phy_name":"ClkB_pad.bb_inst/IOPAD"
},
"pin1":
{
"log_name":"ClkB_pad.bb_inst/O",
"phy_name":"ClkB_pad.bb_inst/PADDI"
},
"arrive":1.000,
"delay":1.000
},
{
"type":"net_delay",
"net":
{
"log_name":"MyCDC01/ClkB_c",
"phy_name":"ClkB_c"
},
"arrive":2.898,
"delay":1.898
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":2.898,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- --------------- ---------------- ------ --------------------- ------
CONSTRAINT 0.000 0.000 1
ClkB top CLOCK LATENCY 0.000 0.000 1
ClkB NET DELAY 0.000 0.000 1
ClkB_pad.bb_inst/B->ClkB_pad.bb_inst/O SEIO33_CORE_J11 PADI_DEL 1.000 1.000 4
MyCDC01/ClkB_c NET DELAY 1.898 2.898 4
MyCDC01/A_Sig1_c.ff_inst/CLK CLOCK PIN 0.000 2.898 1
Uncertainty 0.000 2.898
Common Path Skew -0.105 2.793
Hold time 0.097 2.890
---------------------------------------- --------------- ---------------- ------ --------------------- ------
Required Time -2.890
Arrival Time 3.119
---------------------------------------- --------------- ---------------- ------ --------------------- ------
Path Slack (Passed) 0.229
++++ Path 3 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Path Begin : MyCDC02/A_Sig1.ff_inst/Q (SLICE_R43C157B)
Path End : out1_i0.ff_inst/DF (SLICE_R42C157C)
Source Clock : ClkA (R)
Destination Clock: ClkA (R)
Logic Level : 2
Delay Ratio : 27.6% (route), 72.4% (logic)
Clock Skew : 0.121 ns
Hold Constraint : 0.000 ns
Common Path Skew : -0.108 ns
Path Slack : 0.272 ns (Passed)
Source Clock Path
{
"path_begin":
{
"type":"port",
"log_name":"ClkA",
"phy_name":"ClkA"
},
"path_end":
{
"type":"pin",
"log_name":"MyCDC02/A_Sig1.ff_inst/CLK",
"phy_name":"MyCDC02.A_Sig1.SLICE_0/CLK"
},
"path_sections":[
{
"type":"net_delay",
"net":
{
"log_name":"ClkA",
"phy_name":"ClkA"
},
"arrive":0.000,
"delay":0.000
},
{
"type":"site_delay",
"pin0":
{
"log_name":"ClkA_pad.bb_inst/B",
"phy_name":"ClkA_pad.bb_inst/IOPAD"
},
"pin1":
{
"log_name":"ClkA_pad.bb_inst/O",
"phy_name":"ClkA_pad.bb_inst/PADDI"
},
"arrive":1.000,
"delay":1.000
},
{
"type":"net_delay",
"net":
{
"log_name":"MyCDC02/ClkA_c",
"phy_name":"ClkA_c"
},
"arrive":2.865,
"delay":1.865
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":2.865,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- --------------- ---------------- ------ --------------------- ------
ClkA top CLOCK LATENCY 0.000 0.000 1
ClkA NET DELAY 0.000 0.000 1
ClkA_pad.bb_inst/B->ClkA_pad.bb_inst/O SEIO33_CORE_J16 PADI_DEL 1.000 1.000 4
MyCDC02/ClkA_c NET DELAY 1.865 2.865 4
MyCDC02/A_Sig1.ff_inst/CLK CLOCK PIN 0.000 2.865 1
Data Path
{
"path_begin":
{
"type":"pin",
"log_name":"MyCDC02/A_Sig1.ff_inst/Q",
"phy_name":"MyCDC02.A_Sig1.SLICE_0/Q0"
},
"path_end":
{
"type":"pin",
"log_name":"out1_i0.ff_inst/DF",
"phy_name":"SLICE_6/DI0"
},
"path_sections":[
{
"type":"site_delay",
"pin0":
{
"log_name":"MyCDC02/A_Sig1.ff_inst/CLK",
"phy_name":"MyCDC02.A_Sig1.SLICE_0/CLK"
},
"pin1":
{
"log_name":"MyCDC02/A_Sig1.ff_inst/Q",
"phy_name":"MyCDC02.A_Sig1.SLICE_0/Q0"
},
"arrive":3.038,
"delay":0.173
},
{
"type":"net_delay",
"net":
{
"log_name":"MyCDC02/B_sig1",
"phy_name":"B_sig1"
},
"arrive":3.148,
"delay":0.110
},
{
"type":"site_delay",
"pin0":
{
"log_name":"i5_2_lut/B",
"phy_name":"SLICE_6/D0"
},
"pin1":
{
"log_name":"i5_2_lut/Z",
"phy_name":"SLICE_6/F0"
},
"arrive":3.264,
"delay":0.116
},
{
"type":"net_delay",
"net":
{
"log_name":"out1_c_N_1",
"phy_name":"out1_c_N_1"
},
"arrive":3.264,
"delay":0.000
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":3.264,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- --------------- ---------------- ------ --------------------- ------
MyCDC02/A_Sig1.ff_inst/CLK->MyCDC02/A_Sig1.ff_inst/Q
SLICE_R43C157B REG_DEL 0.173 3.038 1
MyCDC02/B_sig1 NET DELAY 0.110 3.148 1
i5_2_lut/B->i5_2_lut/Z SLICE_R42C157C CTOF_DEL 0.116 3.264 1
out1_c_N_1 NET DELAY 0.000 3.264 1
out1_i0.ff_inst/DF ENDPOINT 0.000 3.264 1
Destination Clock Path
{
"path_begin":
{
"type":"port",
"log_name":"ClkA",
"phy_name":"ClkA"
},
"path_end":
{
"type":"pin",
"log_name":"out1_i0.ff_inst/CLK",
"phy_name":"SLICE_6/CLK"
},
"path_sections":[
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":0.000,
"delay":0.000
},
{
"type":"net_delay",
"net":
{
"log_name":"ClkA",
"phy_name":"ClkA"
},
"arrive":0.000,
"delay":0.000
},
{
"type":"site_delay",
"pin0":
{
"log_name":"ClkA_pad.bb_inst/B",
"phy_name":"ClkA_pad.bb_inst/IOPAD"
},
"pin1":
{
"log_name":"ClkA_pad.bb_inst/O",
"phy_name":"ClkA_pad.bb_inst/PADDI"
},
"arrive":1.000,
"delay":1.000
},
{
"type":"net_delay",
"net":
{
"log_name":"MyCDC02/ClkA_c",
"phy_name":"ClkA_c"
},
"arrive":2.986,
"delay":1.986
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":2.986,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- --------------- ---------------- ------ --------------------- ------
CONSTRAINT 0.000 0.000 1
ClkA top CLOCK LATENCY 0.000 0.000 1
ClkA NET DELAY 0.000 0.000 1
ClkA_pad.bb_inst/B->ClkA_pad.bb_inst/O SEIO33_CORE_J16 PADI_DEL 1.000 1.000 4
MyCDC02/ClkA_c NET DELAY 1.986 2.986 4
out1_i0.ff_inst/CLK CLOCK PIN 0.000 2.986 1
Uncertainty 0.000 2.986
Common Path Skew -0.108 2.878
Hold time 0.114 2.992
---------------------------------------- --------------- ---------------- ------ --------------------- ------
Required Time -2.992
Arrival Time 3.264
---------------------------------------- --------------- ---------------- ------ --------------------- ------
Path Slack (Passed) 0.272
++++ Path 4 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Path Begin : MyCDC01/A_Sig1_c.ff_inst/Q (SLICE_R43C157D)
Path End : out2_i1.ff_inst/DF (SLICE_R44C157D)
Source Clock : ClkB (R)
Destination Clock: ClkB (R)
Logic Level : 2
Delay Ratio : 30.9% (route), 69.1% (logic)
Clock Skew : 0.119 ns
Hold Constraint : 0.000 ns
Common Path Skew : -0.105 ns
Path Slack : 0.290 ns (Passed)
Source Clock Path
{
"path_begin":
{
"type":"port",
"log_name":"ClkB",
"phy_name":"ClkB"
},
"path_end":
{
"type":"pin",
"log_name":"MyCDC01/A_Sig1_c.ff_inst/CLK",
"phy_name":"MyCDC01.A_Sig1_c.SLICE_2/CLK"
},
"path_sections":[
{
"type":"net_delay",
"net":
{
"log_name":"ClkB",
"phy_name":"ClkB"
},
"arrive":0.000,
"delay":0.000
},
{
"type":"site_delay",
"pin0":
{
"log_name":"ClkB_pad.bb_inst/B",
"phy_name":"ClkB_pad.bb_inst/IOPAD"
},
"pin1":
{
"log_name":"ClkB_pad.bb_inst/O",
"phy_name":"ClkB_pad.bb_inst/PADDI"
},
"arrive":1.000,
"delay":1.000
},
{
"type":"net_delay",
"net":
{
"log_name":"MyCDC01/ClkB_c",
"phy_name":"ClkB_c"
},
"arrive":2.779,
"delay":1.779
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":2.779,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- --------------- ---------------- ------ --------------------- ------
ClkB top CLOCK LATENCY 0.000 0.000 1
ClkB NET DELAY 0.000 0.000 1
ClkB_pad.bb_inst/B->ClkB_pad.bb_inst/O SEIO33_CORE_J11 PADI_DEL 1.000 1.000 4
MyCDC01/ClkB_c NET DELAY 1.779 2.779 4
MyCDC01/A_Sig1_c.ff_inst/CLK CLOCK PIN 0.000 2.779 1
Data Path
{
"path_begin":
{
"type":"pin",
"log_name":"MyCDC01/A_Sig1_c.ff_inst/Q",
"phy_name":"MyCDC01.A_Sig1_c.SLICE_2/Q0"
},
"path_end":
{
"type":"pin",
"log_name":"out2_i1.ff_inst/DF",
"phy_name":"SLICE_4/DI0"
},
"path_sections":[
{
"type":"site_delay",
"pin0":
{
"log_name":"MyCDC01/A_Sig1_c.ff_inst/CLK",
"phy_name":"MyCDC01.A_Sig1_c.SLICE_2/CLK"
},
"pin1":
{
"log_name":"MyCDC01/A_Sig1_c.ff_inst/Q",
"phy_name":"MyCDC01.A_Sig1_c.SLICE_2/Q0"
},
"arrive":2.952,
"delay":0.173
},
{
"type":"net_delay",
"net":
{
"log_name":"MyCDC01/A_Sig1",
"phy_name":"A_Sig1"
},
"arrive":3.081,
"delay":0.129
},
{
"type":"site_delay",
"pin0":
{
"log_name":"i9_2_lut/B",
"phy_name":"SLICE_4/A0"
},
"pin1":
{
"log_name":"i9_2_lut/Z",
"phy_name":"SLICE_4/F0"
},
"arrive":3.197,
"delay":0.116
},
{
"type":"net_delay",
"net":
{
"log_name":"out2_c_N_2",
"phy_name":"out2_c_N_2"
},
"arrive":3.197,
"delay":0.000
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":3.197,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- --------------- ---------------- ------ --------------------- ------
MyCDC01/A_Sig1_c.ff_inst/CLK->MyCDC01/A_Sig1_c.ff_inst/Q
SLICE_R43C157D REG_DEL 0.173 2.952 1
MyCDC01/A_Sig1 NET DELAY 0.129 3.081 1
i9_2_lut/B->i9_2_lut/Z SLICE_R44C157D CTOF_DEL 0.116 3.197 1
out2_c_N_2 NET DELAY 0.000 3.197 1
out2_i1.ff_inst/DF ENDPOINT 0.000 3.197 1
Destination Clock Path
{
"path_begin":
{
"type":"port",
"log_name":"ClkB",
"phy_name":"ClkB"
},
"path_end":
{
"type":"pin",
"log_name":"out2_i1.ff_inst/CLK",
"phy_name":"SLICE_4/CLK"
},
"path_sections":[
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":0.000,
"delay":0.000
},
{
"type":"net_delay",
"net":
{
"log_name":"ClkB",
"phy_name":"ClkB"
},
"arrive":0.000,
"delay":0.000
},
{
"type":"site_delay",
"pin0":
{
"log_name":"ClkB_pad.bb_inst/B",
"phy_name":"ClkB_pad.bb_inst/IOPAD"
},
"pin1":
{
"log_name":"ClkB_pad.bb_inst/O",
"phy_name":"ClkB_pad.bb_inst/PADDI"
},
"arrive":1.000,
"delay":1.000
},
{
"type":"net_delay",
"net":
{
"log_name":"MyCDC01/ClkB_c",
"phy_name":"ClkB_c"
},
"arrive":2.898,
"delay":1.898
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":2.898,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- --------------- ---------------- ------ --------------------- ------
CONSTRAINT 0.000 0.000 1
ClkB top CLOCK LATENCY 0.000 0.000 1
ClkB NET DELAY 0.000 0.000 1
ClkB_pad.bb_inst/B->ClkB_pad.bb_inst/O SEIO33_CORE_J11 PADI_DEL 1.000 1.000 4
MyCDC01/ClkB_c NET DELAY 1.898 2.898 4
out2_i1.ff_inst/CLK CLOCK PIN 0.000 2.898 1
Uncertainty 0.000 2.898
Common Path Skew -0.105 2.793
Hold time 0.114 2.907
---------------------------------------- --------------- ---------------- ------ --------------------- ------
Required Time -2.907
Arrival Time 3.197
---------------------------------------- --------------- ---------------- ------ --------------------- ------
Path Slack (Passed) 0.290
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
End of Detailed Report for timing paths
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
##########################################################