POSTSYN: Post Synthesis Process Radiant Software (64-bit) 2023.2.1.288.0
Command Line: postsyn -a LIFCL -p LIFCL-17 -t QFN72 -sp 9_High-Performance_1.0V -oc Commercial -top -w -o lab03_impl_1_syn.udb -ldc C:/Users/ssyahril/Downloads/FAE_F2F_Training_Labs_V2/FAE_F2F_Training_Labs_V2/LAB_03/impl_1/lab03_impl_1.ldc -gui -msgset C:/Users/ssyahril/Downloads/FAE_F2F_Training_Labs_V2/FAE_F2F_Training_Labs_V2/LAB_03/promote.xml lab03_impl_1.vm 
   Architecture:     LIFCL
   Device:           LIFCL-17
   Package:          QFN72
   Performance:      9_High-Performance_1.0V
Reading input file 'lab03_impl_1.vm' ...
Reading constraint file 'C:/Users/ssyahril/Downloads/FAE_F2F_Training_Labs_V2/FAE_F2F_Training_Labs_V2/LAB_03/impl_1/lab03_impl_1.ldc' ...
Removing unused logic ...
INFO <35811146> - Signal GSR_INST.GSROUT undriven or does not drive anything - clipped
Starting design annotation....
 
Constraint Summary:
   Total number of constraints: 2
   Total number of constraints dropped: 0
 
Writing output file 'lab03_impl_1_syn.udb'.
POSTSYN finished successfully.
Total CPU Time: 0 secs 
Total REAL Time: 0 secs 
Peak Memory Usage: 188 MB
Checksum -- postsyn: 8b67ffb79068073b2cf76da9911ac0595a3fae41