Timing Report
Lattice Timing Report -  Setup  and Hold, Version Radiant Software (64-bit) 2022.1.1.289.4

Wed Apr 12 08:47:28 2023

Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp.   All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
Copyright (c) 2001 Agere Systems   All rights reserved.
Copyright (c) 2002-2022 Lattice Semiconductor Corporation,  All rights reserved.

Command line:    timing -sethld -v 10 -u 10 -endpoints 10 -nperend 1 -html -rpt LAB01_impl_1.tws LAB01_impl_1_syn.udb -gui

-------------------------------------------
Design:          top
Family:          LFCPNX
Device:          LFCPNX-50
Package:         CBG256
Performance:     9_High-Performance_1.0V
Package Status:                     Final          Version 16
-------------------------------------------


=====================================================================
                    Table of Contents
=====================================================================
  • 1 DESIGN CHECKING
  • 1.1 SDC Constraints
  • 1.2 Constraint Coverage
  • 1.3 Overall Summary
  • 1.4 Unconstrained Report
  • 1.5 Combinational Loop
  • 2 Setup at Speed Grade 9_High-Performance_1.0V Corner at 85 Degrees
  • 2.1 Clock Summary
  • 2.2 Endpoint slacks
  • 2.3 Detailed Report
  • 3 Hold at Speed Grade M Corner at 85 Degrees
  • 3.1 Endpoint slacks
  • 3.2 Detailed Report
  • ===================================================================== End of Table of Contents ===================================================================== 1 DESIGN CHECKING 1.1 SDC Constraints create_generated_clock -name {clk2} -source [get_pins {MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK}] -multiply_by 2 [get_pins {MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS }] create_generated_clock -name {clk1} -source [get_pins {MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK}] -multiply_by 2 [get_pins {MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP }] create_clock -name {Clk} -period 20 [get_ports Clk] 1.2 Constraint Coverage Constraint Coverage: 40% 1.3 Overall Summary Setup at Speed Grade 9_High-Performance_1.0V Corner at 85 Degrees Timing Errors: 0 endpoints; Total Negative Slack: 0.000 ns Hold at Speed Grade M Corner at 85 Degrees Timing Errors: 0 endpoints; Total Negative Slack: 0.000 ns 1.4 Unconstrained Report 1.4.1 Unconstrained Start/End Points Clocked but unconstrained timing start points ------------------------------------------------------------------- Listing 2 Start Points | Type ------------------------------------------------------------------- B_sig1.ff_inst/Q | No required time A_Sig1.ff_inst/Q | No required time ------------------------------------------------------------------- | Number of unconstrained timing start po | ints | 2 | ------------------------------------------------------------------- Clocked but unconstrained timing end points ------------------------------------------------------------------- Listing 2 End Points | Type ------------------------------------------------------------------- A_Sig_c.ff_inst/DF | No arrival time B_sig_c.ff_inst/DF | No arrival time ------------------------------------------------------------------- | Number of unconstrained timing end poin | ts | 2 | ------------------------------------------------------------------- 1.4.2 Start/End Points Without Timing Constraints I/O ports without constraint ---------------------------- Possible constraints to use on I/O ports are: set_input_delay, set_output_delay, set_max_delay, create_clock, create_generated_clock, ... ------------------------------------------------------------------- Listing 4 Start or End Points | Type ------------------------------------------------------------------- A | input B | input out1 | output out2 | output ------------------------------------------------------------------- | Number of I/O ports without constraint | 4 | ------------------------------------------------------------------- Nets without clock definition Define a clock on a top level port or a generated clock on a clock divider pin associated with this net(s). -------------------------------------------------- There is no instance satisfying reporting criteria 1.5 Combinational Loop None 2 Setup at Speed Grade 9_High-Performance_1.0V Corner at 85 Degrees 2.1 Clock Summary 2.1.1 Clock "clk1" create_generated_clock -name {clk1} -source [get_pins {MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK}] -multiply_by 2 [get_pins {MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP }] Single Clock Domain ------------------------------------------------------------------------------------------------------- Clock clk1 | | Period | Frequency ------------------------------------------------------------------------------------------------------- From clk1 | Target | 10.000 ns | 100.000 MHz | Actual (all paths) | 1.000 ns | 1000.000 MHz A_Sig_c.ff_inst/CLK (MPW) | (50% duty cycle) | 1.000 ns | 1000.000 MHz ------------------------------------------------------------------------------------------------------- Clock Domain Crossing ------------------------------------------------------------------------------------------------------ Clock clk1 | Worst Time Between Edges | Comment ------------------------------------------------------------------------------------------------------ From clk2 | ---- | No path From Clk | ---- | No path ------------------------------------------------------------------------------------------------------ 2.1.2 Clock "clk2" create_generated_clock -name {clk2} -source [get_pins {MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK}] -multiply_by 2 [get_pins {MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS }] Single Clock Domain ------------------------------------------------------------------------------------------------------- Clock clk2 | | Period | Frequency ------------------------------------------------------------------------------------------------------- From clk2 | Target | 10.000 ns | 100.000 MHz | Actual (all paths) | 1.082 ns | 924.214 MHz B_sig1.ff_inst/CLK (MPW) | (50% duty cycle) | 1.000 ns | 1000.000 MHz ------------------------------------------------------------------------------------------------------- Clock Domain Crossing ------------------------------------------------------------------------------------------------------ Clock clk2 | Worst Time Between Edges | Comment ------------------------------------------------------------------------------------------------------ From clk1 | 2.500 ns | slack = 1.204 ns From Clk | ---- | No path ------------------------------------------------------------------------------------------------------ 2.1.3 Clock "Clk" create_clock -name {Clk} -period 20 [get_ports Clk] Single Clock Domain ------------------------------------------------------------------------------------------------------- Clock Clk | | Period | Frequency ------------------------------------------------------------------------------------------------------- From Clk | Target | 20.000 ns | 50.000 MHz | Actual (all paths) | 5.000 ns | 200.000 MHz Clk_pad.bb_inst/B (MPW) | (50% duty cycle) | 5.000 ns | 200.000 MHz ------------------------------------------------------------------------------------------------------- Clock Domain Crossing ------------------------------------------------------------------------------------------------------ Clock Clk | Worst Time Between Edges | Comment ------------------------------------------------------------------------------------------------------ From clk1 | ---- | No path From clk2 | ---- | No path ------------------------------------------------------------------------------------------------------ 2.2 Endpoint slacks ------------------------------------------------------- Listing 2 End Points | Slack ------------------------------------------------------- B_sig1.ff_inst/DF | 1.204 ns A_Sig1.ff_inst/DF | 9.324 ns ------------------------------------------------------- | Setup # of endpoints with negative slack:| 0 | ------------------------------------------------------- 2.3 Detailed Report XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX Detail report of critical paths XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Detailed Report for timing paths +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ ++++Path 1 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Path Begin : A_Sig_c.ff_inst/Q (SLICEREG) Path End : B_sig1.ff_inst/DF (SLICEREG) Source Clock : clk1 (R) Destination Clock: clk2 (R) Logic Level : 2 Delay Ratio : 57.8% (route), 42.2% (logic) Clock Skew : -0.107 ns Setup Constraint : 2.500 ns Path Slack : 1.203 ns (Passed) Source Clock Path { "path_begin": { "type":"port", "log_name":"Clk", "phy_name":"Clk" }, "path_end": { "type":"pin", "log_name":"A_Sig_c.ff_inst/CLK", "phy_name":"A_Sig_c.ff_inst/CLK" }, "path_sections":[ { "type":"net_delay", "net": { "log_name":"Clk", "phy_name":"Clk" }, "arrive":0.000, "delay":0.000 }, { "type":"site_delay", "pin0": { "log_name":"Clk_pad.bb_inst/B", "phy_name":"Clk_pad.bb_inst/B" }, "pin1": { "log_name":"Clk_pad.bb_inst/O", "phy_name":"Clk_pad.bb_inst/O" }, "arrive":1.366, "delay":1.366 }, { "type":"net_delay", "net": { "log_name":"Clk_c", "phy_name":"Clk_c" }, "arrive":1.666, "delay":0.300 }, { "type":"site_delay", "pin0": { "log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK", "phy_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK" }, "pin1": { "log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP", "phy_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP" }, "arrive":1.666, "delay":0.000 }, { "type":"site_delay", "pin0": { "log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK", "phy_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK" }, "pin1": { "log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP", "phy_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP" }, "arrive":1.152, "delay":-0.514 }, { "type":"net_delay", "net": { "log_name":"clk1", "phy_name":"clk1" }, "arrive":1.666, "delay":0.514 } ] } Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- -------------- ------------- --------- --------------------- ------ Clk top CLOCK LATENCY 0.000 0.000 1 Clk NET DELAY 0.000 0.000 1 Clk_pad.bb_inst/B->Clk_pad.bb_inst/O BB PADI_DEL 1.366 1.366 1 Clk_c NET DELAY 0.300 1.666 1 MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK->MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP PLL_CORE 0.000 1.666 3 MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK->MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP (TOTAL_ADJUSTMENTS) PLL_CORE -0.514 1.152 3 clk1 NET DELAY 0.514 1.666 3 Data Path { "path_begin": { "type":"pin", "log_name":"A_Sig_c.ff_inst/Q", "phy_name":"A_Sig_c.ff_inst/Q" }, "path_end": { "type":"pin", "log_name":"B_sig1.ff_inst/DF", "phy_name":"B_sig1.ff_inst/DF" }, "path_sections":[ { "type":"site_delay", "pin0": { "log_name":"A_Sig_c.ff_inst/CLK", "phy_name":"A_Sig_c.ff_inst/CLK" }, "pin1": { "log_name":"A_Sig_c.ff_inst/Q", "phy_name":"A_Sig_c.ff_inst/Q" }, "arrive":1.970, "delay":0.304 }, { "type":"net_delay", "net": { "log_name":"A_Sig", "phy_name":"A_Sig" }, "arrive":2.377, "delay":0.407 }, { "type":"site_delay", "pin0": { "log_name":"B_sig_I_2_2_lut/B", "phy_name":"B_sig_I_2_2_lut/B" }, "pin1": { "log_name":"B_sig_I_2_2_lut/Z", "phy_name":"B_sig_I_2_2_lut/Z" }, "arrive":2.590, "delay":0.213 }, { "type":"net_delay", "net": { "log_name":"out2_N_1", "phy_name":"out2_N_1" }, "arrive":2.890, "delay":0.300 } ] } Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- -------------- ------------- --------- --------------------- ------ A_Sig_c.ff_inst/CLK->A_Sig_c.ff_inst/Q SLICEREG REG_DEL 0.304 1.970 2 A_Sig NET DELAY 0.407 2.377 2 B_sig_I_2_2_lut/B->B_sig_I_2_2_lut/Z LUT4 CTOF_DEL 0.213 2.590 1 out2_N_1 ( DF ) NET DELAY 0.300 2.890 1 Destination Clock Path { "path_begin": { "type":"port", "log_name":"Clk", "phy_name":"Clk" }, "path_end": { "type":"pin", "log_name":"B_sig1.ff_inst/CLK", "phy_name":"B_sig1.ff_inst/CLK" }, "path_sections":[ { "type":"site_delay", "pin0": { "log_name":"", "phy_name":"" }, "pin1": { "log_name":"", "phy_name":"" }, "arrive":2.500, "delay":0.000 }, { "type":"net_delay", "net": { "log_name":"Clk", "phy_name":"Clk" }, "arrive":2.500, "delay":0.000 }, { "type":"site_delay", "pin0": { "log_name":"Clk_pad.bb_inst/B", "phy_name":"Clk_pad.bb_inst/B" }, "pin1": { "log_name":"Clk_pad.bb_inst/O", "phy_name":"Clk_pad.bb_inst/O" }, "arrive":3.866, "delay":1.366 }, { "type":"net_delay", "net": { "log_name":"Clk_c", "phy_name":"Clk_c" }, "arrive":4.166, "delay":0.300 }, { "type":"site_delay", "pin0": { "log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK", "phy_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK" }, "pin1": { "log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS", "phy_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS" }, "arrive":4.166, "delay":0.000 }, { "type":"site_delay", "pin0": { "log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK", "phy_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK" }, "pin1": { "log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS", "phy_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS" }, "arrive":3.651, "delay":-0.514 }, { "type":"net_delay", "net": { "log_name":"clk2", "phy_name":"clk2" }, "arrive":4.058, "delay":0.407 } ] } Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- -------------- ------------- --------- --------------------- ------ CONSTRAINT 0.000 2.500 1 Clk top CLOCK LATENCY 0.000 2.500 1 Clk NET DELAY 0.000 2.500 1 Clk_pad.bb_inst/B->Clk_pad.bb_inst/O BB PADI_DEL 1.366 3.866 1 Clk_c NET DELAY 0.300 4.166 1 MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK->MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS PLL_CORE 0.000 4.166 2 MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK->MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS (TOTAL_ADJUSTMENTS) PLL_CORE -0.514 3.651 2 clk2 ( CLK ) NET DELAY 0.407 4.058 2 Uncertainty -(0.000) 4.058 Setup time -(-0.035) 4.093 ---------------------------------------- -------------- ------------- --------- --------------------- ------ Required Time 4.093 Arrival Time -(2.890) ---------------------------------------- -------------- ------------- --------- --------------------- ------ Path Slack (Passed) 1.203 ++++ Path 2 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Path Begin : A_Sig_c.ff_inst/Q (SLICEREG) Path End : A_Sig1.ff_inst/DF (SLICEREG) Source Clock : clk1 (R) Destination Clock: clk1 (R) Logic Level : 1 Delay Ratio : 57.2% (route), 42.8% (logic) Clock Skew : 0.000 ns Setup Constraint : 10.000 ns Path Slack : 9.324 ns (Passed) Source Clock Path { "path_begin": { "type":"port", "log_name":"Clk", "phy_name":"Clk" }, "path_end": { "type":"pin", "log_name":"A_Sig_c.ff_inst/CLK", "phy_name":"A_Sig_c.ff_inst/CLK" }, "path_sections":[ { "type":"net_delay", "net": { "log_name":"Clk", "phy_name":"Clk" }, "arrive":0.000, "delay":0.000 }, { "type":"site_delay", "pin0": { "log_name":"Clk_pad.bb_inst/B", "phy_name":"Clk_pad.bb_inst/B" }, "pin1": { "log_name":"Clk_pad.bb_inst/O", "phy_name":"Clk_pad.bb_inst/O" }, "arrive":1.366, "delay":1.366 }, { "type":"net_delay", "net": { "log_name":"Clk_c", "phy_name":"Clk_c" }, "arrive":1.666, "delay":0.300 }, { "type":"site_delay", "pin0": { "log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK", "phy_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK" }, "pin1": { "log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP", "phy_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP" }, "arrive":1.666, "delay":0.000 }, { "type":"site_delay", "pin0": { "log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK", "phy_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK" }, "pin1": { "log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP", "phy_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP" }, "arrive":1.152, "delay":-0.514 }, { "type":"net_delay", "net": { "log_name":"clk1", "phy_name":"clk1" }, "arrive":1.666, "delay":0.514 } ] } Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- -------------- ------------- --------- --------------------- ------ Clk top CLOCK LATENCY 0.000 0.000 1 Clk NET DELAY 0.000 0.000 1 Clk_pad.bb_inst/B->Clk_pad.bb_inst/O BB PADI_DEL 1.366 1.366 1 Clk_c NET DELAY 0.300 1.666 1 MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK->MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP PLL_CORE 0.000 1.666 3 MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK->MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP (TOTAL_ADJUSTMENTS) PLL_CORE -0.514 1.152 3 clk1 NET DELAY 0.514 1.666 3 Data Path { "path_begin": { "type":"pin", "log_name":"A_Sig_c.ff_inst/Q", "phy_name":"A_Sig_c.ff_inst/Q" }, "path_end": { "type":"pin", "log_name":"A_Sig1.ff_inst/DF", "phy_name":"A_Sig1.ff_inst/DF" }, "path_sections":[ { "type":"site_delay", "pin0": { "log_name":"A_Sig_c.ff_inst/CLK", "phy_name":"A_Sig_c.ff_inst/CLK" }, "pin1": { "log_name":"A_Sig_c.ff_inst/Q", "phy_name":"A_Sig_c.ff_inst/Q" }, "arrive":1.970, "delay":0.304 }, { "type":"net_delay", "net": { "log_name":"A_Sig", "phy_name":"A_Sig" }, "arrive":2.377, "delay":0.407 } ] } Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- -------------- ------------- --------- --------------------- ------ A_Sig_c.ff_inst/CLK->A_Sig_c.ff_inst/Q SLICEREG REG_DEL 0.304 1.970 2 A_Sig ( DF ) NET DELAY 0.407 2.377 2 Destination Clock Path { "path_begin": { "type":"port", "log_name":"Clk", "phy_name":"Clk" }, "path_end": { "type":"pin", "log_name":"A_Sig1.ff_inst/CLK", "phy_name":"A_Sig1.ff_inst/CLK" }, "path_sections":[ { "type":"site_delay", "pin0": { "log_name":"", "phy_name":"" }, "pin1": { "log_name":"", "phy_name":"" }, "arrive":10.000, "delay":0.000 }, { "type":"net_delay", "net": { "log_name":"Clk", "phy_name":"Clk" }, "arrive":10.000, "delay":0.000 }, { "type":"site_delay", "pin0": { "log_name":"Clk_pad.bb_inst/B", "phy_name":"Clk_pad.bb_inst/B" }, "pin1": { "log_name":"Clk_pad.bb_inst/O", "phy_name":"Clk_pad.bb_inst/O" }, "arrive":11.366, "delay":1.366 }, { "type":"net_delay", "net": { "log_name":"Clk_c", "phy_name":"Clk_c" }, "arrive":11.666, "delay":0.300 }, { "type":"site_delay", "pin0": { "log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK", "phy_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK" }, "pin1": { "log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP", "phy_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP" }, "arrive":11.666, "delay":0.000 }, { "type":"site_delay", "pin0": { "log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK", "phy_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK" }, "pin1": { "log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP", "phy_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP" }, "arrive":11.152, "delay":-0.514 }, { "type":"net_delay", "net": { "log_name":"clk1", "phy_name":"clk1" }, "arrive":11.666, "delay":0.514 } ] } Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- -------------- ------------- --------- --------------------- ------ CONSTRAINT 0.000 10.000 1 Clk top CLOCK LATENCY 0.000 10.000 1 Clk NET DELAY 0.000 10.000 1 Clk_pad.bb_inst/B->Clk_pad.bb_inst/O BB PADI_DEL 1.366 11.366 1 Clk_c NET DELAY 0.300 11.666 1 MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK->MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP PLL_CORE 0.000 11.666 3 MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK->MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP (TOTAL_ADJUSTMENTS) PLL_CORE -0.514 11.152 3 clk1 ( CLK ) NET DELAY 0.514 11.666 3 Uncertainty -(0.000) 11.666 Setup time -(-0.035) 11.701 ---------------------------------------- -------------- ------------- --------- --------------------- ------ Required Time 11.701 Arrival Time -(2.377) ---------------------------------------- -------------- ------------- --------- --------------------- ------ Path Slack (Passed) 9.324 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ End of Detailed Report for timing paths +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ ########################################################## 3 Hold at Speed Grade M Corner at 85 Degrees 3.1 Endpoint slacks ------------------------------------------------------- Listing 2 End Points | Slack ------------------------------------------------------- A_Sig1.ff_inst/DF | 0.535 ns B_sig1.ff_inst/DF | 0.906 ns ------------------------------------------------------- | Hold # of endpoints with negative slack: | 0 | ------------------------------------------------------- 3.2 Detailed Report XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX Detail report of critical paths XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Detailed Report for timing paths +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ ++++Path 1 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Path Begin : A_Sig_c.ff_inst/Q (SLICEREG) Path End : A_Sig1.ff_inst/DF (SLICEREG) Source Clock : clk1 (R) Destination Clock: clk1 (R) Logic Level : 1 Delay Ratio : 60.0% (route), 40.0% (logic) Clock Skew : 0.000 ns Hold Constraint : 0.000 ns Path Slack : 0.535 ns (Passed) Source Clock Path { "path_begin": { "type":"port", "log_name":"Clk", "phy_name":"Clk" }, "path_end": { "type":"pin", "log_name":"A_Sig_c.ff_inst/CLK", "phy_name":"A_Sig_c.ff_inst/CLK" }, "path_sections":[ { "type":"net_delay", "net": { "log_name":"Clk", "phy_name":"Clk" }, "arrive":0.000, "delay":0.000 }, { "type":"site_delay", "pin0": { "log_name":"Clk_pad.bb_inst/B", "phy_name":"Clk_pad.bb_inst/B" }, "pin1": { "log_name":"Clk_pad.bb_inst/O", "phy_name":"Clk_pad.bb_inst/O" }, "arrive":1.366, "delay":1.366 }, { "type":"net_delay", "net": { "log_name":"Clk_c", "phy_name":"Clk_c" }, "arrive":1.666, "delay":0.300 }, { "type":"site_delay", "pin0": { "log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK", "phy_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK" }, "pin1": { "log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP", "phy_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP" }, "arrive":1.666, "delay":0.000 }, { "type":"site_delay", "pin0": { "log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK", "phy_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK" }, "pin1": { "log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP", "phy_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP" }, "arrive":1.152, "delay":-0.514 }, { "type":"net_delay", "net": { "log_name":"clk1", "phy_name":"clk1" }, "arrive":1.666, "delay":0.514 } ] } Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- -------------- ------------- ------ --------------------- ------ Clk top CLOCK LATENCY 0.000 0.000 1 Clk NET DELAY 0.000 0.000 1 Clk_pad.bb_inst/B->Clk_pad.bb_inst/O BB PADI_DEL 1.366 1.366 1 Clk_c NET DELAY 0.300 1.666 1 MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK->MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP PLL_CORE 0.000 1.666 3 MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK->MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP (TOTAL_ADJUSTMENTS) PLL_CORE -0.514 1.152 3 clk1 NET DELAY 0.514 1.666 3 Data Path { "path_begin": { "type":"pin", "log_name":"A_Sig_c.ff_inst/Q", "phy_name":"A_Sig_c.ff_inst/Q" }, "path_end": { "type":"pin", "log_name":"A_Sig1.ff_inst/DF", "phy_name":"A_Sig1.ff_inst/DF" }, "path_sections":[ { "type":"site_delay", "pin0": { "log_name":"A_Sig_c.ff_inst/CLK", "phy_name":"A_Sig_c.ff_inst/CLK" }, "pin1": { "log_name":"A_Sig_c.ff_inst/Q", "phy_name":"A_Sig_c.ff_inst/Q" }, "arrive":1.937, "delay":0.271 }, { "type":"net_delay", "net": { "log_name":"A_Sig", "phy_name":"A_Sig" }, "arrive":2.344, "delay":0.407 } ] } Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- -------------- ------------- ------ --------------------- ------ A_Sig_c.ff_inst/CLK->A_Sig_c.ff_inst/Q SLICEREG REG_DEL 0.271 1.937 2 A_Sig ( DF ) NET DELAY 0.407 2.344 2 Destination Clock Path { "path_begin": { "type":"port", "log_name":"Clk", "phy_name":"Clk" }, "path_end": { "type":"pin", "log_name":"A_Sig1.ff_inst/CLK", "phy_name":"A_Sig1.ff_inst/CLK" }, "path_sections":[ { "type":"site_delay", "pin0": { "log_name":"", "phy_name":"" }, "pin1": { "log_name":"", "phy_name":"" }, "arrive":0.000, "delay":0.000 }, { "type":"net_delay", "net": { "log_name":"Clk", "phy_name":"Clk" }, "arrive":0.000, "delay":0.000 }, { "type":"site_delay", "pin0": { "log_name":"Clk_pad.bb_inst/B", "phy_name":"Clk_pad.bb_inst/B" }, "pin1": { "log_name":"Clk_pad.bb_inst/O", "phy_name":"Clk_pad.bb_inst/O" }, "arrive":1.366, "delay":1.366 }, { "type":"net_delay", "net": { "log_name":"Clk_c", "phy_name":"Clk_c" }, "arrive":1.666, "delay":0.300 }, { "type":"site_delay", "pin0": { "log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK", "phy_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK" }, "pin1": { "log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP", "phy_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP" }, "arrive":1.666, "delay":0.000 }, { "type":"site_delay", "pin0": { "log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK", "phy_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK" }, "pin1": { "log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP", "phy_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP" }, "arrive":1.152, "delay":-0.514 }, { "type":"net_delay", "net": { "log_name":"clk1", "phy_name":"clk1" }, "arrive":1.666, "delay":0.514 } ] } Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- -------------- ------------- ------ --------------------- ------ CONSTRAINT 0.000 0.000 1 Clk top CLOCK LATENCY 0.000 0.000 1 Clk NET DELAY 0.000 0.000 1 Clk_pad.bb_inst/B->Clk_pad.bb_inst/O BB PADI_DEL 1.366 1.366 1 Clk_c NET DELAY 0.300 1.666 1 MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK->MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP PLL_CORE 0.000 1.666 3 MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK->MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP (TOTAL_ADJUSTMENTS) PLL_CORE -0.514 1.152 3 clk1 ( CLK ) NET DELAY 0.514 1.666 3 Uncertainty 0.000 1.666 Hold time 0.143 1.809 ---------------------------------------- -------------- ------------- ------ --------------------- ------ Required Time -1.809 Arrival Time 2.344 ---------------------------------------- -------------- ------------- ------ --------------------- ------ Path Slack (Passed) 0.535 ++++ Path 2 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Path Begin : B_sig_c.ff_inst/Q (SLICEREG) Path End : B_sig1.ff_inst/DF (SLICEREG) Source Clock : clk2 (R) Destination Clock: clk2 (R) Logic Level : 2 Delay Ratio : 57.1% (route), 42.9% (logic) Clock Skew : 0.000 ns Hold Constraint : 0.000 ns Path Slack : 0.906 ns (Passed) Source Clock Path { "path_begin": { "type":"port", "log_name":"Clk", "phy_name":"Clk" }, "path_end": { "type":"pin", "log_name":"B_sig_c.ff_inst/CLK", "phy_name":"B_sig_c.ff_inst/CLK" }, "path_sections":[ { "type":"net_delay", "net": { "log_name":"Clk", "phy_name":"Clk" }, "arrive":0.000, "delay":0.000 }, { "type":"site_delay", "pin0": { "log_name":"Clk_pad.bb_inst/B", "phy_name":"Clk_pad.bb_inst/B" }, "pin1": { "log_name":"Clk_pad.bb_inst/O", "phy_name":"Clk_pad.bb_inst/O" }, "arrive":1.366, "delay":1.366 }, { "type":"net_delay", "net": { "log_name":"Clk_c", "phy_name":"Clk_c" }, "arrive":1.666, "delay":0.300 }, { "type":"site_delay", "pin0": { "log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK", "phy_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK" }, "pin1": { "log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS", "phy_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS" }, "arrive":1.666, "delay":0.000 }, { "type":"site_delay", "pin0": { "log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK", "phy_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK" }, "pin1": { "log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS", "phy_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS" }, "arrive":1.151, "delay":-0.514 }, { "type":"net_delay", "net": { "log_name":"clk2", "phy_name":"clk2" }, "arrive":1.558, "delay":0.407 } ] } Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- -------------- ------------- ------ --------------------- ------ Clk top CLOCK LATENCY 0.000 0.000 1 Clk NET DELAY 0.000 0.000 1 Clk_pad.bb_inst/B->Clk_pad.bb_inst/O BB PADI_DEL 1.366 1.366 1 Clk_c NET DELAY 0.300 1.666 1 MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK->MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS PLL_CORE 0.000 1.666 2 MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK->MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS (TOTAL_ADJUSTMENTS) PLL_CORE -0.514 1.151 2 clk2 NET DELAY 0.407 1.558 2 Data Path { "path_begin": { "type":"pin", "log_name":"B_sig_c.ff_inst/Q", "phy_name":"B_sig_c.ff_inst/Q" }, "path_end": { "type":"pin", "log_name":"B_sig1.ff_inst/DF", "phy_name":"B_sig1.ff_inst/DF" }, "path_sections":[ { "type":"site_delay", "pin0": { "log_name":"B_sig_c.ff_inst/CLK", "phy_name":"B_sig_c.ff_inst/CLK" }, "pin1": { "log_name":"B_sig_c.ff_inst/Q", "phy_name":"B_sig_c.ff_inst/Q" }, "arrive":1.830, "delay":0.271 }, { "type":"net_delay", "net": { "log_name":"B_sig", "phy_name":"B_sig" }, "arrive":2.130, "delay":0.300 }, { "type":"site_delay", "pin0": { "log_name":"B_sig_I_2_2_lut/A", "phy_name":"B_sig_I_2_2_lut/A" }, "pin1": { "log_name":"B_sig_I_2_2_lut/Z", "phy_name":"B_sig_I_2_2_lut/Z" }, "arrive":2.309, "delay":0.179 }, { "type":"net_delay", "net": { "log_name":"out2_N_1", "phy_name":"out2_N_1" }, "arrive":2.609, "delay":0.300 } ] } Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- -------------- ------------- ------ --------------------- ------ B_sig_c.ff_inst/CLK->B_sig_c.ff_inst/Q SLICEREG REG_DEL 0.271 1.830 1 B_sig NET DELAY 0.300 2.130 1 B_sig_I_2_2_lut/A->B_sig_I_2_2_lut/Z LUT4 CTOF_DEL 0.179 2.309 1 out2_N_1 ( DF ) NET DELAY 0.300 2.609 1 Destination Clock Path { "path_begin": { "type":"port", "log_name":"Clk", "phy_name":"Clk" }, "path_end": { "type":"pin", "log_name":"B_sig1.ff_inst/CLK", "phy_name":"B_sig1.ff_inst/CLK" }, "path_sections":[ { "type":"site_delay", "pin0": { "log_name":"", "phy_name":"" }, "pin1": { "log_name":"", "phy_name":"" }, "arrive":0.000, "delay":0.000 }, { "type":"net_delay", "net": { "log_name":"Clk", "phy_name":"Clk" }, "arrive":0.000, "delay":0.000 }, { "type":"site_delay", "pin0": { "log_name":"Clk_pad.bb_inst/B", "phy_name":"Clk_pad.bb_inst/B" }, "pin1": { "log_name":"Clk_pad.bb_inst/O", "phy_name":"Clk_pad.bb_inst/O" }, "arrive":1.366, "delay":1.366 }, { "type":"net_delay", "net": { "log_name":"Clk_c", "phy_name":"Clk_c" }, "arrive":1.666, "delay":0.300 }, { "type":"site_delay", "pin0": { "log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK", "phy_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK" }, "pin1": { "log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS", "phy_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS" }, "arrive":1.666, "delay":0.000 }, { "type":"site_delay", "pin0": { "log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK", "phy_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK" }, "pin1": { "log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS", "phy_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS" }, "arrive":1.151, "delay":-0.514 }, { "type":"net_delay", "net": { "log_name":"clk2", "phy_name":"clk2" }, "arrive":1.558, "delay":0.407 } ] } Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- -------------- ------------- ------ --------------------- ------ CONSTRAINT 0.000 0.000 1 Clk top CLOCK LATENCY 0.000 0.000 1 Clk NET DELAY 0.000 0.000 1 Clk_pad.bb_inst/B->Clk_pad.bb_inst/O BB PADI_DEL 1.366 1.366 1 Clk_c NET DELAY 0.300 1.666 1 MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK->MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS PLL_CORE 0.000 1.666 2 MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK->MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS (TOTAL_ADJUSTMENTS) PLL_CORE -0.514 1.151 2 clk2 ( CLK ) NET DELAY 0.407 1.558 2 Uncertainty 0.000 1.558 Hold time 0.144 1.702 ---------------------------------------- -------------- ------------- ------ --------------------- ------ Required Time -1.702 Arrival Time 2.608 ---------------------------------------- -------------- ------------- ------ --------------------- ------ Path Slack (Passed) 0.906 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ End of Detailed Report for timing paths +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ ##########################################################

















































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